File: /usr/src/linux/drivers/scsi/sym53c8xx_defs.h
1 /******************************************************************************
2 ** High Performance device driver for the Symbios 53C896 controller.
3 **
4 ** Copyright (C) 1998-2000 Gerard Roudier <groudier@club-internet.fr>
5 **
6 ** This driver also supports all the Symbios 53C8XX controller family,
7 ** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8 ** revisions of 53C815 controllers.
9 **
10 ** This driver is based on the Linux port of the FreeBSD ncr driver.
11 **
12 ** Copyright (C) 1994 Wolfgang Stanglmeier
13 **
14 **-----------------------------------------------------------------------------
15 **
16 ** This program is free software; you can redistribute it and/or modify
17 ** it under the terms of the GNU General Public License as published by
18 ** the Free Software Foundation; either version 2 of the License, or
19 ** (at your option) any later version.
20 **
21 ** This program is distributed in the hope that it will be useful,
22 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ** GNU General Public License for more details.
25 **
26 ** You should have received a copy of the GNU General Public License
27 ** along with this program; if not, write to the Free Software
28 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 **
30 **-----------------------------------------------------------------------------
31 **
32 ** The Linux port of the FreeBSD ncr driver has been achieved in
33 ** november 1995 by:
34 **
35 ** Gerard Roudier <groudier@club-internet.fr>
36 **
37 ** Being given that this driver originates from the FreeBSD version, and
38 ** in order to keep synergy on both, any suggested enhancements and corrections
39 ** received on Linux are automatically a potential candidate for the FreeBSD
40 ** version.
41 **
42 ** The original driver has been written for 386bsd and FreeBSD by
43 ** Wolfgang Stanglmeier <wolf@cologne.de>
44 ** Stefan Esser <se@mi.Uni-Koeln.de>
45 **
46 **-----------------------------------------------------------------------------
47 **
48 ** Major contributions:
49 ** --------------------
50 **
51 ** NVRAM detection and reading.
52 ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
53 **
54 *******************************************************************************
55 */
56
57 #ifndef SYM53C8XX_DEFS_H
58 #define SYM53C8XX_DEFS_H
59
60 /*
61 ** Check supported Linux versions
62 */
63
64 #if !defined(LINUX_VERSION_CODE)
65 #include <linux/version.h>
66 #endif
67 #include <linux/config.h>
68
69 #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
70
71 /*
72 * NCR PQS/PDS special device support.
73 */
74 #ifdef CONFIG_SCSI_NCR53C8XX_PQS_PDS
75 #define SCSI_NCR_PQS_PDS_SUPPORT
76 #endif
77
78 /*
79 * No more an option, enabled by default.
80 */
81 #ifndef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
82 #define CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
83 #endif
84
85 /*
86 ** These options are not tunable from 'make config'
87 */
88 #define SCSI_NCR_PROC_INFO_SUPPORT
89
90 /*
91 ** If you want a driver as small as possible, donnot define the
92 ** following options.
93 */
94 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
95 #define SCSI_NCR_DEBUG_INFO_SUPPORT
96 #define SCSI_NCR_PCI_FIX_UP_SUPPORT
97 #ifdef SCSI_NCR_PROC_INFO_SUPPORT
98 # define SCSI_NCR_USER_COMMAND_SUPPORT
99 # define SCSI_NCR_USER_INFO_SUPPORT
100 #endif
101
102 /*
103 ** To disable integrity checking, do not define the
104 ** following option.
105 */
106 #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
107 # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
108 #endif
109
110 /*==========================================================
111 **
112 ** nvram settings - #define SCSI_NCR_NVRAM_SUPPORT to enable
113 **
114 **==========================================================
115 */
116
117 #ifdef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
118 #define SCSI_NCR_NVRAM_SUPPORT
119 /* #define SCSI_NCR_DEBUG_NVRAM */
120 #endif
121
122 /* ---------------------------------------------------------------------
123 ** Take into account kernel configured parameters.
124 ** Most of these options can be overridden at startup by a command line.
125 ** ---------------------------------------------------------------------
126 */
127
128 /*
129 * For Ultra2 and Ultra3 SCSI support option, use special features.
130 *
131 * Value (default) means:
132 * bit 0 : all features enabled, except:
133 * bit 1 : PCI Write And Invalidate.
134 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
135 *
136 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
137 * enabled by the driver.
138 */
139 #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
140
141 #define SCSI_NCR_MAX_SYNC (80)
142
143 /*
144 * Allow tags from 2 to 256, default 8
145 */
146 #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
147 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
148 #define SCSI_NCR_MAX_TAGS (2)
149 #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
150 #define SCSI_NCR_MAX_TAGS (256)
151 #else
152 #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
153 #endif
154 #else
155 #define SCSI_NCR_MAX_TAGS (8)
156 #endif
157
158 /*
159 * Allow tagged command queuing support if configured with default number
160 * of tags set to max (see above).
161 */
162 #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
163 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
164 #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
165 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
166 #else
167 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
168 #endif
169
170 /*
171 * Use normal IO if configured. Forced for alpha.
172 */
173 #if defined(CONFIG_SCSI_NCR53C8XX_IOMAPPED)
174 #define SCSI_NCR_IOMAPPED
175 #elif defined(__alpha__)
176 #define SCSI_NCR_IOMAPPED
177 #elif defined(__powerpc__)
178 #if LINUX_VERSION_CODE <= LinuxVersionCode(2,4,3)
179 #define SCSI_NCR_IOMAPPED
180 #define SCSI_NCR_PCI_MEM_NOT_SUPPORTED
181 #endif
182 #elif defined(__sparc__)
183 #undef SCSI_NCR_IOMAPPED
184 #endif
185
186 /*
187 * Should we enable DAC cycles on Sparc64 platform?
188 * Until further investigation we do not enable it
189 * at the moment.
190 * We may want to enable it for __ia64__ (untested)
191 */
192 #if defined(__ia64__)
193 # if !defined(SCSI_NCR_USE_64BIT_DAC)
194 # define SCSI_NCR_USE_64BIT_DAC
195 # endif
196 #else
197 # undef SCSI_NCR_USE_64BIT_DAC
198 #endif
199
200 /*
201 * Immediate arbitration
202 */
203 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
204 #define SCSI_NCR_IARB_SUPPORT
205 #endif
206
207 /*
208 * Should we enable DAC cycles on sparc64 platforms?
209 * Until further investigation we do not enable it
210 * anywhere at the moment.
211 */
212 #undef SCSI_NCR_USE_64BIT_DAC
213
214 /*
215 * Sync transfer frequency at startup.
216 * Allow from 5Mhz to 80Mhz default 20 Mhz.
217 */
218 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
219 #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
220 #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
221 #undef CONFIG_SCSI_NCR53C8XX_SYNC
222 #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
223 #endif
224
225 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
226 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
227 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
228 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
229 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
230 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
231 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
232 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
233 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
234 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
235 #else
236 #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
237 #endif
238
239 /*
240 * Disallow disconnections at boot-up
241 */
242 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
243 #define SCSI_NCR_SETUP_DISCONNECTION (0)
244 #else
245 #define SCSI_NCR_SETUP_DISCONNECTION (1)
246 #endif
247
248 /*
249 * Force synchronous negotiation for all targets
250 */
251 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
252 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
253 #else
254 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
255 #endif
256
257 /*
258 * Disable master parity checking (flawed hardwares need that)
259 */
260 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
261 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
262 #else
263 #define SCSI_NCR_SETUP_MASTER_PARITY (1)
264 #endif
265
266 /*
267 * Disable scsi parity checking (flawed devices may need that)
268 */
269 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
270 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
271 #else
272 #define SCSI_NCR_SETUP_SCSI_PARITY (1)
273 #endif
274
275 /*
276 * Vendor specific stuff
277 */
278 #ifdef CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT
279 #define SCSI_NCR_SETUP_LED_PIN (1)
280 #define SCSI_NCR_SETUP_DIFF_SUPPORT (4)
281 #else
282 #define SCSI_NCR_SETUP_LED_PIN (0)
283 #define SCSI_NCR_SETUP_DIFF_SUPPORT (0)
284 #endif
285
286 /*
287 * Settle time after reset at boot-up
288 */
289 #define SCSI_NCR_SETUP_SETTLE_TIME (2)
290
291 /*
292 ** Bridge quirks work-around option defaulted to 1.
293 */
294 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
295 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
296 #endif
297
298 /*
299 ** Work-around common bridge misbehaviour.
300 **
301 ** - Do not flush posted writes in the opposite
302 ** direction on read.
303 ** - May reorder DMA writes to memory.
304 **
305 ** This option should not affect performances
306 ** significantly, so it is the default.
307 */
308 #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
309 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
310 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
311 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
312
313 /*
314 ** Same as option 1, but also deal with
315 ** misconfigured interrupts.
316 **
317 ** - Edge triggerred instead of level sensitive.
318 ** - No interrupt line connected.
319 ** - IRQ number misconfigured.
320 **
321 ** If no interrupt is delivered, the driver will
322 ** catch the interrupt conditions 10 times per
323 ** second. No need to say that this option is
324 ** not recommended.
325 */
326 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
327 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
328 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
329 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
330 #define SCSI_NCR_PCIQ_BROKEN_INTR
331
332 /*
333 ** Some bridge designers decided to flush
334 ** everything prior to deliver the interrupt.
335 ** This option tries to deal with such a
336 ** behaviour.
337 */
338 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
339 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
340 #endif
341
342 /*
343 ** Other parameters not configurable with "make config"
344 ** Avoid to change these constants, unless you know what you are doing.
345 */
346
347 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
348 #define SCSI_NCR_MAX_SCATTER (127)
349 #define SCSI_NCR_MAX_TARGET (16)
350
351 /*
352 ** Compute some desirable value for CAN_QUEUE
353 ** and CMD_PER_LUN.
354 ** The driver will use lower values if these
355 ** ones appear to be too large.
356 */
357 #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
358 #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
359
360 #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
361 #define SCSI_NCR_TIMER_INTERVAL (HZ)
362
363 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
364 #define SCSI_NCR_MAX_LUN (16)
365 #else
366 #define SCSI_NCR_MAX_LUN (1)
367 #endif
368
369 #ifndef HOSTS_C
370
371 /*
372 ** These simple macros limit expression involving
373 ** kernel time values (jiffies) to some that have
374 ** chance not to be too much incorrect. :-)
375 */
376 #define ktime_get(o) (jiffies + (u_long) o)
377 #define ktime_exp(b) ((long)(jiffies) - (long)(b) >= 0)
378 #define ktime_dif(a, b) ((long)(a) - (long)(b))
379 /* These ones are not used in this driver */
380 #define ktime_add(a, o) ((a) + (u_long)(o))
381 #define ktime_sub(a, o) ((a) - (u_long)(o))
382
383
384 /*
385 * IO functions definition for big/little endian CPU support.
386 * For now, the NCR is only supported in little endian addressing mode,
387 */
388
389 #ifdef __BIG_ENDIAN
390
391 #if LINUX_VERSION_CODE < LinuxVersionCode(2,1,0)
392 #error "BIG ENDIAN byte ordering needs kernel version >= 2.1.0"
393 #endif
394
395 #define inw_l2b inw
396 #define inl_l2b inl
397 #define outw_b2l outw
398 #define outl_b2l outl
399
400 #define readb_raw readb
401 #define writeb_raw writeb
402
403 #if defined(__hppa__)
404 #define readw_l2b(a) le16_to_cpu(readw(a))
405 #define readl_l2b(a) le32_to_cpu(readl(a))
406 #define writew_b2l(v,a) writew(cpu_to_le16(v),a)
407 #define writel_b2l(v,a) writel(cpu_to_le32(v),a)
408 #else /* Other bid-endian */
409 #define readw_l2b readw
410 #define readl_l2b readl
411 #define writew_b2l writew
412 #define writel_b2l writel
413 #endif
414
415 #else /* little endian */
416
417 #define inw_raw inw
418 #define inl_raw inl
419 #define outw_raw outw
420 #define outl_raw outl
421
422 #if defined(__i386__) /* i386 implements full FLAT memory/MMIO model */
423 #define readb_raw(a) (*(volatile unsigned char *) (a))
424 #define readw_raw(a) (*(volatile unsigned short *) (a))
425 #define readl_raw(a) (*(volatile unsigned int *) (a))
426 #define writeb_raw(b,a) ((*(volatile unsigned char *) (a)) = (b))
427 #define writew_raw(b,a) ((*(volatile unsigned short *) (a)) = (b))
428 #define writel_raw(b,a) ((*(volatile unsigned int *) (a)) = (b))
429
430 #else /* Other little-endian */
431 #define readb_raw readb
432 #define readw_raw readw
433 #define readl_raw readl
434 #define writeb_raw writeb
435 #define writew_raw writew
436 #define writel_raw writel
437
438 #endif
439 #endif
440
441 #ifdef SCSI_NCR_BIG_ENDIAN
442 #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
443 #endif
444
445
446 /*
447 * IA32 architecture does not reorder STORES and prevents
448 * LOADS from passing STORES. It is called `program order'
449 * by Intel and allows device drivers to deal with memory
450 * ordering by only ensuring that the code is not reordered
451 * by the compiler when ordering is required.
452 * Other architectures implement a weaker ordering that
453 * requires memory barriers (and also IO barriers when they
454 * make sense) to be used.
455 * We want to be paranoid for ppc and ia64. :)
456 */
457
458 #if defined(__i386__) || defined(__x86_64__)
459 #define MEMORY_BARRIER() do { ; } while(0)
460 #elif defined __powerpc__
461 #define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory")
462 #elif defined __ia64__
463 #define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory")
464 #else
465 #define MEMORY_BARRIER() mb()
466 #endif
467
468
469 /*
470 * If the NCR uses big endian addressing mode over the
471 * PCI, actual io register addresses for byte and word
472 * accesses must be changed according to lane routing.
473 * Btw, ncr_offb() and ncr_offw() macros only apply to
474 * constants and so donnot generate bloated code.
475 */
476
477 #if defined(SCSI_NCR_BIG_ENDIAN)
478
479 #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
480 #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
481
482 #else
483
484 #define ncr_offb(o) (o)
485 #define ncr_offw(o) (o)
486
487 #endif
488
489 /*
490 * If the CPU and the NCR use same endian-ness adressing,
491 * no byte reordering is needed for script patching.
492 * Macro cpu_to_scr() is to be used for script patching.
493 * Macro scr_to_cpu() is to be used for getting a DWORD
494 * from the script.
495 */
496
497 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
498
499 #define cpu_to_scr(dw) cpu_to_le32(dw)
500 #define scr_to_cpu(dw) le32_to_cpu(dw)
501
502 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
503
504 #define cpu_to_scr(dw) cpu_to_be32(dw)
505 #define scr_to_cpu(dw) be32_to_cpu(dw)
506
507 #else
508
509 #define cpu_to_scr(dw) (dw)
510 #define scr_to_cpu(dw) (dw)
511
512 #endif
513
514 /*
515 * Access to the controller chip.
516 *
517 * If SCSI_NCR_IOMAPPED is defined, the driver will use
518 * normal IOs instead of the MEMORY MAPPED IO method
519 * recommended by PCI specifications.
520 * If all PCI bridges, host brigdes and architectures
521 * would have been correctly designed for PCI, this
522 * option would be useless.
523 *
524 * If the CPU and the NCR use same endian-ness adressing,
525 * no byte reordering is needed for accessing chip io
526 * registers. Functions suffixed by '_raw' are assumed
527 * to access the chip over the PCI without doing byte
528 * reordering. Functions suffixed by '_l2b' are
529 * assumed to perform little-endian to big-endian byte
530 * reordering, those suffixed by '_b2l' blah, blah,
531 * blah, ...
532 */
533
534 #if defined(SCSI_NCR_IOMAPPED)
535
536 /*
537 * IO mapped only input / ouput
538 */
539
540 #define INB_OFF(o) inb (np->base_io + ncr_offb(o))
541 #define OUTB_OFF(o, val) outb ((val), np->base_io + ncr_offb(o))
542
543 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
544
545 #define INW_OFF(o) inw_l2b (np->base_io + ncr_offw(o))
546 #define INL_OFF(o) inl_l2b (np->base_io + (o))
547
548 #define OUTW_OFF(o, val) outw_b2l ((val), np->base_io + ncr_offw(o))
549 #define OUTL_OFF(o, val) outl_b2l ((val), np->base_io + (o))
550
551 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
552
553 #define INW_OFF(o) inw_b2l (np->base_io + ncr_offw(o))
554 #define INL_OFF(o) inl_b2l (np->base_io + (o))
555
556 #define OUTW_OFF(o, val) outw_l2b ((val), np->base_io + ncr_offw(o))
557 #define OUTL_OFF(o, val) outl_l2b ((val), np->base_io + (o))
558
559 #else
560
561 #define INW_OFF(o) inw_raw (np->base_io + ncr_offw(o))
562 #define INL_OFF(o) inl_raw (np->base_io + (o))
563
564 #define OUTW_OFF(o, val) outw_raw ((val), np->base_io + ncr_offw(o))
565 #define OUTL_OFF(o, val) outl_raw ((val), np->base_io + (o))
566
567 #endif /* ENDIANs */
568
569 #else /* defined SCSI_NCR_IOMAPPED */
570
571 /*
572 * MEMORY mapped IO input / output
573 */
574
575 #define INB_OFF(o) readb_raw((char *)np->reg + ncr_offb(o))
576 #define OUTB_OFF(o, val) writeb_raw((val), (char *)np->reg + ncr_offb(o))
577
578 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
579
580 #define INW_OFF(o) readw_l2b((char *)np->reg + ncr_offw(o))
581 #define INL_OFF(o) readl_l2b((char *)np->reg + (o))
582
583 #define OUTW_OFF(o, val) writew_b2l((val), (char *)np->reg + ncr_offw(o))
584 #define OUTL_OFF(o, val) writel_b2l((val), (char *)np->reg + (o))
585
586 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
587
588 #define INW_OFF(o) readw_b2l((char *)np->reg + ncr_offw(o))
589 #define INL_OFF(o) readl_b2l((char *)np->reg + (o))
590
591 #define OUTW_OFF(o, val) writew_l2b((val), (char *)np->reg + ncr_offw(o))
592 #define OUTL_OFF(o, val) writel_l2b((val), (char *)np->reg + (o))
593
594 #else
595
596 #define INW_OFF(o) readw_raw((char *)np->reg + ncr_offw(o))
597 #define INL_OFF(o) readl_raw((char *)np->reg + (o))
598
599 #define OUTW_OFF(o, val) writew_raw((val), (char *)np->reg + ncr_offw(o))
600 #define OUTL_OFF(o, val) writel_raw((val), (char *)np->reg + (o))
601
602 #endif
603
604 #endif /* defined SCSI_NCR_IOMAPPED */
605
606 #define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
607 #define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
608 #define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
609
610 #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
611 #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
612 #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
613
614 /*
615 * Set bit field ON, OFF
616 */
617
618 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
619 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
620 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
621 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
622 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
623 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
624
625 /*
626 * We normally want the chip to have a consistent view
627 * of driver internal data structures when we restart it.
628 * Thus these macros.
629 */
630 #define OUTL_DSP(v) \
631 do { \
632 MEMORY_BARRIER(); \
633 OUTL (nc_dsp, (v)); \
634 } while (0)
635
636 #define OUTONB_STD() \
637 do { \
638 MEMORY_BARRIER(); \
639 OUTONB (nc_dcntl, (STD|NOCOM)); \
640 } while (0)
641
642
643 /*
644 ** NCR53C8XX Device Ids
645 */
646
647 #ifndef PCI_DEVICE_ID_NCR_53C810
648 #define PCI_DEVICE_ID_NCR_53C810 1
649 #endif
650
651 #ifndef PCI_DEVICE_ID_NCR_53C810AP
652 #define PCI_DEVICE_ID_NCR_53C810AP 5
653 #endif
654
655 #ifndef PCI_DEVICE_ID_NCR_53C815
656 #define PCI_DEVICE_ID_NCR_53C815 4
657 #endif
658
659 #ifndef PCI_DEVICE_ID_NCR_53C820
660 #define PCI_DEVICE_ID_NCR_53C820 2
661 #endif
662
663 #ifndef PCI_DEVICE_ID_NCR_53C825
664 #define PCI_DEVICE_ID_NCR_53C825 3
665 #endif
666
667 #ifndef PCI_DEVICE_ID_NCR_53C860
668 #define PCI_DEVICE_ID_NCR_53C860 6
669 #endif
670
671 #ifndef PCI_DEVICE_ID_NCR_53C875
672 #define PCI_DEVICE_ID_NCR_53C875 0xf
673 #endif
674
675 #ifndef PCI_DEVICE_ID_NCR_53C875J
676 #define PCI_DEVICE_ID_NCR_53C875J 0x8f
677 #endif
678
679 #ifndef PCI_DEVICE_ID_NCR_53C885
680 #define PCI_DEVICE_ID_NCR_53C885 0xd
681 #endif
682
683 #ifndef PCI_DEVICE_ID_NCR_53C895
684 #define PCI_DEVICE_ID_NCR_53C895 0xc
685 #endif
686
687 #ifndef PCI_DEVICE_ID_NCR_53C896
688 #define PCI_DEVICE_ID_NCR_53C896 0xb
689 #endif
690
691 #ifndef PCI_DEVICE_ID_NCR_53C895A
692 #define PCI_DEVICE_ID_NCR_53C895A 0x12
693 #endif
694
695 #ifndef PCI_DEVICE_ID_NCR_53C875A
696 #define PCI_DEVICE_ID_NCR_53C875A 0x13
697 #endif
698
699 #ifndef PCI_DEVICE_ID_NCR_53C1510D
700 #define PCI_DEVICE_ID_NCR_53C1510D 0xa
701 #endif
702
703 #ifndef PCI_DEVICE_ID_LSI_53C1010
704 #define PCI_DEVICE_ID_LSI_53C1010 0x20
705 #endif
706
707 #ifndef PCI_DEVICE_ID_LSI_53C1010_66
708 #define PCI_DEVICE_ID_LSI_53C1010_66 0x21
709 #endif
710
711
712 /*
713 ** NCR53C8XX devices features table.
714 */
715 typedef struct {
716 unsigned short device_id;
717 unsigned short revision_id;
718 char *name;
719 unsigned char burst_max; /* log-base-2 of max burst */
720 unsigned char offset_max;
721 unsigned char nr_divisor;
722 unsigned int features;
723 #define FE_LED0 (1<<0)
724 #define FE_WIDE (1<<1) /* Wide data transfers */
725 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
726 #define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
727 #define FE_DBLR (1<<4) /* Clock doubler present */
728 #define FE_QUAD (1<<5) /* Clock quadrupler present */
729 #define FE_ERL (1<<6) /* Enable read line */
730 #define FE_CLSE (1<<7) /* Cache line size enable */
731 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
732 #define FE_ERMP (1<<9) /* Enable read multiple */
733 #define FE_BOF (1<<10) /* Burst opcode fetch */
734 #define FE_DFS (1<<11) /* DMA fifo size */
735 #define FE_PFEN (1<<12) /* Prefetch enable */
736 #define FE_LDSTR (1<<13) /* Load/Store supported */
737 #define FE_RAM (1<<14) /* On chip RAM present */
738 #define FE_VARCLK (1<<15) /* SCSI clock may vary */
739 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
740 #define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
741 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
742 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
743 #define FE_LEDC (1<<20) /* Hardware control of LED */
744 #define FE_DIFF (1<<21) /* Support Differential SCSI */
745 #define FE_ULTRA3 (1<<22) /* Ultra-3 80Mtrans/sec */
746 #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
747 #define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
748 #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
749
750 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
751 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
752 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
753 } ncr_chip;
754
755 /*
756 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 3.
757 ** Memory Read transaction terminated by a retry followed by
758 ** Memory Read Line command.
759 */
760 #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
761
762 /*
763 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 5.
764 ** On paper, this errata is harmless. But it is a good reason for
765 ** using a shorter programmed burst length (64 DWORDS instead of 128).
766 */
767
768 #define SCSI_NCR_CHIP_TABLE \
769 { \
770 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, \
771 FE_ERL} \
772 , \
773 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, \
774 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} \
775 , \
776 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, \
777 FE_ERL|FE_BOF} \
778 , \
779 {PCI_DEVICE_ID_NCR_53C820, 0xff, "820", 4, 8, 4, \
780 FE_WIDE|FE_ERL} \
781 , \
782 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 4, 8, 4, \
783 FE_WIDE|FE_ERL|FE_BOF|FE_DIFF} \
784 , \
785 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, \
786 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} \
787 , \
788 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, \
789 FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} \
790 , \
791 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, \
792 FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
793 FE_RAM|FE_DIFF|FE_VARCLK} \
794 , \
795 {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, \
796 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
797 FE_RAM|FE_DIFF|FE_VARCLK} \
798 , \
799 {PCI_DEVICE_ID_NCR_53C875J,0xff, "875J", 6, 16, 5, \
800 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
801 FE_RAM|FE_VARCLK} \
802 , \
803 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, \
804 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
805 FE_RAM|FE_DIFF|FE_VARCLK} \
806 , \
807 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, \
808 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
809 FE_RAM} \
810 , \
811 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, \
812 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
813 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ISTAT1} \
814 , \
815 {PCI_DEVICE_ID_NCR_53C895A, 0xff, "895a", 6, 31, 7, \
816 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
817 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
818 , \
819 {PCI_DEVICE_ID_NCR_53C875A, 0xff, "875a", 6, 31, 7, \
820 FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
821 FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC} \
822 , \
823 {PCI_DEVICE_ID_NCR_53C1510D, 0xff, "1510D", 7, 31, 7, \
824 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
825 FE_RAM|FE_IO256} \
826 , \
827 {PCI_DEVICE_ID_LSI_53C1010, 0xff, "1010-33", 6, 62, 7, \
828 FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
829 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3} \
830 , \
831 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 62, 7, \
832 FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_ISTAT1| \
833 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3| \
834 FE_66MHZ} \
835 }
836
837 /*
838 * List of supported NCR chip ids
839 */
840 #define SCSI_NCR_CHIP_IDS \
841 { \
842 PCI_DEVICE_ID_NCR_53C810, \
843 PCI_DEVICE_ID_NCR_53C815, \
844 PCI_DEVICE_ID_NCR_53C820, \
845 PCI_DEVICE_ID_NCR_53C825, \
846 PCI_DEVICE_ID_NCR_53C860, \
847 PCI_DEVICE_ID_NCR_53C875, \
848 PCI_DEVICE_ID_NCR_53C875J, \
849 PCI_DEVICE_ID_NCR_53C885, \
850 PCI_DEVICE_ID_NCR_53C895, \
851 PCI_DEVICE_ID_NCR_53C896, \
852 PCI_DEVICE_ID_NCR_53C895A, \
853 PCI_DEVICE_ID_NCR_53C1510D, \
854 PCI_DEVICE_ID_LSI_53C1010, \
855 PCI_DEVICE_ID_LSI_53C1010_66 \
856 }
857
858 /*
859 ** Driver setup structure.
860 **
861 ** This structure is initialized from linux config options.
862 ** It can be overridden at boot-up by the boot command line.
863 */
864 #define SCSI_NCR_MAX_EXCLUDES 8
865 struct ncr_driver_setup {
866 u_char master_parity;
867 u_char scsi_parity;
868 u_char disconnection;
869 u_char special_features;
870 u_char force_sync_nego;
871 u_char reverse_probe;
872 u_char pci_fix_up;
873 u_char use_nvram;
874 u_char verbose;
875 u_char default_tags;
876 u_short default_sync;
877 u_short debug;
878 u_char burst_max;
879 u_char led_pin;
880 u_char max_wide;
881 u_char settle_delay;
882 u_char diff_support;
883 u_char irqm;
884 u_char bus_check;
885 u_char optimize;
886 u_char recovery;
887 u_char host_id;
888 u_short iarb;
889 u_long excludes[SCSI_NCR_MAX_EXCLUDES];
890 char tag_ctrl[100];
891 };
892
893 /*
894 ** Initial setup.
895 ** Can be overriden at startup by a command line.
896 */
897 #define SCSI_NCR_DRIVER_SETUP \
898 { \
899 SCSI_NCR_SETUP_MASTER_PARITY, \
900 SCSI_NCR_SETUP_SCSI_PARITY, \
901 SCSI_NCR_SETUP_DISCONNECTION, \
902 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
903 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
904 0, \
905 0, \
906 1, \
907 0, \
908 SCSI_NCR_SETUP_DEFAULT_TAGS, \
909 SCSI_NCR_SETUP_DEFAULT_SYNC, \
910 0x00, \
911 7, \
912 SCSI_NCR_SETUP_LED_PIN, \
913 1, \
914 SCSI_NCR_SETUP_SETTLE_TIME, \
915 SCSI_NCR_SETUP_DIFF_SUPPORT, \
916 0, \
917 1, \
918 0, \
919 0, \
920 255, \
921 0x00 \
922 }
923
924 /*
925 ** Boot fail safe setup.
926 ** Override initial setup from boot command line:
927 ** ncr53c8xx=safe:y
928 */
929 #define SCSI_NCR_DRIVER_SAFE_SETUP \
930 { \
931 0, \
932 1, \
933 0, \
934 0, \
935 0, \
936 0, \
937 0, \
938 1, \
939 2, \
940 0, \
941 255, \
942 0x00, \
943 255, \
944 0, \
945 0, \
946 10, \
947 1, \
948 1, \
949 1, \
950 0, \
951 0, \
952 255 \
953 }
954
955 #ifdef SCSI_NCR_NVRAM_SUPPORT
956 /*
957 ** Symbios NvRAM data format
958 */
959 #define SYMBIOS_NVRAM_SIZE 368
960 #define SYMBIOS_NVRAM_ADDRESS 0x100
961
962 struct Symbios_nvram {
963 /* Header 6 bytes */
964 u_short type; /* 0x0000 */
965 u_short byte_count; /* excluding header/trailer */
966 u_short checksum;
967
968 /* Controller set up 20 bytes */
969 u_char v_major; /* 0x00 */
970 u_char v_minor; /* 0x30 */
971 u_int32 boot_crc;
972 u_short flags;
973 #define SYMBIOS_SCAM_ENABLE (1)
974 #define SYMBIOS_PARITY_ENABLE (1<<1)
975 #define SYMBIOS_VERBOSE_MSGS (1<<2)
976 #define SYMBIOS_CHS_MAPPING (1<<3)
977 #define SYMBIOS_NO_NVRAM (1<<3) /* ??? */
978 u_short flags1;
979 #define SYMBIOS_SCAN_HI_LO (1)
980 u_short term_state;
981 #define SYMBIOS_TERM_CANT_PROGRAM (0)
982 #define SYMBIOS_TERM_ENABLED (1)
983 #define SYMBIOS_TERM_DISABLED (2)
984 u_short rmvbl_flags;
985 #define SYMBIOS_RMVBL_NO_SUPPORT (0)
986 #define SYMBIOS_RMVBL_BOOT_DEVICE (1)
987 #define SYMBIOS_RMVBL_MEDIA_INSTALLED (2)
988 u_char host_id;
989 u_char num_hba; /* 0x04 */
990 u_char num_devices; /* 0x10 */
991 u_char max_scam_devices; /* 0x04 */
992 u_char num_valid_scam_devives; /* 0x00 */
993 u_char rsvd;
994
995 /* Boot order 14 bytes * 4 */
996 struct Symbios_host{
997 u_short type; /* 4:8xx / 0:nok */
998 u_short device_id; /* PCI device id */
999 u_short vendor_id; /* PCI vendor id */
1000 u_char bus_nr; /* PCI bus number */
1001 u_char device_fn; /* PCI device/function number << 3*/
1002 u_short word8;
1003 u_short flags;
1004 #define SYMBIOS_INIT_SCAN_AT_BOOT (1)
1005 u_short io_port; /* PCI io_port address */
1006 } host[4];
1007
1008 /* Targets 8 bytes * 16 */
1009 struct Symbios_target {
1010 u_char flags;
1011 #define SYMBIOS_DISCONNECT_ENABLE (1)
1012 #define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1)
1013 #define SYMBIOS_SCAN_LUNS (1<<2)
1014 #define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3)
1015 u_char rsvd;
1016 u_char bus_width; /* 0x08/0x10 */
1017 u_char sync_offset;
1018 u_short sync_period; /* 4*period factor */
1019 u_short timeout;
1020 } target[16];
1021 /* Scam table 8 bytes * 4 */
1022 struct Symbios_scam {
1023 u_short id;
1024 u_short method;
1025 #define SYMBIOS_SCAM_DEFAULT_METHOD (0)
1026 #define SYMBIOS_SCAM_DONT_ASSIGN (1)
1027 #define SYMBIOS_SCAM_SET_SPECIFIC_ID (2)
1028 #define SYMBIOS_SCAM_USE_ORDER_GIVEN (3)
1029 u_short status;
1030 #define SYMBIOS_SCAM_UNKNOWN (0)
1031 #define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1)
1032 #define SYMBIOS_SCAM_ID_NOT_SET (2)
1033 #define SYMBIOS_SCAM_ID_VALID (3)
1034 u_char target_id;
1035 u_char rsvd;
1036 } scam[4];
1037
1038 u_char spare_devices[15*8];
1039 u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
1040 };
1041 typedef struct Symbios_nvram Symbios_nvram;
1042 typedef struct Symbios_host Symbios_host;
1043 typedef struct Symbios_target Symbios_target;
1044 typedef struct Symbios_scam Symbios_scam;
1045
1046 /*
1047 ** Tekram NvRAM data format.
1048 */
1049 #define TEKRAM_NVRAM_SIZE 64
1050 #define TEKRAM_93C46_NVRAM_ADDRESS 0
1051 #define TEKRAM_24C16_NVRAM_ADDRESS 0x40
1052
1053 struct Tekram_nvram {
1054 struct Tekram_target {
1055 u_char flags;
1056 #define TEKRAM_PARITY_CHECK (1)
1057 #define TEKRAM_SYNC_NEGO (1<<1)
1058 #define TEKRAM_DISCONNECT_ENABLE (1<<2)
1059 #define TEKRAM_START_CMD (1<<3)
1060 #define TEKRAM_TAGGED_COMMANDS (1<<4)
1061 #define TEKRAM_WIDE_NEGO (1<<5)
1062 u_char sync_index;
1063 u_short word2;
1064 } target[16];
1065 u_char host_id;
1066 u_char flags;
1067 #define TEKRAM_MORE_THAN_2_DRIVES (1)
1068 #define TEKRAM_DRIVES_SUP_1GB (1<<1)
1069 #define TEKRAM_RESET_ON_POWER_ON (1<<2)
1070 #define TEKRAM_ACTIVE_NEGATION (1<<3)
1071 #define TEKRAM_IMMEDIATE_SEEK (1<<4)
1072 #define TEKRAM_SCAN_LUNS (1<<5)
1073 #define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */
1074 u_char boot_delay_index;
1075 u_char max_tags_index;
1076 u_short flags1;
1077 #define TEKRAM_F2_F6_ENABLED (1)
1078 u_short spare[29];
1079 };
1080 typedef struct Tekram_nvram Tekram_nvram;
1081 typedef struct Tekram_target Tekram_target;
1082
1083 #endif /* SCSI_NCR_NVRAM_SUPPORT */
1084
1085 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
1086
1087 /*-----------------------------------------------------------------
1088 **
1089 ** The ncr 53c810 register structure.
1090 **
1091 **-----------------------------------------------------------------
1092 */
1093
1094 struct ncr_reg {
1095 /*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
1096
1097 /*01*/ u_char nc_scntl1; /* no reset */
1098 #define ISCON 0x10 /* connected to scsi */
1099 #define CRST 0x08 /* force reset */
1100 #define IARB 0x02 /* immediate arbitration */
1101
1102 /*02*/ u_char nc_scntl2; /* no disconnect expected */
1103 #define SDU 0x80 /* cmd: disconnect will raise error */
1104 #define CHM 0x40 /* sta: chained mode */
1105 #define WSS 0x08 /* sta: wide scsi send [W]*/
1106 #define WSR 0x01 /* sta: wide scsi received [W]*/
1107
1108 /*03*/ u_char nc_scntl3; /* cnf system clock dependent */
1109 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
1110 #define ULTRA 0x80 /* cmd: ULTRA enable */
1111 /* bits 0-2, 7 rsvd for C1010 */
1112
1113 /*04*/ u_char nc_scid; /* cnf host adapter scsi address */
1114 #define RRE 0x40 /* r/w:e enable response to resel. */
1115 #define SRE 0x20 /* r/w:e enable response to select */
1116
1117 /*05*/ u_char nc_sxfer; /* ### Sync speed and count */
1118 /* bits 6-7 rsvd for C1010 */
1119
1120 /*06*/ u_char nc_sdid; /* ### Destination-ID */
1121
1122 /*07*/ u_char nc_gpreg; /* ??? IO-Pins */
1123
1124 /*08*/ u_char nc_sfbr; /* ### First byte in phase */
1125
1126 /*09*/ u_char nc_socl;
1127 #define CREQ 0x80 /* r/w: SCSI-REQ */
1128 #define CACK 0x40 /* r/w: SCSI-ACK */
1129 #define CBSY 0x20 /* r/w: SCSI-BSY */
1130 #define CSEL 0x10 /* r/w: SCSI-SEL */
1131 #define CATN 0x08 /* r/w: SCSI-ATN */
1132 #define CMSG 0x04 /* r/w: SCSI-MSG */
1133 #define CC_D 0x02 /* r/w: SCSI-C_D */
1134 #define CI_O 0x01 /* r/w: SCSI-I_O */
1135
1136 /*0a*/ u_char nc_ssid;
1137
1138 /*0b*/ u_char nc_sbcl;
1139
1140 /*0c*/ u_char nc_dstat;
1141 #define DFE 0x80 /* sta: dma fifo empty */
1142 #define MDPE 0x40 /* int: master data parity error */
1143 #define BF 0x20 /* int: script: bus fault */
1144 #define ABRT 0x10 /* int: script: command aborted */
1145 #define SSI 0x08 /* int: script: single step */
1146 #define SIR 0x04 /* int: script: interrupt instruct. */
1147 #define IID 0x01 /* int: script: illegal instruct. */
1148
1149 /*0d*/ u_char nc_sstat0;
1150 #define ILF 0x80 /* sta: data in SIDL register lsb */
1151 #define ORF 0x40 /* sta: data in SODR register lsb */
1152 #define OLF 0x20 /* sta: data in SODL register lsb */
1153 #define AIP 0x10 /* sta: arbitration in progress */
1154 #define LOA 0x08 /* sta: arbitration lost */
1155 #define WOA 0x04 /* sta: arbitration won */
1156 #define IRST 0x02 /* sta: scsi reset signal */
1157 #define SDP 0x01 /* sta: scsi parity signal */
1158
1159 /*0e*/ u_char nc_sstat1;
1160 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
1161
1162 /*0f*/ u_char nc_sstat2;
1163 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
1164 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
1165 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
1166 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
1167 #define LDSC 0x02 /* sta: disconnect & reconnect */
1168
1169 /*10*/ u_char nc_dsa; /* --> Base page */
1170 /*11*/ u_char nc_dsa1;
1171 /*12*/ u_char nc_dsa2;
1172 /*13*/ u_char nc_dsa3;
1173
1174 /*14*/ u_char nc_istat; /* --> Main Command and status */
1175 #define CABRT 0x80 /* cmd: abort current operation */
1176 #define SRST 0x40 /* mod: reset chip */
1177 #define SIGP 0x20 /* r/w: message from host to ncr */
1178 #define SEM 0x10 /* r/w: message between host + ncr */
1179 #define CON 0x08 /* sta: connected to scsi */
1180 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
1181 #define SIP 0x02 /* sta: scsi-interrupt */
1182 #define DIP 0x01 /* sta: host/script interrupt */
1183
1184 /*15*/ u_char nc_istat1; /* 896 and later cores only */
1185 #define FLSH 0x04 /* sta: chip is flushing */
1186 #define SRUN 0x02 /* sta: scripts are running */
1187 #define SIRQD 0x01 /* r/w: disable INT pin */
1188
1189 /*16*/ u_char nc_mbox0; /* 896 and later cores only */
1190 /*17*/ u_char nc_mbox1; /* 896 and later cores only */
1191
1192 /*18*/ u_char nc_ctest0;
1193 /*19*/ u_char nc_ctest1;
1194
1195 /*1a*/ u_char nc_ctest2;
1196 #define CSIGP 0x40
1197 /* bits 0-2,7 rsvd for C1010 */
1198
1199 /*1b*/ u_char nc_ctest3;
1200 #define FLF 0x08 /* cmd: flush dma fifo */
1201 #define CLF 0x04 /* cmd: clear dma fifo */
1202 #define FM 0x02 /* mod: fetch pin mode */
1203 #define WRIE 0x01 /* mod: write and invalidate enable */
1204 /* bits 4-7 rsvd for C1010 */
1205
1206 /*1c*/ u_int32 nc_temp; /* ### Temporary stack */
1207
1208 /*20*/ u_char nc_dfifo;
1209 /*21*/ u_char nc_ctest4;
1210 #define BDIS 0x80 /* mod: burst disable */
1211 #define MPEE 0x08 /* mod: master parity error enable */
1212
1213 /*22*/ u_char nc_ctest5;
1214 #define DFS 0x20 /* mod: dma fifo size */
1215 /* bits 0-1, 3-7 rsvd for C1010 */
1216 /*23*/ u_char nc_ctest6;
1217
1218 /*24*/ u_int32 nc_dbc; /* ### Byte count and command */
1219 /*28*/ u_int32 nc_dnad; /* ### Next command register */
1220 /*2c*/ u_int32 nc_dsp; /* --> Script Pointer */
1221 /*30*/ u_int32 nc_dsps; /* --> Script pointer save/opcode#2 */
1222
1223 /*34*/ u_char nc_scratcha; /* Temporary register a */
1224 /*35*/ u_char nc_scratcha1;
1225 /*36*/ u_char nc_scratcha2;
1226 /*37*/ u_char nc_scratcha3;
1227
1228 /*38*/ u_char nc_dmode;
1229 #define BL_2 0x80 /* mod: burst length shift value +2 */
1230 #define BL_1 0x40 /* mod: burst length shift value +1 */
1231 #define ERL 0x08 /* mod: enable read line */
1232 #define ERMP 0x04 /* mod: enable read multiple */
1233 #define BOF 0x02 /* mod: burst op code fetch */
1234
1235 /*39*/ u_char nc_dien;
1236 /*3a*/ u_char nc_sbr;
1237
1238 /*3b*/ u_char nc_dcntl; /* --> Script execution control */
1239 #define CLSE 0x80 /* mod: cache line size enable */
1240 #define PFF 0x40 /* cmd: pre-fetch flush */
1241 #define PFEN 0x20 /* mod: pre-fetch enable */
1242 #define SSM 0x10 /* mod: single step mode */
1243 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
1244 #define STD 0x04 /* cmd: start dma mode */
1245 #define IRQD 0x02 /* mod: irq disable */
1246 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
1247 /* bits 0-1 rsvd for C1010 */
1248
1249 /*3c*/ u_int32 nc_adder;
1250
1251 /*40*/ u_short nc_sien; /* -->: interrupt enable */
1252 /*42*/ u_short nc_sist; /* <--: interrupt status */
1253 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
1254 #define STO 0x0400/* sta: timeout (select) */
1255 #define GEN 0x0200/* sta: timeout (general) */
1256 #define HTH 0x0100/* sta: timeout (handshake) */
1257 #define MA 0x80 /* sta: phase mismatch */
1258 #define CMP 0x40 /* sta: arbitration complete */
1259 #define SEL 0x20 /* sta: selected by another device */
1260 #define RSL 0x10 /* sta: reselected by another device*/
1261 #define SGE 0x08 /* sta: gross error (over/underflow)*/
1262 #define UDC 0x04 /* sta: unexpected disconnect */
1263 #define RST 0x02 /* sta: scsi bus reset detected */
1264 #define PAR 0x01 /* sta: scsi parity error */
1265
1266 /*44*/ u_char nc_slpar;
1267 /*45*/ u_char nc_swide;
1268 /*46*/ u_char nc_macntl;
1269 /*47*/ u_char nc_gpcntl;
1270 /*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
1271 /*49*/ u_char nc_stime1; /* cmd: timeout user defined */
1272 /*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
1273
1274 /*4c*/ u_char nc_stest0;
1275
1276 /*4d*/ u_char nc_stest1;
1277 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
1278 #define DBLEN 0x08 /* clock doubler running */
1279 #define DBLSEL 0x04 /* clock doubler selected */
1280
1281
1282 /*4e*/ u_char nc_stest2;
1283 #define ROF 0x40 /* reset scsi offset (after gross error!) */
1284 #define EXT 0x02 /* extended filtering */
1285
1286 /*4f*/ u_char nc_stest3;
1287 #define TE 0x80 /* c: tolerAnt enable */
1288 #define HSC 0x20 /* c: Halt SCSI Clock */
1289 #define CSF 0x02 /* c: clear scsi fifo */
1290
1291 /*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
1292 /*52*/ u_char nc_stest4;
1293 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
1294 #define SMODE_HVD 0x40 /* High Voltage Differential */
1295 #define SMODE_SE 0x80 /* Single Ended */
1296 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
1297 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
1298 /* bits 0-5 rsvd for C1010 */
1299
1300 /*53*/ u_char nc_53_;
1301 /*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
1302 /*56*/ u_char nc_ccntl0; /* Chip Control 0 (896) */
1303 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
1304 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
1305 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
1306 #define DISFC 0x10 /* Disable Auto FIFO Clear */
1307 #define DILS 0x02 /* Disable Internal Load/Store */
1308 #define DPR 0x01 /* Disable Pipe Req */
1309
1310 /*57*/ u_char nc_ccntl1; /* Chip Control 1 (896) */
1311 #define ZMOD 0x80 /* High Impedance Mode */
1312 #define DIC 0x10 /* Disable Internal Cycles */
1313 #define DDAC 0x08 /* Disable Dual Address Cycle */
1314 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
1315 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
1316 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
1317
1318 /*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
1319 /*5a*/ u_short nc_5a_;
1320
1321 /*5c*/ u_char nc_scr0; /* Working register B */
1322 /*5d*/ u_char nc_scr1; /* */
1323 /*5e*/ u_char nc_scr2; /* */
1324 /*5f*/ u_char nc_scr3; /* */
1325
1326 /*60*/ u_char nc_scrx[64]; /* Working register C-R */
1327 /*a0*/ u_int32 nc_mmrs; /* Memory Move Read Selector */
1328 /*a4*/ u_int32 nc_mmws; /* Memory Move Write Selector */
1329 /*a8*/ u_int32 nc_sfs; /* Script Fetch Selector */
1330 /*ac*/ u_int32 nc_drs; /* DSA Relative Selector */
1331 /*b0*/ u_int32 nc_sbms; /* Static Block Move Selector */
1332 /*b4*/ u_int32 nc_dbms; /* Dynamic Block Move Selector */
1333 /*b8*/ u_int32 nc_dnad64; /* DMA Next Address 64 */
1334 /*bc*/ u_short nc_scntl4; /* C1010 only */
1335 #define U3EN 0x80 /* Enable Ultra 3 */
1336 #define AIPEN 0x40 /* Allow check upper byte lanes */
1337 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
1338 transfer edge */
1339 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
1340 transfer edge */
1341
1342 /*be*/ u_char nc_aipcntl0; /* Epat Control 1 C1010 only */
1343 /*bf*/ u_char nc_aipcntl1; /* AIP Control C1010_66 Only */
1344
1345 /*c0*/ u_int32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
1346 /*c4*/ u_int32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
1347 /*c8*/ u_char nc_rbc; /* Remaining Byte Count */
1348 /*c9*/ u_char nc_rbc1; /* */
1349 /*ca*/ u_char nc_rbc2; /* */
1350 /*cb*/ u_char nc_rbc3; /* */
1351
1352 /*cc*/ u_char nc_ua; /* Updated Address */
1353 /*cd*/ u_char nc_ua1; /* */
1354 /*ce*/ u_char nc_ua2; /* */
1355 /*cf*/ u_char nc_ua3; /* */
1356 /*d0*/ u_int32 nc_esa; /* Entry Storage Address */
1357 /*d4*/ u_char nc_ia; /* Instruction Address */
1358 /*d5*/ u_char nc_ia1;
1359 /*d6*/ u_char nc_ia2;
1360 /*d7*/ u_char nc_ia3;
1361 /*d8*/ u_int32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
1362 /*dc*/ u_int32 nc_csbc; /* Cumulative SCSI Byte Count */
1363
1364 /* Following for C1010 only */
1365 /*e0*/ u_short nc_crcpad; /* CRC Value */
1366 /*e2*/ u_char nc_crccntl0; /* CRC control register */
1367 #define SNDCRC 0x10 /* Send CRC Request */
1368 /*e3*/ u_char nc_crccntl1; /* CRC control register */
1369 /*e4*/ u_int32 nc_crcdata; /* CRC data register */
1370 /*e8*/ u_int32 nc_e8_; /* rsvd */
1371 /*ec*/ u_int32 nc_ec_; /* rsvd */
1372 /*f0*/ u_short nc_dfbc; /* DMA FIFO byte count */
1373
1374 };
1375
1376 /*-----------------------------------------------------------
1377 **
1378 ** Utility macros for the script.
1379 **
1380 **-----------------------------------------------------------
1381 */
1382
1383 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
1384 #define REG(r) REGJ (nc_, r)
1385
1386 typedef u_int32 ncrcmd;
1387
1388 /*-----------------------------------------------------------
1389 **
1390 ** SCSI phases
1391 **
1392 ** DT phases illegal for ncr driver.
1393 **
1394 **-----------------------------------------------------------
1395 */
1396
1397 #define SCR_DATA_OUT 0x00000000
1398 #define SCR_DATA_IN 0x01000000
1399 #define SCR_COMMAND 0x02000000
1400 #define SCR_STATUS 0x03000000
1401 #define SCR_DT_DATA_OUT 0x04000000
1402 #define SCR_DT_DATA_IN 0x05000000
1403 #define SCR_MSG_OUT 0x06000000
1404 #define SCR_MSG_IN 0x07000000
1405
1406 #define SCR_ILG_OUT 0x04000000
1407 #define SCR_ILG_IN 0x05000000
1408
1409 /*-----------------------------------------------------------
1410 **
1411 ** Data transfer via SCSI.
1412 **
1413 **-----------------------------------------------------------
1414 **
1415 ** MOVE_ABS (LEN)
1416 ** <<start address>>
1417 **
1418 ** MOVE_IND (LEN)
1419 ** <<dnad_offset>>
1420 **
1421 ** MOVE_TBL
1422 ** <<dnad_offset>>
1423 **
1424 **-----------------------------------------------------------
1425 */
1426
1427 #define OPC_MOVE 0x08000000
1428
1429 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
1430 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
1431 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
1432
1433 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
1434 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
1435 #define SCR_CHMOV_TBL (0x10000000)
1436
1437 struct scr_tblmove {
1438 u_int32 size;
1439 u_int32 addr;
1440 };
1441
1442 /*-----------------------------------------------------------
1443 **
1444 ** Selection
1445 **
1446 **-----------------------------------------------------------
1447 **
1448 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
1449 ** <<alternate_address>>
1450 **
1451 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
1452 ** <<alternate_address>>
1453 **
1454 **-----------------------------------------------------------
1455 */
1456
1457 #define SCR_SEL_ABS 0x40000000
1458 #define SCR_SEL_ABS_ATN 0x41000000
1459 #define SCR_SEL_TBL 0x42000000
1460 #define SCR_SEL_TBL_ATN 0x43000000
1461
1462 struct scr_tblsel {
1463 u_char sel_scntl4;
1464 u_char sel_sxfer;
1465 u_char sel_id;
1466 u_char sel_scntl3;
1467 };
1468
1469 #define SCR_JMP_REL 0x04000000
1470 #define SCR_ID(id) (((u_int32)(id)) << 16)
1471
1472 /*-----------------------------------------------------------
1473 **
1474 ** Waiting for Disconnect or Reselect
1475 **
1476 **-----------------------------------------------------------
1477 **
1478 ** WAIT_DISC
1479 ** dummy: <<alternate_address>>
1480 **
1481 ** WAIT_RESEL
1482 ** <<alternate_address>>
1483 **
1484 **-----------------------------------------------------------
1485 */
1486
1487 #define SCR_WAIT_DISC 0x48000000
1488 #define SCR_WAIT_RESEL 0x50000000
1489
1490 /*-----------------------------------------------------------
1491 **
1492 ** Bit Set / Reset
1493 **
1494 **-----------------------------------------------------------
1495 **
1496 ** SET (flags {|.. })
1497 **
1498 ** CLR (flags {|.. })
1499 **
1500 **-----------------------------------------------------------
1501 */
1502
1503 #define SCR_SET(f) (0x58000000 | (f))
1504 #define SCR_CLR(f) (0x60000000 | (f))
1505
1506 #define SCR_CARRY 0x00000400
1507 #define SCR_TRG 0x00000200
1508 #define SCR_ACK 0x00000040
1509 #define SCR_ATN 0x00000008
1510
1511
1512
1513
1514 /*-----------------------------------------------------------
1515 **
1516 ** Memory to memory move
1517 **
1518 **-----------------------------------------------------------
1519 **
1520 ** COPY (bytecount)
1521 ** << source_address >>
1522 ** << destination_address >>
1523 **
1524 ** SCR_COPY sets the NO FLUSH option by default.
1525 ** SCR_COPY_F does not set this option.
1526 **
1527 ** For chips which do not support this option,
1528 ** ncr_copy_and_bind() will remove this bit.
1529 **-----------------------------------------------------------
1530 */
1531
1532 #define SCR_NO_FLUSH 0x01000000
1533
1534 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1535 #define SCR_COPY_F(n) (0xc0000000 | (n))
1536
1537 /*-----------------------------------------------------------
1538 **
1539 ** Register move and binary operations
1540 **
1541 **-----------------------------------------------------------
1542 **
1543 ** SFBR_REG (reg, op, data) reg = SFBR op data
1544 ** << 0 >>
1545 **
1546 ** REG_SFBR (reg, op, data) SFBR = reg op data
1547 ** << 0 >>
1548 **
1549 ** REG_REG (reg, op, data) reg = reg op data
1550 ** << 0 >>
1551 **
1552 **-----------------------------------------------------------
1553 ** On 810A, 860, 825A, 875, 895 and 896 chips the content
1554 ** of SFBR register can be used as data (SCR_SFBR_DATA).
1555 ** The 896 has additionnal IO registers starting at
1556 ** offset 0x80. Bit 7 of register offset is stored in
1557 ** bit 7 of the SCRIPTS instruction first DWORD.
1558 **-----------------------------------------------------------
1559 */
1560
1561 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1562
1563 #define SCR_SFBR_REG(reg,op,data) \
1564 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1565
1566 #define SCR_REG_SFBR(reg,op,data) \
1567 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1568
1569 #define SCR_REG_REG(reg,op,data) \
1570 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1571
1572
1573 #define SCR_LOAD 0x00000000
1574 #define SCR_SHL 0x01000000
1575 #define SCR_OR 0x02000000
1576 #define SCR_XOR 0x03000000
1577 #define SCR_AND 0x04000000
1578 #define SCR_SHR 0x05000000
1579 #define SCR_ADD 0x06000000
1580 #define SCR_ADDC 0x07000000
1581
1582 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1583
1584 /*-----------------------------------------------------------
1585 **
1586 ** FROM_REG (reg) SFBR = reg
1587 ** << 0 >>
1588 **
1589 ** TO_REG (reg) reg = SFBR
1590 ** << 0 >>
1591 **
1592 ** LOAD_REG (reg, data) reg = <data>
1593 ** << 0 >>
1594 **
1595 ** LOAD_SFBR(data) SFBR = <data>
1596 ** << 0 >>
1597 **
1598 **-----------------------------------------------------------
1599 */
1600
1601 #define SCR_FROM_REG(reg) \
1602 SCR_REG_SFBR(reg,SCR_OR,0)
1603
1604 #define SCR_TO_REG(reg) \
1605 SCR_SFBR_REG(reg,SCR_OR,0)
1606
1607 #define SCR_LOAD_REG(reg,data) \
1608 SCR_REG_REG(reg,SCR_LOAD,data)
1609
1610 #define SCR_LOAD_SFBR(data) \
1611 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1612
1613 /*-----------------------------------------------------------
1614 **
1615 ** LOAD from memory to register.
1616 ** STORE from register to memory.
1617 **
1618 ** Only supported by 810A, 860, 825A, 875, 895 and 896.
1619 **
1620 **-----------------------------------------------------------
1621 **
1622 ** LOAD_ABS (LEN)
1623 ** <<start address>>
1624 **
1625 ** LOAD_REL (LEN) (DSA relative)
1626 ** <<dsa_offset>>
1627 **
1628 **-----------------------------------------------------------
1629 */
1630
1631 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1632 #define SCR_NO_FLUSH2 0x02000000
1633 #define SCR_DSA_REL2 0x10000000
1634
1635 #define SCR_LOAD_R(reg, how, n) \
1636 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1637
1638 #define SCR_STORE_R(reg, how, n) \
1639 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1640
1641 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1642 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1643 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1644 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1645
1646 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1647 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1648 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1649 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1650
1651
1652 /*-----------------------------------------------------------
1653 **
1654 ** Waiting for Disconnect or Reselect
1655 **
1656 **-----------------------------------------------------------
1657 **
1658 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1659 ** <<address>>
1660 **
1661 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1662 ** <<distance>>
1663 **
1664 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1665 ** <<address>>
1666 **
1667 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1668 ** <<distance>>
1669 **
1670 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1671 ** <<dummy>>
1672 **
1673 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
1674 ** <<ident>>
1675 **
1676 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1677 ** <<ident>>
1678 **
1679 ** Conditions:
1680 ** WHEN (phase)
1681 ** IF (phase)
1682 ** CARRYSET
1683 ** DATA (data, mask)
1684 **
1685 **-----------------------------------------------------------
1686 */
1687
1688 #define SCR_NO_OP 0x80000000
1689 #define SCR_JUMP 0x80080000
1690 #define SCR_JUMP64 0x80480000
1691 #define SCR_JUMPR 0x80880000
1692 #define SCR_CALL 0x88080000
1693 #define SCR_CALLR 0x88880000
1694 #define SCR_RETURN 0x90080000
1695 #define SCR_INT 0x98080000
1696 #define SCR_INT_FLY 0x98180000
1697
1698 #define IFFALSE(arg) (0x00080000 | (arg))
1699 #define IFTRUE(arg) (0x00000000 | (arg))
1700
1701 #define WHEN(phase) (0x00030000 | (phase))
1702 #define IF(phase) (0x00020000 | (phase))
1703
1704 #define DATA(D) (0x00040000 | ((D) & 0xff))
1705 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1706
1707 #define CARRYSET (0x00200000)
1708
1709 /*-----------------------------------------------------------
1710 **
1711 ** SCSI constants.
1712 **
1713 **-----------------------------------------------------------
1714 */
1715
1716 /*
1717 ** Messages
1718 */
1719
1720 #define M_COMPLETE (0x00)
1721 #define M_EXTENDED (0x01)
1722 #define M_SAVE_DP (0x02)
1723 #define M_RESTORE_DP (0x03)
1724 #define M_DISCONNECT (0x04)
1725 #define M_ID_ERROR (0x05)
1726 #define M_ABORT (0x06)
1727 #define M_REJECT (0x07)
1728 #define M_NOOP (0x08)
1729 #define M_PARITY (0x09)
1730 #define M_LCOMPLETE (0x0a)
1731 #define M_FCOMPLETE (0x0b)
1732 #define M_RESET (0x0c)
1733 #define M_ABORT_TAG (0x0d)
1734 #define M_CLEAR_QUEUE (0x0e)
1735 #define M_INIT_REC (0x0f)
1736 #define M_REL_REC (0x10)
1737 #define M_TERMINATE (0x11)
1738 #define M_SIMPLE_TAG (0x20)
1739 #define M_HEAD_TAG (0x21)
1740 #define M_ORDERED_TAG (0x22)
1741 #define M_IGN_RESIDUE (0x23)
1742 #define M_IDENTIFY (0x80)
1743
1744 #define M_X_MODIFY_DP (0x00)
1745 #define M_X_SYNC_REQ (0x01)
1746 #define M_X_WIDE_REQ (0x03)
1747 #define M_X_PPR_REQ (0x04)
1748
1749 /*
1750 ** Status
1751 */
1752
1753 #define S_GOOD (0x00)
1754 #define S_CHECK_COND (0x02)
1755 #define S_COND_MET (0x04)
1756 #define S_BUSY (0x08)
1757 #define S_INT (0x10)
1758 #define S_INT_COND_MET (0x14)
1759 #define S_CONFLICT (0x18)
1760 #define S_TERMINATED (0x20)
1761 #define S_QUEUE_FULL (0x28)
1762 #define S_ILLEGAL (0xff)
1763 #define S_SENSE (0x80)
1764
1765 /*
1766 * End of ncrreg from FreeBSD
1767 */
1768
1769 #endif /* !defined HOSTS_C */
1770
1771 #endif /* defined SYM53C8XX_DEFS_H */
1772