File: /usr/src/linux/arch/i386/kernel/pci-i386.c
1 /*
2 * Low-Level PCI Access for i386 machines
3 *
4 * Copyright 1993, 1994 Drew Eckhardt
5 * Visionary Computing
6 * (Unix and Linux consulting and custom programming)
7 * Drew@Colorado.EDU
8 * +1 (303) 786-7975
9 *
10 * Drew's work was sponsored by:
11 * iX Multiuser Multitasking Magazine
12 * Hannover, Germany
13 * hm@ix.de
14 *
15 * Copyright 1997--2000 Martin Mares <mj@suse.cz>
16 *
17 * For more information, please consult the following manuals (look at
18 * http://www.pcisig.com/ for how to get them):
19 *
20 * PCI BIOS Specification
21 * PCI Local Bus Specification
22 * PCI to PCI Bridge Specification
23 * PCI System Design Guide
24 *
25 *
26 * CHANGELOG :
27 * Jun 17, 1994 : Modified to accommodate the broken pre-PCI BIOS SPECIFICATION
28 * Revision 2.0 present on <thys@dennis.ee.up.ac.za>'s ASUS mainboard.
29 *
30 * Jan 5, 1995 : Modified to probe PCI hardware at boot time by Frederic
31 * Potter, potter@cao-vlsi.ibp.fr
32 *
33 * Jan 10, 1995 : Modified to store the information about configured pci
34 * devices into a list, which can be accessed via /proc/pci by
35 * Curtis Varner, cvarner@cs.ucr.edu
36 *
37 * Jan 12, 1995 : CPU-PCI bridge optimization support by Frederic Potter.
38 * Alpha version. Intel & UMC chipset support only.
39 *
40 * Apr 16, 1995 : Source merge with the DEC Alpha PCI support. Most of the code
41 * moved to drivers/pci/pci.c.
42 *
43 * Dec 7, 1996 : Added support for direct configuration access of boards
44 * with Intel compatible access schemes (tsbogend@alpha.franken.de)
45 *
46 * Feb 3, 1997 : Set internal functions to static, save/restore flags
47 * avoid dead locks reading broken PCI BIOS, werner@suse.de
48 *
49 * Apr 26, 1997 : Fixed case when there is BIOS32, but not PCI BIOS
50 * (mj@atrey.karlin.mff.cuni.cz)
51 *
52 * May 7, 1997 : Added some missing cli()'s. [mj]
53 *
54 * Jun 20, 1997 : Corrected problems in "conf1" type accesses.
55 * (paubert@iram.es)
56 *
57 * Aug 2, 1997 : Split to PCI BIOS handling and direct PCI access parts
58 * and cleaned it up... Martin Mares <mj@atrey.karlin.mff.cuni.cz>
59 *
60 * Feb 6, 1998 : No longer using BIOS to find devices and device classes. [mj]
61 *
62 * May 1, 1998 : Support for peer host bridges. [mj]
63 *
64 * Jun 19, 1998 : Changed to use spinlocks, so that PCI configuration space
65 * can be accessed from interrupts even on SMP systems. [mj]
66 *
67 * August 1998 : Better support for peer host bridges and more paranoid
68 * checks for direct hardware access. Ugh, this file starts to look as
69 * a large gallery of common hardware bug workarounds (watch the comments)
70 * -- the PCI specs themselves are sane, but most implementors should be
71 * hit hard with \hammer scaled \magstep5. [mj]
72 *
73 * Jan 23, 1999 : More improvements to peer host bridge logic. i450NX fixup. [mj]
74 *
75 * Feb 8, 1999 : Added UM8886BF I/O address fixup. [mj]
76 *
77 * August 1999 : New resource management and configuration access stuff. [mj]
78 *
79 * Sep 19, 1999 : Use PCI IRQ routing tables for detection of peer host bridges.
80 * Based on ideas by Chris Frantz and David Hinds. [mj]
81 *
82 * Sep 28, 1999 : Handle unreported/unassigned IRQs. Thanks to Shuu Yamaguchi
83 * for a lot of patience during testing. [mj]
84 *
85 * Oct 8, 1999 : Split to pci-i386.c, pci-pc.c and pci-visws.c. [mj]
86 */
87
88 #include <linux/types.h>
89 #include <linux/kernel.h>
90 #include <linux/pci.h>
91 #include <linux/init.h>
92 #include <linux/ioport.h>
93 #include <linux/errno.h>
94
95 #include "pci-i386.h"
96
97 void
98 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
99 struct resource *res, int resource)
100 {
101 u32 new, check;
102 int reg;
103
104 new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
105 if (resource < 6) {
106 reg = PCI_BASE_ADDRESS_0 + 4*resource;
107 } else if (resource == PCI_ROM_RESOURCE) {
108 res->flags |= PCI_ROM_ADDRESS_ENABLE;
109 new |= PCI_ROM_ADDRESS_ENABLE;
110 reg = dev->rom_base_reg;
111 } else {
112 /* Somebody might have asked allocation of a non-standard resource */
113 return;
114 }
115
116 pci_write_config_dword(dev, reg, new);
117 pci_read_config_dword(dev, reg, &check);
118 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
119 printk(KERN_ERR "PCI: Error while updating region "
120 "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
121 new, check);
122 }
123 }
124
125 /*
126 * We need to avoid collisions with `mirrored' VGA ports
127 * and other strange ISA hardware, so we always want the
128 * addresses to be allocated in the 0x000-0x0ff region
129 * modulo 0x400.
130 *
131 * Why? Because some silly external IO cards only decode
132 * the low 10 bits of the IO address. The 0x00-0xff region
133 * is reserved for motherboard devices that decode all 16
134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
135 * but we want to try to avoid allocating at 0x2900-0x2bff
136 * which might have be mirrored at 0x0100-0x03ff..
137 */
138 void
139 pcibios_align_resource(void *data, struct resource *res, unsigned long size)
140 {
141 if (res->flags & IORESOURCE_IO) {
142 unsigned long start = res->start;
143
144 if (start & 0x300) {
145 start = (start + 0x3ff) & ~0x3ff;
146 res->start = start;
147 }
148 }
149 }
150
151
152 /*
153 * Handle resources of PCI devices. If the world were perfect, we could
154 * just allocate all the resource regions and do nothing more. It isn't.
155 * On the other hand, we cannot just re-allocate all devices, as it would
156 * require us to know lots of host bridge internals. So we attempt to
157 * keep as much of the original configuration as possible, but tweak it
158 * when it's found to be wrong.
159 *
160 * Known BIOS problems we have to work around:
161 * - I/O or memory regions not configured
162 * - regions configured, but not enabled in the command register
163 * - bogus I/O addresses above 64K used
164 * - expansion ROMs left enabled (this may sound harmless, but given
165 * the fact the PCI specs explicitly allow address decoders to be
166 * shared between expansion ROMs and other resource regions, it's
167 * at least dangerous)
168 *
169 * Our solution:
170 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
171 * This gives us fixed barriers on where we can allocate.
172 * (2) Allocate resources for all enabled devices. If there is
173 * a collision, just mark the resource as unallocated. Also
174 * disable expansion ROMs during this step.
175 * (3) Try to allocate resources for disabled devices. If the
176 * resources were assigned correctly, everything goes well,
177 * if they weren't, they won't disturb allocation of other
178 * resources.
179 * (4) Assign new addresses to resources which were either
180 * not configured at all or misconfigured. If explicitly
181 * requested by the user, configure expansion ROM address
182 * as well.
183 */
184
185 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
186 {
187 struct list_head *ln;
188 struct pci_bus *bus;
189 struct pci_dev *dev;
190 int idx;
191 struct resource *r, *pr;
192
193 /* Depth-First Search on bus tree */
194 for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
195 bus = pci_bus_b(ln);
196 if ((dev = bus->self)) {
197 for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
198 r = &dev->resource[idx];
199 if (!r->start)
200 continue;
201 pr = pci_find_parent_resource(dev, r);
202 if (!pr || request_resource(pr, r) < 0)
203 printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, dev->slot_name);
204 }
205 }
206 pcibios_allocate_bus_resources(&bus->children);
207 }
208 }
209
210 static void __init pcibios_allocate_resources(int pass)
211 {
212 struct pci_dev *dev;
213 int idx, disabled;
214 u16 command;
215 struct resource *r, *pr;
216
217 pci_for_each_dev(dev) {
218 pci_read_config_word(dev, PCI_COMMAND, &command);
219 for(idx = 0; idx < 6; idx++) {
220 r = &dev->resource[idx];
221 if (r->parent) /* Already allocated */
222 continue;
223 if (!r->start) /* Address not assigned at all */
224 continue;
225 if (r->flags & IORESOURCE_IO)
226 disabled = !(command & PCI_COMMAND_IO);
227 else
228 disabled = !(command & PCI_COMMAND_MEMORY);
229 if (pass == disabled) {
230 DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
231 r->start, r->end, r->flags, disabled, pass);
232 pr = pci_find_parent_resource(dev, r);
233 if (!pr || request_resource(pr, r) < 0) {
234 printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, dev->slot_name);
235 /* We'll assign a new address later */
236 r->end -= r->start;
237 r->start = 0;
238 }
239 }
240 }
241 if (!pass) {
242 r = &dev->resource[PCI_ROM_RESOURCE];
243 if (r->flags & PCI_ROM_ADDRESS_ENABLE) {
244 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
245 u32 reg;
246 DBG("PCI: Switching off ROM of %s\n", dev->slot_name);
247 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
248 pci_read_config_dword(dev, dev->rom_base_reg, ®);
249 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
250 }
251 }
252 }
253 }
254
255 static void __init pcibios_assign_resources(void)
256 {
257 struct pci_dev *dev;
258 int idx;
259 struct resource *r;
260
261 pci_for_each_dev(dev) {
262 int class = dev->class >> 8;
263
264 /* Don't touch classless devices and host bridges */
265 if (!class || class == PCI_CLASS_BRIDGE_HOST)
266 continue;
267
268 for(idx=0; idx<6; idx++) {
269 r = &dev->resource[idx];
270
271 /*
272 * Don't touch IDE controllers and I/O ports of video cards!
273 */
274 if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
275 (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
276 continue;
277
278 /*
279 * We shall assign a new address to this resource, either because
280 * the BIOS forgot to do so or because we have decided the old
281 * address was unusable for some reason.
282 */
283 if (!r->start && r->end)
284 pci_assign_resource(dev, idx);
285 }
286
287 if (pci_probe & PCI_ASSIGN_ROMS) {
288 r = &dev->resource[PCI_ROM_RESOURCE];
289 r->end -= r->start;
290 r->start = 0;
291 if (r->end)
292 pci_assign_resource(dev, PCI_ROM_RESOURCE);
293 }
294 }
295 }
296
297 void __init pcibios_resource_survey(void)
298 {
299 DBG("PCI: Allocating resources\n");
300 pcibios_allocate_bus_resources(&pci_root_buses);
301 pcibios_allocate_resources(0);
302 pcibios_allocate_resources(1);
303 pcibios_assign_resources();
304 }
305
306 int pcibios_enable_resources(struct pci_dev *dev)
307 {
308 u16 cmd, old_cmd;
309 int idx;
310 struct resource *r;
311
312 pci_read_config_word(dev, PCI_COMMAND, &cmd);
313 old_cmd = cmd;
314 for(idx=0; idx<6; idx++) {
315 r = &dev->resource[idx];
316 if (!r->start && r->end) {
317 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
318 return -EINVAL;
319 }
320 if (r->flags & IORESOURCE_IO)
321 cmd |= PCI_COMMAND_IO;
322 if (r->flags & IORESOURCE_MEM)
323 cmd |= PCI_COMMAND_MEMORY;
324 }
325 if (dev->resource[PCI_ROM_RESOURCE].start)
326 cmd |= PCI_COMMAND_MEMORY;
327 if (cmd != old_cmd) {
328 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
329 pci_write_config_word(dev, PCI_COMMAND, cmd);
330 }
331 return 0;
332 }
333
334 /*
335 * If we set up a device for bus mastering, we need to check the latency
336 * timer as certain crappy BIOSes forget to set it properly.
337 */
338 unsigned int pcibios_max_latency = 255;
339
340 void pcibios_set_master(struct pci_dev *dev)
341 {
342 u8 lat;
343 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
344 if (lat < 16)
345 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
346 else if (lat > pcibios_max_latency)
347 lat = pcibios_max_latency;
348 else
349 return;
350 printk("PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
351 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
352 }
353
354 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
355 enum pci_mmap_state mmap_state, int write_combine)
356 {
357 unsigned long prot;
358
359 /* I/O space cannot be accessed via normal processor loads and
360 * stores on this platform.
361 */
362 if (mmap_state == pci_mmap_io)
363 return -EINVAL;
364
365 /* Leave vm_pgoff as-is, the PCI space address is the physical
366 * address on this platform.
367 */
368 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
369
370 prot = pgprot_val(vma->vm_page_prot);
371 if (boot_cpu_data.x86 > 3)
372 prot |= _PAGE_PCD | _PAGE_PWT;
373 vma->vm_page_prot = __pgprot(prot);
374
375 /* Write-combine setting is ignored, it is changed via the mtrr
376 * interfaces on this platform.
377 */
378 if (remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
379 vma->vm_end - vma->vm_start,
380 vma->vm_page_prot))
381 return -EAGAIN;
382
383 return 0;
384 }
385