File: /usr/src/linux/arch/i386/kernel/setup.c
1 /*
2 * linux/arch/i386/kernel/setup.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 *
6 * Enhanced CPU type detection by Mike Jagdis, Patrick St. Jean
7 * and Martin Mares, November 1997.
8 *
9 * Force Cyrix 6x86(MX) and M II processors to report MTRR capability
10 * and Cyrix "coma bug" recognition by
11 * Zoltán Böszörményi <zboszor@mail.externet.hu> February 1999.
12 *
13 * Force Centaur C6 processors to report MTRR capability.
14 * Bart Hartgers <bart@etpmod.phys.tue.nl>, May 1999.
15 *
16 * Intel Mobile Pentium II detection fix. Sean Gilley, June 1999.
17 *
18 * IDT Winchip tweaks, misc clean ups.
19 * Dave Jones <davej@suse.de>, August 1999
20 *
21 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
22 *
23 * Better detection of Centaur/IDT WinChip models.
24 * Bart Hartgers <bart@etpmod.phys.tue.nl>, August 1999.
25 *
26 * Memory region support
27 * David Parsons <orc@pell.chi.il.us>, July-August 1999
28 *
29 * Cleaned up cache-detection code
30 * Dave Jones <davej@suse.de>, October 1999
31 *
32 * Added proper L2 cache detection for Coppermine
33 * Dragan Stancevic <visitor@valinux.com>, October 1999
34 *
35 * Added the original array for capability flags but forgot to credit
36 * myself :) (~1998) Fixed/cleaned up some cpu_model_info and other stuff
37 * Jauder Ho <jauderho@carumba.com>, January 2000
38 *
39 * Detection for Celeron coppermine, identify_cpu() overhauled,
40 * and a few other clean ups.
41 * Dave Jones <davej@suse.de>, April 2000
42 *
43 * Pentium III FXSR, SSE support
44 * General FPU state handling cleanups
45 * Gareth Hughes <gareth@valinux.com>, May 2000
46 *
47 * Added proper Cascades CPU and L2 cache detection for Cascades
48 * and 8-way type cache happy bunch from Intel:^)
49 * Dragan Stancevic <visitor@valinux.com>, May 2000
50 *
51 * Forward port AMD Duron errata T13 from 2.2.17pre
52 * Dave Jones <davej@suse.de>, August 2000
53 *
54 * Forward port lots of fixes/improvements from 2.2.18pre
55 * Cyrix III, Pentium IV support.
56 * Dave Jones <davej@suse.de>, October 2000
57 *
58 * Massive cleanup of CPU detection and bug handling;
59 * Transmeta CPU detection,
60 * H. Peter Anvin <hpa@zytor.com>, November 2000
61 *
62 * Added E820 sanitization routine (removes overlapping memory regions);
63 * Brian Moyle <bmoyle@mvista.com>, February 2001
64 *
65 * VIA C3 Support.
66 * Dave Jones <davej@suse.de>, March 2001
67 *
68 * AMD Athlon/Duron/Thunderbird bluesmoke support.
69 * Dave Jones <davej@suse.de>, April 2001.
70 */
71
72 /*
73 * This file handles the architecture-dependent parts of initialization
74 */
75
76 #include <linux/errno.h>
77 #include <linux/sched.h>
78 #include <linux/kernel.h>
79 #include <linux/mm.h>
80 #include <linux/stddef.h>
81 #include <linux/unistd.h>
82 #include <linux/ptrace.h>
83 #include <linux/slab.h>
84 #include <linux/user.h>
85 #include <linux/a.out.h>
86 #include <linux/tty.h>
87 #include <linux/ioport.h>
88 #include <linux/delay.h>
89 #include <linux/config.h>
90 #include <linux/init.h>
91 #include <linux/apm_bios.h>
92 #ifdef CONFIG_BLK_DEV_RAM
93 #include <linux/blk.h>
94 #endif
95 #include <linux/highmem.h>
96 #include <linux/bootmem.h>
97 #include <asm/processor.h>
98 #include <linux/console.h>
99 #include <asm/mtrr.h>
100 #include <asm/uaccess.h>
101 #include <asm/system.h>
102 #include <asm/io.h>
103 #include <asm/smp.h>
104 #include <asm/cobalt.h>
105 #include <asm/msr.h>
106 #include <asm/desc.h>
107 #include <asm/e820.h>
108 #include <asm/dma.h>
109 #include <asm/mpspec.h>
110 #include <asm/mmu_context.h>
111 /*
112 * Machine setup..
113 */
114
115 char ignore_irq13; /* set if exception 16 works */
116 struct cpuinfo_x86 boot_cpu_data = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
117
118 unsigned long mmu_cr4_features;
119
120 /*
121 * Bus types ..
122 */
123 #ifdef CONFIG_EISA
124 int EISA_bus;
125 #endif
126 int MCA_bus;
127
128 /* for MCA, but anyone else can use it if they want */
129 unsigned int machine_id;
130 unsigned int machine_submodel_id;
131 unsigned int BIOS_revision;
132 unsigned int mca_pentium_flag;
133
134 /* For PCI or other memory-mapped resources */
135 unsigned long pci_mem_start = 0x10000000;
136
137 /*
138 * Setup options
139 */
140 struct drive_info_struct { char dummy[32]; } drive_info;
141 struct screen_info screen_info;
142 struct apm_info apm_info;
143 struct sys_desc_table_struct {
144 unsigned short length;
145 unsigned char table[0];
146 };
147
148 struct e820map e820;
149
150 unsigned char aux_device_present;
151
152 extern void mcheck_init(struct cpuinfo_x86 *c);
153 extern int root_mountflags;
154 extern char _text, _etext, _edata, _end;
155
156 static int disable_x86_serial_nr __initdata = 1;
157 static int disable_x86_fxsr __initdata = 0;
158
159 /*
160 * This is set up by the setup-routine at boot-time
161 */
162 #define PARAM ((unsigned char *)empty_zero_page)
163 #define SCREEN_INFO (*(struct screen_info *) (PARAM+0))
164 #define EXT_MEM_K (*(unsigned short *) (PARAM+2))
165 #define ALT_MEM_K (*(unsigned long *) (PARAM+0x1e0))
166 #define E820_MAP_NR (*(char*) (PARAM+E820NR))
167 #define E820_MAP ((struct e820entry *) (PARAM+E820MAP))
168 #define APM_BIOS_INFO (*(struct apm_bios_info *) (PARAM+0x40))
169 #define DRIVE_INFO (*(struct drive_info_struct *) (PARAM+0x80))
170 #define SYS_DESC_TABLE (*(struct sys_desc_table_struct*)(PARAM+0xa0))
171 #define MOUNT_ROOT_RDONLY (*(unsigned short *) (PARAM+0x1F2))
172 #define RAMDISK_FLAGS (*(unsigned short *) (PARAM+0x1F8))
173 #define ORIG_ROOT_DEV (*(unsigned short *) (PARAM+0x1FC))
174 #define AUX_DEVICE_INFO (*(unsigned char *) (PARAM+0x1FF))
175 #define LOADER_TYPE (*(unsigned char *) (PARAM+0x210))
176 #define KERNEL_START (*(unsigned long *) (PARAM+0x214))
177 #define INITRD_START (*(unsigned long *) (PARAM+0x218))
178 #define INITRD_SIZE (*(unsigned long *) (PARAM+0x21c))
179 #define COMMAND_LINE ((char *) (PARAM+2048))
180 #define COMMAND_LINE_SIZE 256
181
182 #define RAMDISK_IMAGE_START_MASK 0x07FF
183 #define RAMDISK_PROMPT_FLAG 0x8000
184 #define RAMDISK_LOAD_FLAG 0x4000
185
186 #ifdef CONFIG_VISWS
187 char visws_board_type = -1;
188 char visws_board_rev = -1;
189
190 #define PIIX_PM_START 0x0F80
191
192 #define SIO_GPIO_START 0x0FC0
193
194 #define SIO_PM_START 0x0FC8
195
196 #define PMBASE PIIX_PM_START
197 #define GPIREG0 (PMBASE+0x30)
198 #define GPIREG(x) (GPIREG0+((x)/8))
199 #define PIIX_GPI_BD_ID1 18
200 #define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1)
201
202 #define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8)
203
204 #define SIO_INDEX 0x2e
205 #define SIO_DATA 0x2f
206
207 #define SIO_DEV_SEL 0x7
208 #define SIO_DEV_ENB 0x30
209 #define SIO_DEV_MSB 0x60
210 #define SIO_DEV_LSB 0x61
211
212 #define SIO_GP_DEV 0x7
213
214 #define SIO_GP_BASE SIO_GPIO_START
215 #define SIO_GP_MSB (SIO_GP_BASE>>8)
216 #define SIO_GP_LSB (SIO_GP_BASE&0xff)
217
218 #define SIO_GP_DATA1 (SIO_GP_BASE+0)
219
220 #define SIO_PM_DEV 0x8
221
222 #define SIO_PM_BASE SIO_PM_START
223 #define SIO_PM_MSB (SIO_PM_BASE>>8)
224 #define SIO_PM_LSB (SIO_PM_BASE&0xff)
225 #define SIO_PM_INDEX (SIO_PM_BASE+0)
226 #define SIO_PM_DATA (SIO_PM_BASE+1)
227
228 #define SIO_PM_FER2 0x1
229
230 #define SIO_PM_GP_EN 0x80
231
232 static void
233 visws_get_board_type_and_rev(void)
234 {
235 int raw;
236
237 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
238 >> PIIX_GPI_BD_SHIFT;
239 /*
240 * Get Board rev.
241 * First, we have to initialize the 307 part to allow us access
242 * to the GPIO registers. Let's map them at 0x0fc0 which is right
243 * after the PIIX4 PM section.
244 */
245 outb_p(SIO_DEV_SEL, SIO_INDEX);
246 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
247
248 outb_p(SIO_DEV_MSB, SIO_INDEX);
249 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
250
251 outb_p(SIO_DEV_LSB, SIO_INDEX);
252 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
253
254 outb_p(SIO_DEV_ENB, SIO_INDEX);
255 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
256
257 /*
258 * Now, we have to map the power management section to write
259 * a bit which enables access to the GPIO registers.
260 * What lunatic came up with this shit?
261 */
262 outb_p(SIO_DEV_SEL, SIO_INDEX);
263 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
264
265 outb_p(SIO_DEV_MSB, SIO_INDEX);
266 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
267
268 outb_p(SIO_DEV_LSB, SIO_INDEX);
269 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
270
271 outb_p(SIO_DEV_ENB, SIO_INDEX);
272 outb_p(1, SIO_DATA); /* Enable PM registers. */
273
274 /*
275 * Now, write the PM register which enables the GPIO registers.
276 */
277 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
278 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
279
280 /*
281 * Now, initialize the GPIO registers.
282 * We want them all to be inputs which is the
283 * power on default, so let's leave them alone.
284 * So, let's just read the board rev!
285 */
286 raw = inb_p(SIO_GP_DATA1);
287 raw &= 0x7f; /* 7 bits of valid board revision ID. */
288
289 if (visws_board_type == VISWS_320) {
290 if (raw < 0x6) {
291 visws_board_rev = 4;
292 } else if (raw < 0xc) {
293 visws_board_rev = 5;
294 } else {
295 visws_board_rev = 6;
296
297 }
298 } else if (visws_board_type == VISWS_540) {
299 visws_board_rev = 2;
300 } else {
301 visws_board_rev = raw;
302 }
303
304 printk(KERN_INFO "Silicon Graphics %s (rev %d)\n",
305 visws_board_type == VISWS_320 ? "320" :
306 (visws_board_type == VISWS_540 ? "540" :
307 "unknown"),
308 visws_board_rev);
309 }
310 #endif
311
312
313 static char command_line[COMMAND_LINE_SIZE];
314 char saved_command_line[COMMAND_LINE_SIZE];
315
316 struct resource standard_io_resources[] = {
317 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
318 { "pic1", 0x20, 0x3f, IORESOURCE_BUSY },
319 { "timer", 0x40, 0x5f, IORESOURCE_BUSY },
320 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
321 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
322 { "pic2", 0xa0, 0xbf, IORESOURCE_BUSY },
323 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
324 { "fpu", 0xf0, 0xff, IORESOURCE_BUSY }
325 };
326
327 #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
328
329 static struct resource code_resource = { "Kernel code", 0x100000, 0 };
330 static struct resource data_resource = { "Kernel data", 0, 0 };
331 static struct resource vram_resource = { "Video RAM area", 0xa0000, 0xbffff, IORESOURCE_BUSY };
332
333 /* System ROM resources */
334 #define MAXROMS 6
335 static struct resource rom_resources[MAXROMS] = {
336 { "System ROM", 0xF0000, 0xFFFFF, IORESOURCE_BUSY },
337 { "Video ROM", 0xc0000, 0xc7fff, IORESOURCE_BUSY }
338 };
339
340 #define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
341
342 static void __init probe_roms(void)
343 {
344 int roms = 1;
345 unsigned long base;
346 unsigned char *romstart;
347
348 request_resource(&iomem_resource, rom_resources+0);
349
350 /* Video ROM is standard at C000:0000 - C7FF:0000, check signature */
351 for (base = 0xC0000; base < 0xE0000; base += 2048) {
352 romstart = bus_to_virt(base);
353 if (!romsignature(romstart))
354 continue;
355 request_resource(&iomem_resource, rom_resources + roms);
356 roms++;
357 break;
358 }
359
360 /* Extension roms at C800:0000 - DFFF:0000 */
361 for (base = 0xC8000; base < 0xE0000; base += 2048) {
362 unsigned long length;
363
364 romstart = bus_to_virt(base);
365 if (!romsignature(romstart))
366 continue;
367 length = romstart[2] * 512;
368 if (length) {
369 unsigned int i;
370 unsigned char chksum;
371
372 chksum = 0;
373 for (i = 0; i < length; i++)
374 chksum += romstart[i];
375
376 /* Good checksum? */
377 if (!chksum) {
378 rom_resources[roms].start = base;
379 rom_resources[roms].end = base + length - 1;
380 rom_resources[roms].name = "Extension ROM";
381 rom_resources[roms].flags = IORESOURCE_BUSY;
382
383 request_resource(&iomem_resource, rom_resources + roms);
384 roms++;
385 if (roms >= MAXROMS)
386 return;
387 }
388 }
389 }
390
391 /* Final check for motherboard extension rom at E000:0000 */
392 base = 0xE0000;
393 romstart = bus_to_virt(base);
394
395 if (romsignature(romstart)) {
396 rom_resources[roms].start = base;
397 rom_resources[roms].end = base + 65535;
398 rom_resources[roms].name = "Extension ROM";
399 rom_resources[roms].flags = IORESOURCE_BUSY;
400
401 request_resource(&iomem_resource, rom_resources + roms);
402 }
403 }
404
405 void __init add_memory_region(unsigned long long start,
406 unsigned long long size, int type)
407 {
408 int x = e820.nr_map;
409
410 if (x == E820MAX) {
411 printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
412 return;
413 }
414
415 e820.map[x].addr = start;
416 e820.map[x].size = size;
417 e820.map[x].type = type;
418 e820.nr_map++;
419 } /* add_memory_region */
420
421 #define E820_DEBUG 1
422
423 static void __init print_memory_map(char *who)
424 {
425 int i;
426
427 for (i = 0; i < e820.nr_map; i++) {
428 printk(" %s: %016Lx - %016Lx ", who,
429 e820.map[i].addr,
430 e820.map[i].addr + e820.map[i].size);
431 switch (e820.map[i].type) {
432 case E820_RAM: printk("(usable)\n");
433 break;
434 case E820_RESERVED:
435 printk("(reserved)\n");
436 break;
437 case E820_ACPI:
438 printk("(ACPI data)\n");
439 break;
440 case E820_NVS:
441 printk("(ACPI NVS)\n");
442 break;
443 default: printk("type %lu\n", e820.map[i].type);
444 break;
445 }
446 }
447 }
448
449 /*
450 * Sanitize the BIOS e820 map.
451 *
452 * Some e820 responses include overlapping entries. The following
453 * replaces the original e820 map with a new one, removing overlaps.
454 *
455 */
456 static int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map)
457 {
458 struct change_member {
459 struct e820entry *pbios; /* pointer to original bios entry */
460 unsigned long long addr; /* address for this change point */
461 };
462 struct change_member change_point_list[2*E820MAX];
463 struct change_member *change_point[2*E820MAX];
464 struct e820entry *overlap_list[E820MAX];
465 struct e820entry new_bios[E820MAX];
466 struct change_member *change_tmp;
467 unsigned long current_type, last_type;
468 unsigned long long last_addr;
469 int chgidx, still_changing;
470 int overlap_entries;
471 int new_bios_entry;
472 int old_nr, new_nr;
473 int i;
474
475 /*
476 Visually we're performing the following (1,2,3,4 = memory types)...
477
478 Sample memory map (w/overlaps):
479 ____22__________________
480 ______________________4_
481 ____1111________________
482 _44_____________________
483 11111111________________
484 ____________________33__
485 ___________44___________
486 __________33333_________
487 ______________22________
488 ___________________2222_
489 _________111111111______
490 _____________________11_
491 _________________4______
492
493 Sanitized equivalent (no overlap):
494 1_______________________
495 _44_____________________
496 ___1____________________
497 ____22__________________
498 ______11________________
499 _________1______________
500 __________3_____________
501 ___________44___________
502 _____________33_________
503 _______________2________
504 ________________1_______
505 _________________4______
506 ___________________2____
507 ____________________33__
508 ______________________4_
509 */
510
511 /* if there's only one memory region, don't bother */
512 if (*pnr_map < 2)
513 return -1;
514
515 old_nr = *pnr_map;
516
517 /* bail out if we find any unreasonable addresses in bios map */
518 for (i=0; i<old_nr; i++)
519 if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr)
520 return -1;
521
522 /* create pointers for initial change-point information (for sorting) */
523 for (i=0; i < 2*old_nr; i++)
524 change_point[i] = &change_point_list[i];
525
526 /* record all known change-points (starting and ending addresses) */
527 chgidx = 0;
528 for (i=0; i < old_nr; i++) {
529 change_point[chgidx]->addr = biosmap[i].addr;
530 change_point[chgidx++]->pbios = &biosmap[i];
531 change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size;
532 change_point[chgidx++]->pbios = &biosmap[i];
533 }
534
535 /* sort change-point list by memory addresses (low -> high) */
536 still_changing = 1;
537 while (still_changing) {
538 still_changing = 0;
539 for (i=1; i < 2*old_nr; i++) {
540 /* if <current_addr> > <last_addr>, swap */
541 /* or, if current=<start_addr> & last=<end_addr>, swap */
542 if ((change_point[i]->addr < change_point[i-1]->addr) ||
543 ((change_point[i]->addr == change_point[i-1]->addr) &&
544 (change_point[i]->addr == change_point[i]->pbios->addr) &&
545 (change_point[i-1]->addr != change_point[i-1]->pbios->addr))
546 )
547 {
548 change_tmp = change_point[i];
549 change_point[i] = change_point[i-1];
550 change_point[i-1] = change_tmp;
551 still_changing=1;
552 }
553 }
554 }
555
556 /* create a new bios memory map, removing overlaps */
557 overlap_entries=0; /* number of entries in the overlap table */
558 new_bios_entry=0; /* index for creating new bios map entries */
559 last_type = 0; /* start with undefined memory type */
560 last_addr = 0; /* start with 0 as last starting address */
561 /* loop through change-points, determining affect on the new bios map */
562 for (chgidx=0; chgidx < 2*old_nr; chgidx++)
563 {
564 /* keep track of all overlapping bios entries */
565 if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr)
566 {
567 /* add map entry to overlap list (> 1 entry implies an overlap) */
568 overlap_list[overlap_entries++]=change_point[chgidx]->pbios;
569 }
570 else
571 {
572 /* remove entry from list (order independent, so swap with last) */
573 for (i=0; i<overlap_entries; i++)
574 {
575 if (overlap_list[i] == change_point[chgidx]->pbios)
576 overlap_list[i] = overlap_list[overlap_entries-1];
577 }
578 overlap_entries--;
579 }
580 /* if there are overlapping entries, decide which "type" to use */
581 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
582 current_type = 0;
583 for (i=0; i<overlap_entries; i++)
584 if (overlap_list[i]->type > current_type)
585 current_type = overlap_list[i]->type;
586 /* continue building up new bios map based on this information */
587 if (current_type != last_type) {
588 if (last_type != 0) {
589 new_bios[new_bios_entry].size =
590 change_point[chgidx]->addr - last_addr;
591 /* move forward only if the new size was non-zero */
592 if (new_bios[new_bios_entry].size != 0)
593 if (++new_bios_entry >= E820MAX)
594 break; /* no more space left for new bios entries */
595 }
596 if (current_type != 0) {
597 new_bios[new_bios_entry].addr = change_point[chgidx]->addr;
598 new_bios[new_bios_entry].type = current_type;
599 last_addr=change_point[chgidx]->addr;
600 }
601 last_type = current_type;
602 }
603 }
604 new_nr = new_bios_entry; /* retain count for new bios entries */
605
606 /* copy new bios mapping into original location */
607 memcpy(biosmap, new_bios, new_nr*sizeof(struct e820entry));
608 *pnr_map = new_nr;
609
610 return 0;
611 }
612
613 /*
614 * Copy the BIOS e820 map into a safe place.
615 *
616 * Sanity-check it while we're at it..
617 *
618 * If we're lucky and live on a modern system, the setup code
619 * will have given us a memory map that we can use to properly
620 * set up memory. If we aren't, we'll fake a memory map.
621 *
622 * We check to see that the memory map contains at least 2 elements
623 * before we'll use it, because the detection code in setup.S may
624 * not be perfect and most every PC known to man has two memory
625 * regions: one from 0 to 640k, and one from 1mb up. (The IBM
626 * thinkpad 560x, for example, does not cooperate with the memory
627 * detection code.)
628 */
629 static int __init copy_e820_map(struct e820entry * biosmap, int nr_map)
630 {
631 /* Only one memory region (or negative)? Ignore it */
632 if (nr_map < 2)
633 return -1;
634
635 do {
636 unsigned long long start = biosmap->addr;
637 unsigned long long size = biosmap->size;
638 unsigned long long end = start + size;
639 unsigned long type = biosmap->type;
640
641 /* Overflow in 64 bits? Ignore the memory map. */
642 if (start > end)
643 return -1;
644
645 /*
646 * Some BIOSes claim RAM in the 640k - 1M region.
647 * Not right. Fix it up.
648 */
649 if (type == E820_RAM) {
650 if (start < 0x100000ULL && end > 0xA0000ULL) {
651 if (start < 0xA0000ULL)
652 add_memory_region(start, 0xA0000ULL-start, type);
653 if (end <= 0x100000ULL)
654 continue;
655 start = 0x100000ULL;
656 size = end - start;
657 }
658 }
659 add_memory_region(start, size, type);
660 } while (biosmap++,--nr_map);
661 return 0;
662 }
663
664 /*
665 * Do NOT EVER look at the BIOS memory size location.
666 * It does not work on many machines.
667 */
668 #define LOWMEMSIZE() (0x9f000)
669
670 void __init setup_memory_region(void)
671 {
672 char *who = "BIOS-e820";
673
674 /*
675 * Try to copy the BIOS-supplied E820-map.
676 *
677 * Otherwise fake a memory map; one section from 0k->640k,
678 * the next section from 1mb->appropriate_mem_k
679 */
680 sanitize_e820_map(E820_MAP, &E820_MAP_NR);
681 if (copy_e820_map(E820_MAP, E820_MAP_NR) < 0) {
682 unsigned long mem_size;
683
684 /* compare results from other methods and take the greater */
685 if (ALT_MEM_K < EXT_MEM_K) {
686 mem_size = EXT_MEM_K;
687 who = "BIOS-88";
688 } else {
689 mem_size = ALT_MEM_K;
690 who = "BIOS-e801";
691 }
692
693 e820.nr_map = 0;
694 add_memory_region(0, LOWMEMSIZE(), E820_RAM);
695 add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM);
696 }
697 printk(KERN_INFO "BIOS-provided physical RAM map:\n");
698 print_memory_map(who);
699 } /* setup_memory_region */
700
701
702 static inline void parse_mem_cmdline (char ** cmdline_p)
703 {
704 char c = ' ', *to = command_line, *from = COMMAND_LINE;
705 int len = 0;
706 int usermem = 0;
707
708 /* Save unparsed command line copy for /proc/cmdline */
709 memcpy(saved_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
710 saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
711
712 for (;;) {
713 /*
714 * "mem=nopentium" disables the 4MB page tables.
715 * "mem=XXX[kKmM]" defines a memory region from HIGH_MEM
716 * to <mem>, overriding the bios size.
717 * "mem=XXX[KkmM]@XXX[KkmM]" defines a memory region from
718 * <start> to <start>+<mem>, overriding the bios size.
719 */
720 if (c == ' ' && !memcmp(from, "mem=", 4)) {
721 if (to != command_line)
722 to--;
723 if (!memcmp(from+4, "nopentium", 9)) {
724 from += 9+4;
725 clear_bit(X86_FEATURE_PSE, &boot_cpu_data.x86_capability);
726 } else if (!memcmp(from+4, "exactmap", 8)) {
727 from += 8+4;
728 e820.nr_map = 0;
729 usermem = 1;
730 } else {
731 /* If the user specifies memory size, we
732 * blow away any automatically generated
733 * size
734 */
735 unsigned long long start_at, mem_size;
736
737 if (usermem == 0) {
738 /* first time in: zap the whitelist
739 * and reinitialize it with the
740 * standard low-memory region.
741 */
742 e820.nr_map = 0;
743 usermem = 1;
744 add_memory_region(0, LOWMEMSIZE(), E820_RAM);
745 }
746 mem_size = memparse(from+4, &from);
747 if (*from == '@')
748 start_at = memparse(from+1, &from);
749 else {
750 start_at = HIGH_MEMORY;
751 mem_size -= HIGH_MEMORY;
752 usermem=0;
753 }
754 add_memory_region(start_at, mem_size, E820_RAM);
755 }
756 }
757 c = *(from++);
758 if (!c)
759 break;
760 if (COMMAND_LINE_SIZE <= ++len)
761 break;
762 *(to++) = c;
763 }
764 *to = '\0';
765 *cmdline_p = command_line;
766 if (usermem) {
767 printk(KERN_INFO "user-defined physical RAM map:\n");
768 print_memory_map("user");
769 }
770 }
771
772 void __init setup_arch(char **cmdline_p)
773 {
774 unsigned long bootmap_size, low_mem_size;
775 unsigned long start_pfn, max_pfn, max_low_pfn;
776 int i;
777
778 #ifdef CONFIG_VISWS
779 visws_get_board_type_and_rev();
780 #endif
781
782 ROOT_DEV = to_kdev_t(ORIG_ROOT_DEV);
783 drive_info = DRIVE_INFO;
784 screen_info = SCREEN_INFO;
785 apm_info.bios = APM_BIOS_INFO;
786 if( SYS_DESC_TABLE.length != 0 ) {
787 MCA_bus = SYS_DESC_TABLE.table[3] &0x2;
788 machine_id = SYS_DESC_TABLE.table[0];
789 machine_submodel_id = SYS_DESC_TABLE.table[1];
790 BIOS_revision = SYS_DESC_TABLE.table[2];
791 }
792 aux_device_present = AUX_DEVICE_INFO;
793
794 #ifdef CONFIG_BLK_DEV_RAM
795 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
796 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
797 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
798 #endif
799 setup_memory_region();
800
801 if (!MOUNT_ROOT_RDONLY)
802 root_mountflags &= ~MS_RDONLY;
803 init_mm.start_code = (unsigned long) &_text;
804 init_mm.end_code = (unsigned long) &_etext;
805 init_mm.end_data = (unsigned long) &_edata;
806 init_mm.brk = (unsigned long) &_end;
807
808 code_resource.start = virt_to_bus(&_text);
809 code_resource.end = virt_to_bus(&_etext)-1;
810 data_resource.start = virt_to_bus(&_etext);
811 data_resource.end = virt_to_bus(&_edata)-1;
812
813 parse_mem_cmdline(cmdline_p);
814
815 #define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
816 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
817 #define PFN_PHYS(x) ((x) << PAGE_SHIFT)
818
819 /*
820 * 128MB for vmalloc and initrd
821 */
822 #define VMALLOC_RESERVE (unsigned long)(128 << 20)
823 #define MAXMEM (unsigned long)(-PAGE_OFFSET-VMALLOC_RESERVE)
824 #define MAXMEM_PFN PFN_DOWN(MAXMEM)
825 #define MAX_NONPAE_PFN (1 << 20)
826
827 /*
828 * partially used pages are not usable - thus
829 * we are rounding upwards:
830 */
831 start_pfn = PFN_UP(__pa(&_end));
832
833 /*
834 * Find the highest page frame number we have available
835 */
836 max_pfn = 0;
837 for (i = 0; i < e820.nr_map; i++) {
838 unsigned long start, end;
839 /* RAM? */
840 if (e820.map[i].type != E820_RAM)
841 continue;
842 start = PFN_UP(e820.map[i].addr);
843 end = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
844 if (start >= end)
845 continue;
846 if (end > max_pfn)
847 max_pfn = end;
848 }
849
850 /*
851 * Determine low and high memory ranges:
852 */
853 max_low_pfn = max_pfn;
854 if (max_low_pfn > MAXMEM_PFN) {
855 max_low_pfn = MAXMEM_PFN;
856 #ifndef CONFIG_HIGHMEM
857 /* Maximum memory usable is what is directly addressable */
858 printk(KERN_WARNING "Warning only %ldMB will be used.\n",
859 MAXMEM>>20);
860 if (max_pfn > MAX_NONPAE_PFN)
861 printk(KERN_WARNING "Use a PAE enabled kernel.\n");
862 else
863 printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
864 #else /* !CONFIG_HIGHMEM */
865 #ifndef CONFIG_X86_PAE
866 if (max_pfn > MAX_NONPAE_PFN) {
867 max_pfn = MAX_NONPAE_PFN;
868 printk(KERN_WARNING "Warning only 4GB will be used.\n");
869 printk(KERN_WARNING "Use a PAE enabled kernel.\n");
870 }
871 #endif /* !CONFIG_X86_PAE */
872 #endif /* !CONFIG_HIGHMEM */
873 }
874
875 #ifdef CONFIG_HIGHMEM
876 highstart_pfn = highend_pfn = max_pfn;
877 if (max_pfn > MAXMEM_PFN) {
878 highstart_pfn = MAXMEM_PFN;
879 printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
880 pages_to_mb(highend_pfn - highstart_pfn));
881 }
882 #endif
883 /*
884 * Initialize the boot-time allocator (with low memory only):
885 */
886 bootmap_size = init_bootmem(start_pfn, max_low_pfn);
887
888 /*
889 * Register fully available low RAM pages with the bootmem allocator.
890 */
891 for (i = 0; i < e820.nr_map; i++) {
892 unsigned long curr_pfn, last_pfn, size;
893 /*
894 * Reserve usable low memory
895 */
896 if (e820.map[i].type != E820_RAM)
897 continue;
898 /*
899 * We are rounding up the start address of usable memory:
900 */
901 curr_pfn = PFN_UP(e820.map[i].addr);
902 if (curr_pfn >= max_low_pfn)
903 continue;
904 /*
905 * ... and at the end of the usable range downwards:
906 */
907 last_pfn = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
908
909 if (last_pfn > max_low_pfn)
910 last_pfn = max_low_pfn;
911
912 /*
913 * .. finally, did all the rounding and playing
914 * around just make the area go away?
915 */
916 if (last_pfn <= curr_pfn)
917 continue;
918
919 size = last_pfn - curr_pfn;
920 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
921 }
922 /*
923 * Reserve the bootmem bitmap itself as well. We do this in two
924 * steps (first step was init_bootmem()) because this catches
925 * the (very unlikely) case of us accidentally initializing the
926 * bootmem allocator with an invalid RAM area.
927 */
928 reserve_bootmem(HIGH_MEMORY, (PFN_PHYS(start_pfn) +
929 bootmap_size + PAGE_SIZE-1) - (HIGH_MEMORY));
930
931 /*
932 * reserve physical page 0 - it's a special BIOS page on many boxes,
933 * enabling clean reboots, SMP operation, laptop functions.
934 */
935 reserve_bootmem(0, PAGE_SIZE);
936
937 #ifdef CONFIG_SMP
938 /*
939 * But first pinch a few for the stack/trampoline stuff
940 * FIXME: Don't need the extra page at 4K, but need to fix
941 * trampoline before removing it. (see the GDT stuff)
942 */
943 reserve_bootmem(PAGE_SIZE, PAGE_SIZE);
944 #endif
945
946 #ifdef CONFIG_X86_LOCAL_APIC
947 /*
948 * Find and reserve possible boot-time SMP configuration:
949 */
950 find_smp_config();
951 #endif
952 #ifdef CONFIG_BLK_DEV_INITRD
953 if (LOADER_TYPE && INITRD_START) {
954 if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
955 reserve_bootmem(INITRD_START, INITRD_SIZE);
956 initrd_start =
957 INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
958 initrd_end = initrd_start+INITRD_SIZE;
959 }
960 else {
961 printk(KERN_ERR "initrd extends beyond end of memory "
962 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
963 INITRD_START + INITRD_SIZE,
964 max_low_pfn << PAGE_SHIFT);
965 initrd_start = 0;
966 }
967 }
968 #endif
969
970 /*
971 * NOTE: before this point _nobody_ is allowed to allocate
972 * any memory using the bootmem allocator.
973 */
974
975 #ifdef CONFIG_SMP
976 smp_alloc_memory(); /* AP processor realmode stacks in low memory*/
977 #endif
978 paging_init();
979 #ifdef CONFIG_X86_LOCAL_APIC
980 /*
981 * get boot-time SMP configuration:
982 */
983 if (smp_found_config)
984 get_smp_config();
985 init_apic_mappings();
986 #endif
987
988
989 /*
990 * Request address space for all standard RAM and ROM resources
991 * and also for regions reported as reserved by the e820.
992 */
993 probe_roms();
994 for (i = 0; i < e820.nr_map; i++) {
995 struct resource *res;
996 if (e820.map[i].addr + e820.map[i].size > 0x100000000ULL)
997 continue;
998 res = alloc_bootmem_low(sizeof(struct resource));
999 switch (e820.map[i].type) {
1000 case E820_RAM: res->name = "System RAM"; break;
1001 case E820_ACPI: res->name = "ACPI Tables"; break;
1002 case E820_NVS: res->name = "ACPI Non-volatile Storage"; break;
1003 default: res->name = "reserved";
1004 }
1005 res->start = e820.map[i].addr;
1006 res->end = res->start + e820.map[i].size - 1;
1007 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
1008 request_resource(&iomem_resource, res);
1009 if (e820.map[i].type == E820_RAM) {
1010 /*
1011 * We dont't know which RAM region contains kernel data,
1012 * so we try it repeatedly and let the resource manager
1013 * test it.
1014 */
1015 request_resource(res, &code_resource);
1016 request_resource(res, &data_resource);
1017 }
1018 }
1019 request_resource(&iomem_resource, &vram_resource);
1020
1021 /* request I/O space for devices used on all i[345]86 PCs */
1022 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
1023 request_resource(&ioport_resource, standard_io_resources+i);
1024
1025 /* Tell the PCI layer not to allocate too close to the RAM area.. */
1026 low_mem_size = ((max_low_pfn << PAGE_SHIFT) + 0xfffff) & ~0xfffff;
1027 if (low_mem_size > pci_mem_start)
1028 pci_mem_start = low_mem_size;
1029
1030 #ifdef CONFIG_VT
1031 #if defined(CONFIG_VGA_CONSOLE)
1032 conswitchp = &vga_con;
1033 #elif defined(CONFIG_DUMMY_CONSOLE)
1034 conswitchp = &dummy_con;
1035 #endif
1036 #endif
1037 }
1038
1039 #ifndef CONFIG_X86_TSC
1040 static int tsc_disable __initdata = 0;
1041
1042 static int __init tsc_setup(char *str)
1043 {
1044 tsc_disable = 1;
1045 return 1;
1046 }
1047
1048 __setup("notsc", tsc_setup);
1049 #endif
1050
1051 static int __init get_model_name(struct cpuinfo_x86 *c)
1052 {
1053 unsigned int *v;
1054 char *p, *q;
1055
1056 if (cpuid_eax(0x80000000) < 0x80000004)
1057 return 0;
1058
1059 v = (unsigned int *) c->x86_model_id;
1060 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
1061 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
1062 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
1063 c->x86_model_id[48] = 0;
1064
1065 /* Intel chips right-justify this string for some dumb reason;
1066 undo that brain damage */
1067 p = q = &c->x86_model_id[0];
1068 while ( *p == ' ' )
1069 p++;
1070 if ( p != q ) {
1071 while ( *p )
1072 *q++ = *p++;
1073 while ( q <= &c->x86_model_id[48] )
1074 *q++ = '\0'; /* Zero-pad the rest */
1075 }
1076
1077 return 1;
1078 }
1079
1080
1081 static void __init display_cacheinfo(struct cpuinfo_x86 *c)
1082 {
1083 unsigned int n, dummy, ecx, edx, l2size;
1084
1085 n = cpuid_eax(0x80000000);
1086
1087 if (n >= 0x80000005) {
1088 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
1089 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
1090 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
1091 c->x86_cache_size=(ecx>>24)+(edx>>24);
1092 }
1093
1094 if (n < 0x80000006) /* Some chips just has a large L1. */
1095 return;
1096
1097 ecx = cpuid_ecx(0x80000006);
1098 l2size = ecx >> 16;
1099
1100 /* AMD errata T13 (order #21922) */
1101 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
1102 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
1103 l2size = 64;
1104 if (c->x86_model == 4 &&
1105 (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
1106 l2size = 256;
1107 }
1108
1109 /* VIA C3 CPUs (670-68F) need further shifting. */
1110 if (c->x86_vendor == X86_VENDOR_CENTAUR && (c->x86 == 6) &&
1111 ((c->x86_model == 7) || (c->x86_model == 8))) {
1112 l2size = l2size >> 8;
1113 }
1114
1115 if ( l2size == 0 )
1116 return; /* Again, no L2 cache is possible */
1117
1118 c->x86_cache_size = l2size;
1119
1120 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
1121 l2size, ecx & 0xFF);
1122 }
1123
1124 /*
1125 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
1126 * misexecution of code under Linux. Owners of such processors should
1127 * contact AMD for precise details and a CPU swap.
1128 *
1129 * See http://www.multimania.com/poulot/k6bug.html
1130 * http://www.amd.com/K6/k6docs/revgd.html
1131 *
1132 * The following test is erm.. interesting. AMD neglected to up
1133 * the chip setting when fixing the bug but they also tweaked some
1134 * performance at the same time..
1135 */
1136
1137 extern void vide(void);
1138 __asm__(".align 4\nvide: ret");
1139
1140 static int __init init_amd(struct cpuinfo_x86 *c)
1141 {
1142 u32 l, h;
1143 int mbytes = max_mapnr >> (20-PAGE_SHIFT);
1144 int r;
1145
1146 /*
1147 * FIXME: We should handle the K5 here. Set up the write
1148 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
1149 * no bus pipeline)
1150 */
1151
1152 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1153 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
1154 clear_bit(0*32+31, &c->x86_capability);
1155
1156 r = get_model_name(c);
1157
1158 switch(c->x86)
1159 {
1160 case 5:
1161 if( c->x86_model < 6 )
1162 {
1163 /* Based on AMD doc 20734R - June 2000 */
1164 if ( c->x86_model == 0 ) {
1165 clear_bit(X86_FEATURE_APIC, &c->x86_capability);
1166 set_bit(X86_FEATURE_PGE, &c->x86_capability);
1167 }
1168 break;
1169 }
1170
1171 if ( c->x86_model == 6 && c->x86_mask == 1 ) {
1172 const int K6_BUG_LOOP = 1000000;
1173 int n;
1174 void (*f_vide)(void);
1175 unsigned long d, d2;
1176
1177 printk(KERN_INFO "AMD K6 stepping B detected - ");
1178
1179 /*
1180 * It looks like AMD fixed the 2.6.2 bug and improved indirect
1181 * calls at the same time.
1182 */
1183
1184 n = K6_BUG_LOOP;
1185 f_vide = vide;
1186 rdtscl(d);
1187 while (n--)
1188 f_vide();
1189 rdtscl(d2);
1190 d = d2-d;
1191
1192 /* Knock these two lines out if it debugs out ok */
1193 printk(KERN_INFO "K6 BUG %ld %d (Report these if test report is incorrect)\n", d, 20*K6_BUG_LOOP);
1194 printk(KERN_INFO "AMD K6 stepping B detected - ");
1195 /* -- cut here -- */
1196 if (d > 20*K6_BUG_LOOP)
1197 printk("system stability may be impaired when more than 32 MB are used.\n");
1198 else
1199 printk("probably OK (after B9730xxxx).\n");
1200 printk(KERN_INFO "Please see http://www.mygale.com/~poulot/k6bug.html\n");
1201 }
1202
1203 /* K6 with old style WHCR */
1204 if( c->x86_model < 8 ||
1205 (c->x86_model== 8 && c->x86_mask < 8))
1206 {
1207 /* We can only write allocate on the low 508Mb */
1208 if(mbytes>508)
1209 mbytes=508;
1210
1211 rdmsr(MSR_K6_WHCR, l, h);
1212 if ((l&0x0000FFFF)==0) {
1213 unsigned long flags;
1214 l=(1<<0)|((mbytes/4)<<1);
1215 local_irq_save(flags);
1216 wbinvd();
1217 wrmsr(MSR_K6_WHCR, l, h);
1218 local_irq_restore(flags);
1219 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
1220 mbytes);
1221
1222 }
1223 break;
1224 }
1225 if (c->x86_model == 8 || c->x86_model == 9 || c->x86_model == 13)
1226 {
1227 /* The more serious chips .. */
1228
1229 if(mbytes>4092)
1230 mbytes=4092;
1231
1232 rdmsr(MSR_K6_WHCR, l, h);
1233 if ((l&0xFFFF0000)==0) {
1234 unsigned long flags;
1235 l=((mbytes>>2)<<22)|(1<<16);
1236 local_irq_save(flags);
1237 wbinvd();
1238 wrmsr(MSR_K6_WHCR, l, h);
1239 local_irq_restore(flags);
1240 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
1241 mbytes);
1242 }
1243
1244 /* Set MTRR capability flag if appropriate */
1245 if ( (c->x86_model == 13) ||
1246 (c->x86_model == 9) ||
1247 ((c->x86_model == 8) &&
1248 (c->x86_mask >= 8)) )
1249 set_bit(X86_FEATURE_K6_MTRR, &c->x86_capability);
1250 break;
1251 }
1252 break;
1253
1254 case 6: /* An Athlon/Duron. We can trust the BIOS probably */
1255 mcheck_init(c);
1256 break;
1257 }
1258
1259 display_cacheinfo(c);
1260 return r;
1261 }
1262
1263 /*
1264 * Read Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
1265 */
1266 static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
1267 {
1268 unsigned char ccr2, ccr3;
1269 unsigned long flags;
1270
1271 /* we test for DEVID by checking whether CCR3 is writable */
1272 local_irq_save(flags);
1273 ccr3 = getCx86(CX86_CCR3);
1274 setCx86(CX86_CCR3, ccr3 ^ 0x80);
1275 getCx86(0xc0); /* dummy to change bus */
1276
1277 if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
1278 ccr2 = getCx86(CX86_CCR2);
1279 setCx86(CX86_CCR2, ccr2 ^ 0x04);
1280 getCx86(0xc0); /* dummy */
1281
1282 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
1283 *dir0 = 0xfd;
1284 else { /* Cx486S A step */
1285 setCx86(CX86_CCR2, ccr2);
1286 *dir0 = 0xfe;
1287 }
1288 }
1289 else {
1290 setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
1291
1292 /* read DIR0 and DIR1 CPU registers */
1293 *dir0 = getCx86(CX86_DIR0);
1294 *dir1 = getCx86(CX86_DIR1);
1295 }
1296 local_irq_restore(flags);
1297 }
1298
1299 /*
1300 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
1301 * order to identify the Cyrix CPU model after we're out of setup.c
1302 *
1303 * Actually since bugs.h doesnt even reference this perhaps someone should
1304 * fix the documentation ???
1305 */
1306 unsigned char Cx86_dir0_msb __initdata = 0;
1307
1308 static char Cx86_model[][9] __initdata = {
1309 "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
1310 "M II ", "Unknown"
1311 };
1312 static char Cx486_name[][5] __initdata = {
1313 "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
1314 "SRx2", "DRx2"
1315 };
1316 static char Cx486S_name[][4] __initdata = {
1317 "S", "S2", "Se", "S2e"
1318 };
1319 static char Cx486D_name[][4] __initdata = {
1320 "DX", "DX2", "?", "?", "?", "DX4"
1321 };
1322 static char Cx86_cb[] __initdata = "?.5x Core/Bus Clock";
1323 static char cyrix_model_mult1[] __initdata = "12??43";
1324 static char cyrix_model_mult2[] __initdata = "12233445";
1325
1326 /*
1327 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
1328 * BIOSes for compatability with DOS games. This makes the udelay loop
1329 * work correctly, and improves performance.
1330 *
1331 * FIXME: our newer udelay uses the tsc. We dont need to frob with SLOP
1332 */
1333
1334 extern void calibrate_delay(void) __init;
1335
1336 static void __init check_cx686_slop(struct cpuinfo_x86 *c)
1337 {
1338 unsigned long flags;
1339
1340 if (Cx86_dir0_msb == 3) {
1341 unsigned char ccr3, ccr5;
1342
1343 local_irq_save(flags);
1344 ccr3 = getCx86(CX86_CCR3);
1345 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
1346 ccr5 = getCx86(CX86_CCR5);
1347 if (ccr5 & 2)
1348 setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
1349 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
1350 local_irq_restore(flags);
1351
1352 if (ccr5 & 2) { /* possible wrong calibration done */
1353 printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
1354 calibrate_delay();
1355 c->loops_per_jiffy = loops_per_jiffy;
1356 }
1357 }
1358 }
1359
1360 static void __init init_cyrix(struct cpuinfo_x86 *c)
1361 {
1362 unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
1363 char *buf = c->x86_model_id;
1364 const char *p = NULL;
1365
1366 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1367 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
1368 clear_bit(0*32+31, &c->x86_capability);
1369
1370 /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
1371 if ( test_bit(1*32+24, &c->x86_capability) ) {
1372 clear_bit(1*32+24, &c->x86_capability);
1373 set_bit(X86_FEATURE_CXMMX, &c->x86_capability);
1374 }
1375
1376 do_cyrix_devid(&dir0, &dir1);
1377
1378 check_cx686_slop(c);
1379
1380 Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */
1381 dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
1382
1383 /* common case step number/rev -- exceptions handled below */
1384 c->x86_model = (dir1 >> 4) + 1;
1385 c->x86_mask = dir1 & 0xf;
1386
1387 /* Now cook; the original recipe is by Channing Corn, from Cyrix.
1388 * We do the same thing for each generation: we work out
1389 * the model, multiplier and stepping. Black magic included,
1390 * to make the silicon step/rev numbers match the printed ones.
1391 */
1392
1393 switch (dir0_msn) {
1394 unsigned char tmp;
1395
1396 case 0: /* Cx486SLC/DLC/SRx/DRx */
1397 p = Cx486_name[dir0_lsn & 7];
1398 break;
1399
1400 case 1: /* Cx486S/DX/DX2/DX4 */
1401 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
1402 : Cx486S_name[dir0_lsn & 3];
1403 break;
1404
1405 case 2: /* 5x86 */
1406 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
1407 p = Cx86_cb+2;
1408 break;
1409
1410 case 3: /* 6x86/6x86L */
1411 Cx86_cb[1] = ' ';
1412 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
1413 if (dir1 > 0x21) { /* 686L */
1414 Cx86_cb[0] = 'L';
1415 p = Cx86_cb;
1416 (c->x86_model)++;
1417 } else /* 686 */
1418 p = Cx86_cb+1;
1419 /* Emulate MTRRs using Cyrix's ARRs. */
1420 set_bit(X86_FEATURE_CYRIX_ARR, &c->x86_capability);
1421 /* 6x86's contain this bug */
1422 c->coma_bug = 1;
1423 break;
1424
1425 case 4: /* MediaGX/GXm */
1426 /*
1427 * Life sometimes gets weiiiiiiiird if we use this
1428 * on the MediaGX. So we turn it off for now.
1429 */
1430
1431 #ifdef CONFIG_PCI
1432 /* It isnt really a PCI quirk directly, but the cure is the
1433 same. The MediaGX has deep magic SMM stuff that handles the
1434 SB emulation. It thows away the fifo on disable_dma() which
1435 is wrong and ruins the audio.
1436
1437 Bug2: VSA1 has a wrap bug so that using maximum sized DMA
1438 causes bad things. According to NatSemi VSA2 has another
1439 bug to do with 'hlt'. I've not seen any boards using VSA2
1440 and X doesn't seem to support it either so who cares 8).
1441 VSA1 we work around however.
1442 */
1443
1444 printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
1445 isa_dma_bridge_buggy = 2;
1446 #endif
1447 c->x86_cache_size=16; /* Yep 16K integrated cache thats it */
1448
1449 /* GXm supports extended cpuid levels 'ala' AMD */
1450 if (c->cpuid_level == 2) {
1451 get_model_name(c); /* get CPU marketing name */
1452 clear_bit(X86_FEATURE_TSC, c->x86_capability);
1453 return;
1454 }
1455 else { /* MediaGX */
1456 Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
1457 p = Cx86_cb+2;
1458 c->x86_model = (dir1 & 0x20) ? 1 : 2;
1459 clear_bit(X86_FEATURE_TSC, &c->x86_capability);
1460 }
1461 break;
1462
1463 case 5: /* 6x86MX/M II */
1464 if (dir1 > 7)
1465 {
1466 dir0_msn++; /* M II */
1467 /* Enable MMX extensions (App note 108) */
1468 setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
1469 }
1470 else
1471 {
1472 c->coma_bug = 1; /* 6x86MX, it has the bug. */
1473 }
1474 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
1475 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
1476 p = Cx86_cb+tmp;
1477 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
1478 (c->x86_model)++;
1479 /* Emulate MTRRs using Cyrix's ARRs. */
1480 set_bit(X86_FEATURE_CYRIX_ARR, &c->x86_capability);
1481 break;
1482
1483 case 0xf: /* Cyrix 486 without DEVID registers */
1484 switch (dir0_lsn) {
1485 case 0xd: /* either a 486SLC or DLC w/o DEVID */
1486 dir0_msn = 0;
1487 p = Cx486_name[(c->hard_math) ? 1 : 0];
1488 break;
1489
1490 case 0xe: /* a 486S A step */
1491 dir0_msn = 0;
1492 p = Cx486S_name[0];
1493 break;
1494 }
1495 break;
1496
1497 default: /* unknown (shouldn't happen, we know everyone ;-) */
1498 dir0_msn = 7;
1499 break;
1500 }
1501 strcpy(buf, Cx86_model[dir0_msn & 7]);
1502 if (p) strcat(buf, p);
1503 return;
1504 }
1505
1506 static void __init init_centaur(struct cpuinfo_x86 *c)
1507 {
1508 enum {
1509 ECX8=1<<1,
1510 EIERRINT=1<<2,
1511 DPM=1<<3,
1512 DMCE=1<<4,
1513 DSTPCLK=1<<5,
1514 ELINEAR=1<<6,
1515 DSMC=1<<7,
1516 DTLOCK=1<<8,
1517 EDCTLB=1<<8,
1518 EMMX=1<<9,
1519 DPDC=1<<11,
1520 EBRPRED=1<<12,
1521 DIC=1<<13,
1522 DDC=1<<14,
1523 DNA=1<<15,
1524 ERETSTK=1<<16,
1525 E2MMX=1<<19,
1526 EAMD3D=1<<20,
1527 };
1528
1529 char *name;
1530 u32 fcr_set=0;
1531 u32 fcr_clr=0;
1532 u32 lo,hi,newlo;
1533 u32 aa,bb,cc,dd;
1534
1535 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1536 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
1537 clear_bit(0*32+31, &c->x86_capability);
1538
1539 switch (c->x86) {
1540
1541 case 5:
1542 switch(c->x86_model) {
1543 case 4:
1544 name="C6";
1545 fcr_set=ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
1546 fcr_clr=DPDC;
1547 printk(KERN_NOTICE "Disabling bugged TSC.\n");
1548 clear_bit(X86_FEATURE_TSC, &c->x86_capability);
1549 break;
1550 case 8:
1551 switch(c->x86_mask) {
1552 default:
1553 name="2";
1554 break;
1555 case 7 ... 9:
1556 name="2A";
1557 break;
1558 case 10 ... 15:
1559 name="2B";
1560 break;
1561 }
1562 fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
1563 fcr_clr=DPDC;
1564 break;
1565 case 9:
1566 name="3";
1567 fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
1568 fcr_clr=DPDC;
1569 break;
1570 case 10:
1571 name="4";
1572 /* no info on the WC4 yet */
1573 break;
1574 default:
1575 name="??";
1576 }
1577
1578 rdmsr(MSR_IDT_FCR1, lo, hi);
1579 newlo=(lo|fcr_set) & (~fcr_clr);
1580
1581 if (newlo!=lo) {
1582 printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo );
1583 wrmsr(MSR_IDT_FCR1, newlo, hi );
1584 } else {
1585 printk(KERN_INFO "Centaur FCR is 0x%X\n",lo);
1586 }
1587 /* Emulate MTRRs using Centaur's MCR. */
1588 set_bit(X86_FEATURE_CENTAUR_MCR, &c->x86_capability);
1589 /* Report CX8 */
1590 set_bit(X86_FEATURE_CX8, &c->x86_capability);
1591 /* Set 3DNow! on Winchip 2 and above. */
1592 if (c->x86_model >=8)
1593 set_bit(X86_FEATURE_3DNOW, &c->x86_capability);
1594 /* See if we can find out some more. */
1595 if ( cpuid_eax(0x80000000) >= 0x80000005 ) {
1596 /* Yes, we can. */
1597 cpuid(0x80000005,&aa,&bb,&cc,&dd);
1598 /* Add L1 data and code cache sizes. */
1599 c->x86_cache_size = (cc>>24)+(dd>>24);
1600 }
1601 sprintf( c->x86_model_id, "WinChip %s", name );
1602 mcheck_init(c);
1603 break;
1604
1605 case 6:
1606 switch (c->x86_model) {
1607 case 6 ... 7: /* Cyrix III or C3 */
1608 rdmsr (MSR_VIA_FCR, lo, hi);
1609 lo |= (1<<1 | 1<<7); /* Report CX8 & enable PGE */
1610 wrmsr (MSR_VIA_FCR, lo, hi);
1611
1612 set_bit(X86_FEATURE_CX8, &c->x86_capability);
1613 set_bit(X86_FEATURE_3DNOW, &c->x86_capability);
1614
1615 get_model_name(c);
1616 display_cacheinfo(c);
1617 break;
1618 }
1619 break;
1620 }
1621 }
1622
1623
1624 static void __init init_transmeta(struct cpuinfo_x86 *c)
1625 {
1626 unsigned int cap_mask, uk, max, dummy;
1627 unsigned int cms_rev1, cms_rev2;
1628 unsigned int cpu_rev, cpu_freq, cpu_flags;
1629 char cpu_info[65];
1630
1631 get_model_name(c); /* Same as AMD/Cyrix */
1632 display_cacheinfo(c);
1633
1634 /* Print CMS and CPU revision */
1635 max = cpuid_eax(0x80860000);
1636 if ( max >= 0x80860001 ) {
1637 cpuid(0x80860001, &dummy, &cpu_rev, &cpu_freq, &cpu_flags);
1638 printk(KERN_INFO "CPU: Processor revision %u.%u.%u.%u, %u MHz\n",
1639 (cpu_rev >> 24) & 0xff,
1640 (cpu_rev >> 16) & 0xff,
1641 (cpu_rev >> 8) & 0xff,
1642 cpu_rev & 0xff,
1643 cpu_freq);
1644 }
1645 if ( max >= 0x80860002 ) {
1646 cpuid(0x80860002, &dummy, &cms_rev1, &cms_rev2, &dummy);
1647 printk(KERN_INFO "CPU: Code Morphing Software revision %u.%u.%u-%u-%u\n",
1648 (cms_rev1 >> 24) & 0xff,
1649 (cms_rev1 >> 16) & 0xff,
1650 (cms_rev1 >> 8) & 0xff,
1651 cms_rev1 & 0xff,
1652 cms_rev2);
1653 }
1654 if ( max >= 0x80860006 ) {
1655 cpuid(0x80860003,
1656 (void *)&cpu_info[0],
1657 (void *)&cpu_info[4],
1658 (void *)&cpu_info[8],
1659 (void *)&cpu_info[12]);
1660 cpuid(0x80860004,
1661 (void *)&cpu_info[16],
1662 (void *)&cpu_info[20],
1663 (void *)&cpu_info[24],
1664 (void *)&cpu_info[28]);
1665 cpuid(0x80860005,
1666 (void *)&cpu_info[32],
1667 (void *)&cpu_info[36],
1668 (void *)&cpu_info[40],
1669 (void *)&cpu_info[44]);
1670 cpuid(0x80860006,
1671 (void *)&cpu_info[48],
1672 (void *)&cpu_info[52],
1673 (void *)&cpu_info[56],
1674 (void *)&cpu_info[60]);
1675 cpu_info[64] = '\0';
1676 printk(KERN_INFO "CPU: %s\n", cpu_info);
1677 }
1678
1679 /* Unhide possibly hidden capability flags */
1680 rdmsr(0x80860004, cap_mask, uk);
1681 wrmsr(0x80860004, ~0, uk);
1682 c->x86_capability[0] = cpuid_edx(0x00000001);
1683 wrmsr(0x80860004, cap_mask, uk);
1684 }
1685
1686
1687 static void __init init_rise(struct cpuinfo_x86 *c)
1688 {
1689 printk("CPU: Rise iDragon");
1690 if (c->x86_model > 2)
1691 printk(" II");
1692 printk("\n");
1693
1694 /* Unhide possibly hidden capability flags
1695 The mp6 iDragon family don't have MSRs.
1696 We switch on extra features with this cpuid weirdness: */
1697 __asm__ (
1698 "movl $0x6363452a, %%eax\n\t"
1699 "movl $0x3231206c, %%ecx\n\t"
1700 "movl $0x2a32313a, %%edx\n\t"
1701 "cpuid\n\t"
1702 "movl $0x63634523, %%eax\n\t"
1703 "movl $0x32315f6c, %%ecx\n\t"
1704 "movl $0x2333313a, %%edx\n\t"
1705 "cpuid\n\t" : : : "eax", "ebx", "ecx", "edx"
1706 );
1707 set_bit(X86_FEATURE_CX8, &c->x86_capability);
1708 }
1709
1710
1711 extern void trap_init_f00f_bug(void);
1712
1713 static void __init init_intel(struct cpuinfo_x86 *c)
1714 {
1715 #ifndef CONFIG_M686
1716 static int f00f_workaround_enabled = 0;
1717 #endif
1718 char *p = NULL;
1719 unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
1720
1721 #ifndef CONFIG_M686
1722 /*
1723 * All current models of Pentium and Pentium with MMX technology CPUs
1724 * have the F0 0F bug, which lets nonpriviledged users lock up the system.
1725 * Note that the workaround only should be initialized once...
1726 */
1727 c->f00f_bug = 0;
1728 if ( c->x86 == 5 ) {
1729 c->f00f_bug = 1;
1730 if ( !f00f_workaround_enabled ) {
1731 trap_init_f00f_bug();
1732 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
1733 f00f_workaround_enabled = 1;
1734 }
1735 }
1736 #endif
1737
1738
1739 if (c->cpuid_level > 1) {
1740 /* supports eax=2 call */
1741 int i, j, n;
1742 int regs[4];
1743 unsigned char *dp = (unsigned char *)regs;
1744
1745 /* Number of times to iterate */
1746 n = cpuid_eax(2) & 0xFF;
1747
1748 for ( i = 0 ; i < n ; i++ ) {
1749 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
1750
1751 /* If bit 31 is set, this is an unknown format */
1752 for ( j = 0 ; j < 3 ; j++ ) {
1753 if ( regs[j] < 0 ) regs[j] = 0;
1754 }
1755
1756 /* Byte 0 is level count, not a descriptor */
1757 for ( j = 1 ; j < 16 ; j++ ) {
1758 unsigned char des = dp[j];
1759 unsigned char dl, dh;
1760 unsigned int cs;
1761
1762 dh = des >> 4;
1763 dl = des & 0x0F;
1764
1765 /* Black magic... */
1766
1767 switch ( dh )
1768 {
1769 case 0:
1770 switch ( dl ) {
1771 case 6:
1772 /* L1 I cache */
1773 l1i += 8;
1774 break;
1775 case 8:
1776 /* L1 I cache */
1777 l1i += 16;
1778 break;
1779 case 10:
1780 /* L1 D cache */
1781 l1d += 8;
1782 break;
1783 case 12:
1784 /* L1 D cache */
1785 l1d += 16;
1786 break;
1787 default:;
1788 /* TLB, or unknown */
1789 }
1790 break;
1791 case 2:
1792 if ( dl ) {
1793 /* L3 cache */
1794 cs = (dl-1) << 9;
1795 l3 += cs;
1796 }
1797 break;
1798 case 4:
1799 if ( c->x86 > 6 && dl ) {
1800 /* P4 family */
1801 /* L3 cache */
1802 cs = 128 << (dl-1);
1803 l3 += cs;
1804 break;
1805 }
1806 /* else same as 8 - fall through */
1807 case 8:
1808 if ( dl ) {
1809 /* L2 cache */
1810 cs = 128 << (dl-1);
1811 l2 += cs;
1812 }
1813 break;
1814 case 6:
1815 if (dl > 5) {
1816 /* L1 D cache */
1817 cs = 8<<(dl-6);
1818 l1d += cs;
1819 }
1820 break;
1821 case 7:
1822 if ( dl >= 8 )
1823 {
1824 /* L2 cache */
1825 cs = 64<<(dl-8);
1826 l2 += cs;
1827 } else {
1828 /* L0 I cache, count as L1 */
1829 cs = dl ? (16 << (dl-1)) : 12;
1830 l1i += cs;
1831 }
1832 break;
1833 default:
1834 /* TLB, or something else we don't know about */
1835 break;
1836 }
1837 }
1838 }
1839 if ( l1i || l1d )
1840 printk(KERN_INFO "CPU: L1 I cache: %dK, L1 D cache: %dK\n",
1841 l1i, l1d);
1842 if ( l2 )
1843 printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
1844 if ( l3 )
1845 printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
1846
1847 /*
1848 * This assumes the L3 cache is shared; it typically lives in
1849 * the northbridge. The L1 caches are included by the L2
1850 * cache, and so should not be included for the purpose of
1851 * SMP switching weights.
1852 */
1853 c->x86_cache_size = l2 ? l2 : (l1i+l1d);
1854 }
1855
1856 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it */
1857 if ( c->x86 == 6 && c->x86_model < 3 && c->x86_mask < 3 )
1858 clear_bit(X86_FEATURE_SEP, &c->x86_capability);
1859
1860 /* Names for the Pentium II/Celeron processors
1861 detectable only by also checking the cache size.
1862 Dixon is NOT a Celeron. */
1863 if (c->x86 == 6) {
1864 switch (c->x86_model) {
1865 case 5:
1866 if (l2 == 0)
1867 p = "Celeron (Covington)";
1868 if (l2 == 256)
1869 p = "Mobile Pentium II (Dixon)";
1870 break;
1871
1872 case 6:
1873 if (l2 == 128)
1874 p = "Celeron (Mendocino)";
1875 break;
1876
1877 case 8:
1878 if (l2 == 128)
1879 p = "Celeron (Coppermine)";
1880 break;
1881 }
1882 }
1883
1884 if ( p )
1885 strcpy(c->x86_model_id, p);
1886
1887 /* Enable MCA if available */
1888 mcheck_init(c);
1889 }
1890
1891 void __init get_cpu_vendor(struct cpuinfo_x86 *c)
1892 {
1893 char *v = c->x86_vendor_id;
1894
1895 if (!strcmp(v, "GenuineIntel"))
1896 c->x86_vendor = X86_VENDOR_INTEL;
1897 else if (!strcmp(v, "AuthenticAMD"))
1898 c->x86_vendor = X86_VENDOR_AMD;
1899 else if (!strcmp(v, "CyrixInstead"))
1900 c->x86_vendor = X86_VENDOR_CYRIX;
1901 else if (!strcmp(v, "UMC UMC UMC "))
1902 c->x86_vendor = X86_VENDOR_UMC;
1903 else if (!strcmp(v, "CentaurHauls"))
1904 c->x86_vendor = X86_VENDOR_CENTAUR;
1905 else if (!strcmp(v, "NexGenDriven"))
1906 c->x86_vendor = X86_VENDOR_NEXGEN;
1907 else if (!strcmp(v, "RiseRiseRise"))
1908 c->x86_vendor = X86_VENDOR_RISE;
1909 else if (!strcmp(v, "GenuineTMx86") ||
1910 !strcmp(v, "TransmetaCPU"))
1911 c->x86_vendor = X86_VENDOR_TRANSMETA;
1912 else
1913 c->x86_vendor = X86_VENDOR_UNKNOWN;
1914 }
1915
1916 struct cpu_model_info {
1917 int vendor;
1918 int family;
1919 char *model_names[16];
1920 };
1921
1922 /* Naming convention should be: <Name> [(<Codename>)] */
1923 /* This table only is used unless init_<vendor>() below doesn't set it; */
1924 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
1925 static struct cpu_model_info cpu_models[] __initdata = {
1926 { X86_VENDOR_INTEL, 4,
1927 { "486 DX-25/33", "486 DX-50", "486 SX", "486 DX/2", "486 SL",
1928 "486 SX/2", NULL, "486 DX/2-WB", "486 DX/4", "486 DX/4-WB", NULL,
1929 NULL, NULL, NULL, NULL, NULL }},
1930 { X86_VENDOR_INTEL, 5,
1931 { "Pentium 60/66 A-step", "Pentium 60/66", "Pentium 75 - 200",
1932 "OverDrive PODP5V83", "Pentium MMX", NULL, NULL,
1933 "Mobile Pentium 75 - 200", "Mobile Pentium MMX", NULL, NULL, NULL,
1934 NULL, NULL, NULL, NULL }},
1935 { X86_VENDOR_INTEL, 6,
1936 { "Pentium Pro A-step", "Pentium Pro", NULL, "Pentium II (Klamath)",
1937 NULL, "Pentium II (Deschutes)", "Mobile Pentium II",
1938 "Pentium III (Katmai)", "Pentium III (Coppermine)", NULL,
1939 "Pentium III (Cascades)", NULL, NULL, NULL, NULL }},
1940 { X86_VENDOR_AMD, 4,
1941 { NULL, NULL, NULL, "486 DX/2", NULL, NULL, NULL, "486 DX/2-WB",
1942 "486 DX/4", "486 DX/4-WB", NULL, NULL, NULL, NULL, "Am5x86-WT",
1943 "Am5x86-WB" }},
1944 { X86_VENDOR_AMD, 5, /* Is this this really necessary?? */
1945 { "K5/SSA5", "K5",
1946 "K5", "K5", NULL, NULL,
1947 "K6", "K6", "K6-2",
1948 "K6-3", NULL, NULL, NULL, NULL, NULL, NULL }},
1949 { X86_VENDOR_AMD, 6, /* Is this this really necessary?? */
1950 { "Athlon", "Athlon",
1951 "Athlon", NULL, "Athlon", NULL,
1952 NULL, NULL, NULL,
1953 NULL, NULL, NULL, NULL, NULL, NULL, NULL }},
1954 { X86_VENDOR_UMC, 4,
1955 { NULL, "U5D", "U5S", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1956 NULL, NULL, NULL, NULL, NULL, NULL }},
1957 { X86_VENDOR_NEXGEN, 5,
1958 { "Nx586", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1959 NULL, NULL, NULL, NULL, NULL, NULL, NULL }},
1960 { X86_VENDOR_RISE, 5,
1961 { "iDragon", NULL, "iDragon", NULL, NULL, NULL, NULL,
1962 NULL, "iDragon II", "iDragon II", NULL, NULL, NULL, NULL, NULL, NULL }},
1963 };
1964
1965 /* Look up CPU names by table lookup. */
1966 static char __init *table_lookup_model(struct cpuinfo_x86 *c)
1967 {
1968 struct cpu_model_info *info = cpu_models;
1969 int i;
1970
1971 if ( c->x86_model >= 16 )
1972 return NULL; /* Range check */
1973
1974 for ( i = 0 ; i < sizeof(cpu_models)/sizeof(struct cpu_model_info) ; i++ ) {
1975 if ( info->vendor == c->x86_vendor &&
1976 info->family == c->x86 ) {
1977 return info->model_names[c->x86_model];
1978 }
1979 info++;
1980 }
1981 return NULL; /* Not found */
1982 }
1983
1984 /*
1985 * Detect a NexGen CPU running without BIOS hypercode new enough
1986 * to have CPUID. (Thanks to Herbert Oppmann)
1987 */
1988
1989 static int __init deep_magic_nexgen_probe(void)
1990 {
1991 int ret;
1992
1993 __asm__ __volatile__ (
1994 " movw $0x5555, %%ax\n"
1995 " xorw %%dx,%%dx\n"
1996 " movw $2, %%cx\n"
1997 " divw %%cx\n"
1998 " movl $0, %%eax\n"
1999 " jnz 1f\n"
2000 " movl $1, %%eax\n"
2001 "1:\n"
2002 : "=a" (ret) : : "cx", "dx" );
2003 return ret;
2004 }
2005
2006 static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
2007 {
2008 if( test_bit(X86_FEATURE_PN, &c->x86_capability) &&
2009 disable_x86_serial_nr ) {
2010 /* Disable processor serial number */
2011 unsigned long lo,hi;
2012 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
2013 lo |= 0x200000;
2014 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
2015 printk(KERN_NOTICE "CPU serial number disabled.\n");
2016 clear_bit(X86_FEATURE_PN, &c->x86_capability);
2017
2018 /* Disabling the serial number may affect the cpuid level */
2019 c->cpuid_level = cpuid_eax(0);
2020 }
2021 }
2022
2023
2024 int __init x86_serial_nr_setup(char *s)
2025 {
2026 disable_x86_serial_nr = 0;
2027 return 1;
2028 }
2029 __setup("serialnumber", x86_serial_nr_setup);
2030
2031 int __init x86_fxsr_setup(char * s)
2032 {
2033 disable_x86_fxsr = 1;
2034 return 1;
2035 }
2036 __setup("nofxsr", x86_fxsr_setup);
2037
2038
2039 /* Standard macro to see if a specific flag is changeable */
2040 static inline int flag_is_changeable_p(u32 flag)
2041 {
2042 u32 f1, f2;
2043
2044 asm("pushfl\n\t"
2045 "pushfl\n\t"
2046 "popl %0\n\t"
2047 "movl %0,%1\n\t"
2048 "xorl %2,%0\n\t"
2049 "pushl %0\n\t"
2050 "popfl\n\t"
2051 "pushfl\n\t"
2052 "popl %0\n\t"
2053 "popfl\n\t"
2054 : "=&r" (f1), "=&r" (f2)
2055 : "ir" (flag));
2056
2057 return ((f1^f2) & flag) != 0;
2058 }
2059
2060
2061 /* Probe for the CPUID instruction */
2062 static int __init have_cpuid_p(void)
2063 {
2064 return flag_is_changeable_p(X86_EFLAGS_ID);
2065 }
2066
2067 /*
2068 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
2069 * by the fact that they preserve the flags across the division of 5/2.
2070 * PII and PPro exhibit this behavior too, but they have cpuid available.
2071 */
2072
2073 /*
2074 * Perform the Cyrix 5/2 test. A Cyrix won't change
2075 * the flags, while other 486 chips will.
2076 */
2077 static inline int test_cyrix_52div(void)
2078 {
2079 unsigned int test;
2080
2081 __asm__ __volatile__(
2082 "sahf\n\t" /* clear flags (%eax = 0x0005) */
2083 "div %b2\n\t" /* divide 5 by 2 */
2084 "lahf" /* store flags into %ah */
2085 : "=a" (test)
2086 : "0" (5), "q" (2)
2087 : "cc");
2088
2089 /* AH is 0x02 on Cyrix after the divide.. */
2090 return (unsigned char) (test >> 8) == 0x02;
2091 }
2092
2093 /* Try to detect a CPU with disabled CPUID, and if so, enable. This routine
2094 may also be used to detect non-CPUID processors and fill in some of
2095 the information manually. */
2096 static int __init id_and_try_enable_cpuid(struct cpuinfo_x86 *c)
2097 {
2098 /* First of all, decide if this is a 486 or higher */
2099 /* It's a 486 if we can modify the AC flag */
2100 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
2101 c->x86 = 4;
2102 else
2103 c->x86 = 3;
2104
2105 /* Detect Cyrix with disabled CPUID */
2106 if ( c->x86 == 4 && test_cyrix_52div() ) {
2107 unsigned char dir0, dir1;
2108
2109 strcpy(c->x86_vendor_id, "CyrixInstead");
2110 c->x86_vendor = X86_VENDOR_CYRIX;
2111
2112 /* Actually enable cpuid on the older cyrix */
2113
2114 /* Retrieve CPU revisions */
2115
2116 do_cyrix_devid(&dir0, &dir1);
2117
2118 dir0>>=4;
2119
2120 /* Check it is an affected model */
2121
2122 if (dir0 == 5 || dir0 == 3)
2123 {
2124 unsigned char ccr3, ccr4;
2125 unsigned long flags;
2126
2127 printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
2128 local_irq_save(flags);
2129 ccr3 = getCx86(CX86_CCR3);
2130 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
2131 ccr4 = getCx86(CX86_CCR4);
2132 setCx86(CX86_CCR4, ccr4 | 0x80); /* enable cpuid */
2133 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
2134 local_irq_restore(flags);
2135 }
2136 } else
2137
2138 /* Detect NexGen with old hypercode */
2139 if ( deep_magic_nexgen_probe() ) {
2140 strcpy(c->x86_vendor_id, "NexGenDriven");
2141 }
2142
2143 return have_cpuid_p(); /* Check to see if CPUID now enabled? */
2144 }
2145
2146 /*
2147 * This does the hard work of actually picking apart the CPU stuff...
2148 */
2149 void __init identify_cpu(struct cpuinfo_x86 *c)
2150 {
2151 int junk, i;
2152 u32 xlvl, tfms;
2153
2154 c->loops_per_jiffy = loops_per_jiffy;
2155 c->x86_cache_size = -1;
2156 c->x86_vendor = X86_VENDOR_UNKNOWN;
2157 c->cpuid_level = -1; /* CPUID not detected */
2158 c->x86_model = c->x86_mask = 0; /* So far unknown... */
2159 c->x86_vendor_id[0] = '\0'; /* Unset */
2160 c->x86_model_id[0] = '\0'; /* Unset */
2161 memset(&c->x86_capability, 0, sizeof c->x86_capability);
2162
2163 if ( !have_cpuid_p() && !id_and_try_enable_cpuid(c) ) {
2164 /* CPU doesn't have CPUID */
2165
2166 /* If there are any capabilities, they're vendor-specific */
2167 /* enable_cpuid() would have set c->x86 for us. */
2168 } else {
2169 /* CPU does have CPUID */
2170
2171 /* Get vendor name */
2172 cpuid(0x00000000, &c->cpuid_level,
2173 (int *)&c->x86_vendor_id[0],
2174 (int *)&c->x86_vendor_id[8],
2175 (int *)&c->x86_vendor_id[4]);
2176
2177 get_cpu_vendor(c);
2178 /* Initialize the standard set of capabilities */
2179 /* Note that the vendor-specific code below might override */
2180
2181 /* Intel-defined flags: level 0x00000001 */
2182 if ( c->cpuid_level >= 0x00000001 ) {
2183 cpuid(0x00000001, &tfms, &junk, &junk,
2184 &c->x86_capability[0]);
2185 c->x86 = (tfms >> 8) & 15;
2186 c->x86_model = (tfms >> 4) & 15;
2187 c->x86_mask = tfms & 15;
2188 } else {
2189 /* Have CPUID level 0 only - unheard of */
2190 c->x86 = 4;
2191 }
2192
2193 /* AMD-defined flags: level 0x80000001 */
2194 xlvl = cpuid_eax(0x80000000);
2195 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
2196 if ( xlvl >= 0x80000001 )
2197 c->x86_capability[1] = cpuid_edx(0x80000001);
2198 if ( xlvl >= 0x80000004 )
2199 get_model_name(c); /* Default name */
2200 }
2201
2202 /* Transmeta-defined flags: level 0x80860001 */
2203 xlvl = cpuid_eax(0x80860000);
2204 if ( (xlvl & 0xffff0000) == 0x80860000 ) {
2205 if ( xlvl >= 0x80860001 )
2206 c->x86_capability[2] = cpuid_edx(0x80860001);
2207 }
2208 }
2209
2210 printk(KERN_DEBUG "CPU: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
2211 c->x86_capability[0],
2212 c->x86_capability[1],
2213 c->x86_capability[2],
2214 c->x86_vendor);
2215
2216 /*
2217 * Vendor-specific initialization. In this section we
2218 * canonicalize the feature flags, meaning if there are
2219 * features a certain CPU supports which CPUID doesn't
2220 * tell us, CPUID claiming incorrect flags, or other bugs,
2221 * we handle them here.
2222 *
2223 * At the end of this section, c->x86_capability better
2224 * indicate the features this CPU genuinely supports!
2225 */
2226 switch ( c->x86_vendor ) {
2227 case X86_VENDOR_UNKNOWN:
2228 default:
2229 /* Not much we can do here... */
2230 /* Check if at least it has cpuid */
2231 if (c->cpuid_level == -1)
2232 {
2233 /* No cpuid. It must be an ancient CPU */
2234 if (c->x86 == 4)
2235 strcpy(c->x86_model_id, "486");
2236 else if (c->x86 == 3)
2237 strcpy(c->x86_model_id, "386");
2238 }
2239 break;
2240
2241 case X86_VENDOR_CYRIX:
2242 init_cyrix(c);
2243 break;
2244
2245 case X86_VENDOR_AMD:
2246 init_amd(c);
2247 break;
2248
2249 case X86_VENDOR_CENTAUR:
2250 init_centaur(c);
2251 break;
2252
2253 case X86_VENDOR_INTEL:
2254 init_intel(c);
2255 break;
2256
2257 case X86_VENDOR_NEXGEN:
2258 c->x86_cache_size = 256; /* A few had 1 MB... */
2259 break;
2260
2261 case X86_VENDOR_TRANSMETA:
2262 init_transmeta(c);
2263 break;
2264
2265 case X86_VENDOR_RISE:
2266 init_rise(c);
2267 break;
2268 }
2269
2270 printk(KERN_DEBUG "CPU: After vendor init, caps: %08x %08x %08x %08x\n",
2271 c->x86_capability[0],
2272 c->x86_capability[1],
2273 c->x86_capability[2],
2274 c->x86_capability[3]);
2275
2276 /*
2277 * The vendor-specific functions might have changed features. Now
2278 * we do "generic changes."
2279 */
2280
2281 /* TSC disabled? */
2282 #ifndef CONFIG_X86_TSC
2283 if ( tsc_disable )
2284 clear_bit(X86_FEATURE_TSC, &c->x86_capability);
2285 #endif
2286
2287 /* FXSR disabled? */
2288 if (disable_x86_fxsr) {
2289 clear_bit(X86_FEATURE_FXSR, &c->x86_capability);
2290 clear_bit(X86_FEATURE_XMM, &c->x86_capability);
2291 }
2292
2293 /* Disable the PN if appropriate */
2294 squash_the_stupid_serial_number(c);
2295
2296 /* If the model name is still unset, do table lookup. */
2297 if ( !c->x86_model_id[0] ) {
2298 char *p;
2299 p = table_lookup_model(c);
2300 if ( p )
2301 strcpy(c->x86_model_id, p);
2302 else
2303 /* Last resort... */
2304 sprintf(c->x86_model_id, "%02x/%02x",
2305 c->x86_vendor, c->x86_model);
2306 }
2307
2308 /* Now the feature flags better reflect actual CPU features! */
2309
2310 printk(KERN_DEBUG "CPU: After generic, caps: %08x %08x %08x %08x\n",
2311 c->x86_capability[0],
2312 c->x86_capability[1],
2313 c->x86_capability[2],
2314 c->x86_capability[3]);
2315
2316 /*
2317 * On SMP, boot_cpu_data holds the common feature set between
2318 * all CPUs; so make sure that we indicate which features are
2319 * common between the CPUs. The first time this routine gets
2320 * executed, c == &boot_cpu_data.
2321 */
2322 if ( c != &boot_cpu_data ) {
2323 /* AND the already accumulated flags with these */
2324 for ( i = 0 ; i < NCAPINTS ; i++ )
2325 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
2326 }
2327
2328 printk(KERN_DEBUG "CPU: Common caps: %08x %08x %08x %08x\n",
2329 boot_cpu_data.x86_capability[0],
2330 boot_cpu_data.x86_capability[1],
2331 boot_cpu_data.x86_capability[2],
2332 boot_cpu_data.x86_capability[3]);
2333 }
2334 /*
2335 * Perform early boot up checks for a valid TSC. See arch/i386/kernel/time.c
2336 */
2337
2338 void __init dodgy_tsc(void)
2339 {
2340 get_cpu_vendor(&boot_cpu_data);
2341
2342 if ( boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX )
2343 init_cyrix(&boot_cpu_data);
2344 }
2345
2346
2347 /* These need to match <asm/processor.h> */
2348 static char *cpu_vendor_names[] __initdata = {
2349 "Intel", "Cyrix", "AMD", "UMC", "NexGen", "Centaur", "Rise", "Transmeta" };
2350
2351
2352 void __init print_cpu_info(struct cpuinfo_x86 *c)
2353 {
2354 char *vendor = NULL;
2355
2356 if (c->x86_vendor < sizeof(cpu_vendor_names)/sizeof(char *))
2357 vendor = cpu_vendor_names[c->x86_vendor];
2358 else if (c->cpuid_level >= 0)
2359 vendor = c->x86_vendor_id;
2360
2361 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
2362 printk("%s ", vendor);
2363
2364 if (!c->x86_model_id[0])
2365 printk("%d86", c->x86);
2366 else
2367 printk("%s", c->x86_model_id);
2368
2369 if (c->x86_mask || c->cpuid_level >= 0)
2370 printk(" stepping %02x\n", c->x86_mask);
2371 else
2372 printk("\n");
2373 }
2374
2375 /*
2376 * Get CPU information for use by the procfs.
2377 */
2378
2379 int get_cpuinfo(char * buffer)
2380 {
2381 char *p = buffer;
2382
2383 /*
2384 * These flag bits must match the definitions in <asm/cpufeature.h>.
2385 * NULL means this bit is undefined or reserved; either way it doesn't
2386 * have meaning as far as Linux is concerned. Note that it's important
2387 * to realize there is a difference between this table and CPUID -- if
2388 * applications want to get the raw CPUID data, they should access
2389 * /dev/cpu/<cpu_nr>/cpuid instead.
2390 */
2391 static char *x86_cap_flags[] = {
2392 /* Intel-defined */
2393 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
2394 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
2395 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
2396 "fxsr", "sse", "sse2", "ss", NULL, "tm", "ia64", NULL,
2397
2398 /* AMD-defined */
2399 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2400 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
2401 NULL, NULL, NULL, NULL, NULL, NULL, "mmxext", NULL,
2402 NULL, NULL, NULL, NULL, NULL, "lm", "3dnowext", "3dnow",
2403
2404 /* Transmeta-defined */
2405 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
2406 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2407 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2408 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2409
2410 /* Other (Linux-defined) */
2411 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", NULL, NULL, NULL, NULL,
2412 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2413 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2414 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2415 };
2416 struct cpuinfo_x86 *c = cpu_data;
2417 int i, n;
2418
2419 for (n = 0; n < NR_CPUS; n++, c++) {
2420 int fpu_exception;
2421 #ifdef CONFIG_SMP
2422 if (!(cpu_online_map & (1<<n)))
2423 continue;
2424 #endif
2425 p += sprintf(p,"processor\t: %d\n"
2426 "vendor_id\t: %s\n"
2427 "cpu family\t: %d\n"
2428 "model\t\t: %d\n"
2429 "model name\t: %s\n",
2430 n,
2431 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
2432 c->x86,
2433 c->x86_model,
2434 c->x86_model_id[0] ? c->x86_model_id : "unknown");
2435
2436 if (c->x86_mask || c->cpuid_level >= 0)
2437 p += sprintf(p, "stepping\t: %d\n", c->x86_mask);
2438 else
2439 p += sprintf(p, "stepping\t: unknown\n");
2440
2441 if ( test_bit(X86_FEATURE_TSC, &c->x86_capability) ) {
2442 p += sprintf(p, "cpu MHz\t\t: %lu.%03lu\n",
2443 cpu_khz / 1000, (cpu_khz % 1000));
2444 }
2445
2446 /* Cache size */
2447 if (c->x86_cache_size >= 0)
2448 p += sprintf(p, "cache size\t: %d KB\n", c->x86_cache_size);
2449
2450 /* We use exception 16 if we have hardware math and we've either seen it or the CPU claims it is internal */
2451 fpu_exception = c->hard_math && (ignore_irq13 || cpu_has_fpu);
2452 p += sprintf(p, "fdiv_bug\t: %s\n"
2453 "hlt_bug\t\t: %s\n"
2454 "f00f_bug\t: %s\n"
2455 "coma_bug\t: %s\n"
2456 "fpu\t\t: %s\n"
2457 "fpu_exception\t: %s\n"
2458 "cpuid level\t: %d\n"
2459 "wp\t\t: %s\n"
2460 "flags\t\t:",
2461 c->fdiv_bug ? "yes" : "no",
2462 c->hlt_works_ok ? "no" : "yes",
2463 c->f00f_bug ? "yes" : "no",
2464 c->coma_bug ? "yes" : "no",
2465 c->hard_math ? "yes" : "no",
2466 fpu_exception ? "yes" : "no",
2467 c->cpuid_level,
2468 c->wp_works_ok ? "yes" : "no");
2469
2470 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
2471 if ( test_bit(i, &c->x86_capability) &&
2472 x86_cap_flags[i] != NULL )
2473 p += sprintf(p, " %s", x86_cap_flags[i]);
2474
2475 p += sprintf(p, "\nbogomips\t: %lu.%02lu\n\n",
2476 c->loops_per_jiffy/(500000/HZ),
2477 (c->loops_per_jiffy/(5000/HZ)) % 100);
2478 }
2479 return p - buffer;
2480 }
2481
2482 static unsigned long cpu_initialized __initdata = 0;
2483
2484 /*
2485 * cpu_init() initializes state that is per-CPU. Some data is already
2486 * initialized (naturally) in the bootstrap process, such as the GDT
2487 * and IDT. We reload them nevertheless, this function acts as a
2488 * 'CPU state barrier', nothing should get across.
2489 */
2490 void __init cpu_init (void)
2491 {
2492 int nr = smp_processor_id();
2493 struct tss_struct * t = &init_tss[nr];
2494
2495 if (test_and_set_bit(nr, &cpu_initialized)) {
2496 printk(KERN_WARNING "CPU#%d already initialized!\n", nr);
2497 for (;;) __sti();
2498 }
2499 printk(KERN_INFO "Initializing CPU#%d\n", nr);
2500
2501 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
2502 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2503 #ifndef CONFIG_X86_TSC
2504 if (tsc_disable && cpu_has_tsc) {
2505 printk(KERN_NOTICE "Disabling TSC...\n");
2506 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
2507 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
2508 set_in_cr4(X86_CR4_TSD);
2509 }
2510 #endif
2511
2512 __asm__ __volatile__("lgdt %0": "=m" (gdt_descr));
2513 __asm__ __volatile__("lidt %0": "=m" (idt_descr));
2514
2515 /*
2516 * Delete NT
2517 */
2518 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
2519
2520 /*
2521 * set up and load the per-CPU TSS and LDT
2522 */
2523 atomic_inc(&init_mm.mm_count);
2524 current->active_mm = &init_mm;
2525 if(current->mm)
2526 BUG();
2527 enter_lazy_tlb(&init_mm, current, nr);
2528
2529 t->esp0 = current->thread.esp0;
2530 set_tss_desc(nr,t);
2531 gdt_table[__TSS(nr)].b &= 0xfffffdff;
2532 load_TR(nr);
2533 load_LDT(&init_mm);
2534
2535 /*
2536 * Clear all 6 debug registers:
2537 */
2538
2539 #define CD(register) __asm__("movl %0,%%db" #register ::"r"(0) );
2540
2541 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
2542
2543 #undef CD
2544
2545 /*
2546 * Force FPU initialization:
2547 */
2548 current->flags &= ~PF_USEDFPU;
2549 current->used_math = 0;
2550 stts();
2551 }
2552
2553 /*
2554 * Local Variables:
2555 * mode:c
2556 * c-file-style:"k&r"
2557 * c-basic-offset:8
2558 * End:
2559 */
2560