File: /usr/src/linux/drivers/sgi/char/sgiserial.h
1 /* sgiserial.h: Definitions for the SGI Zilog85C30 serial driver.
2 *
3 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
4 */
5 #ifndef _SGI_SERIAL_H
6 #define _SGI_SERIAL_H
7
8 /* Just one channel */
9 struct sgi_zschannel {
10 #ifdef __MIPSEB__
11 volatile unsigned char unused0[3];
12 volatile unsigned char control;
13 volatile unsigned char unused1[3];
14 volatile unsigned char data;
15 #else /* __MIPSEL__ */
16 volatile unsigned char control;
17 volatile unsigned char unused0[3];
18 volatile unsigned char data;
19 volatile unsigned char unused1[3];
20 #endif
21 };
22
23 /* The address space layout for each zs chip. Yes they are
24 * backwards.
25 */
26 struct sgi_zslayout {
27 struct sgi_zschannel channelB;
28 struct sgi_zschannel channelA;
29 };
30
31 #define NUM_ZSREGS 16
32
33 struct serial_struct {
34 int type;
35 int line;
36 int port;
37 int irq;
38 int flags;
39 int xmit_fifo_size;
40 int custom_divisor;
41 int baud_base;
42 unsigned short close_delay;
43 char reserved_char[2];
44 int hub6;
45 unsigned short closing_wait; /* time to wait before closing */
46 unsigned short closing_wait2; /* no longer used... */
47 int reserved[4];
48 };
49
50 /*
51 * For the close wait times, 0 means wait forever for serial port to
52 * flush its output. 65535 means don't wait at all.
53 */
54 #define ZILOG_CLOSING_WAIT_INF 0
55 #define ZILOG_CLOSING_WAIT_NONE 65535
56
57 /*
58 * Definitions for ZILOG_struct (and serial_struct) flags field
59 */
60 #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
61 on the callout port */
62 #define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
63 #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */
64 #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
65
66 #define ZILOG_SPD_MASK 0x0030
67 #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
68
69 #define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
70 #define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */
71
72 #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
73 #define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
74 #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
75 #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
76 #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
77
78 #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */
79 #define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged
80 * users can set or reset */
81
82 /* Internal flags used only by kernel/chr_drv/serial.c */
83 #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
84 #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
85 #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
86 #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
87 #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
88 #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
89 #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
90
91 /* Software state per channel */
92
93 #ifdef __KERNEL__
94 /*
95 * This is our internal structure for each serial port's state.
96 *
97 * Many fields are paralleled by the structure used by the serial_struct
98 * structure.
99 *
100 * For definitions of the flags field, see tty.h
101 */
102
103 struct sgi_serial {
104 struct sgi_serial *zs_next; /* For IRQ servicing chain */
105 struct sgi_zschannel *zs_channel; /* Channel registers */
106 unsigned char read_reg_zero;
107
108 char soft_carrier; /* Use soft carrier on this channel */
109 char cons_keyb; /* Channel runs the keyboard */
110 char cons_mouse; /* Channel runs the mouse */
111 char break_abort; /* Is serial console in, so process brk/abrt */
112 char kgdb_channel; /* Kgdb is running on this channel */
113 char is_cons; /* Is this our console. */
114
115 /* We need to know the current clock divisor
116 * to read the bps rate the chip has currently
117 * loaded.
118 */
119 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */
120 int zs_baud;
121
122 /* Current write register values */
123 unsigned char curregs[NUM_ZSREGS];
124
125 /* Values we need to set next opportunity */
126 unsigned char pendregs[NUM_ZSREGS];
127
128 char change_needed;
129
130 int magic;
131 int baud_base;
132 int port;
133 int irq;
134 int flags; /* defined in tty.h */
135 int type; /* UART type */
136 struct tty_struct *tty;
137 int read_status_mask;
138 int ignore_status_mask;
139 int timeout;
140 int xmit_fifo_size;
141 int custom_divisor;
142 int x_char; /* xon/xoff character */
143 int close_delay;
144 unsigned short closing_wait;
145 unsigned short closing_wait2;
146 unsigned long event;
147 unsigned long last_active;
148 int line;
149 int count; /* # of fd on device */
150 int blocked_open; /* # of blocked opens */
151 long session; /* Session of opening process */
152 long pgrp; /* pgrp of opening process */
153 unsigned char *xmit_buf;
154 int xmit_head;
155 int xmit_tail;
156 int xmit_cnt;
157 struct tq_struct tqueue;
158 struct tq_struct tqueue_hangup;
159 struct termios normal_termios;
160 struct termios callout_termios;
161 wait_queue_head_t open_wait;
162 wait_queue_head_t close_wait;
163 };
164
165
166 #define SERIAL_MAGIC 0x5301
167
168 /*
169 * The size of the serial xmit buffer is 1 page, or 4096 bytes
170 */
171 #define SERIAL_XMIT_SIZE 4096
172
173 /*
174 * Events are used to schedule things to happen at timer-interrupt
175 * time, instead of at rs interrupt time.
176 */
177 #define RS_EVENT_WRITE_WAKEUP 0
178
179 #endif /* __KERNEL__ */
180
181 /* Conversion routines to/from brg time constants from/to bits
182 * per second.
183 */
184 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
185 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
186
187 /* The Zilog register set */
188
189 #define FLAG 0x7e
190
191 /* Write Register 0 */
192 #define R0 0 /* Register selects */
193 #define R1 1
194 #define R2 2
195 #define R3 3
196 #define R4 4
197 #define R5 5
198 #define R6 6
199 #define R7 7
200 #define R8 8
201 #define R9 9
202 #define R10 10
203 #define R11 11
204 #define R12 12
205 #define R13 13
206 #define R14 14
207 #define R15 15
208
209 #define NULLCODE 0 /* Null Code */
210 #define POINT_HIGH 0x8 /* Select upper half of registers */
211 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
212 #define SEND_ABORT 0x18 /* HDLC Abort */
213 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
214 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
215 #define ERR_RES 0x30 /* Error Reset */
216 #define RES_H_IUS 0x38 /* Reset highest IUS */
217
218 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
219 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
220 #define RES_EOM_L 0xC0 /* Reset EOM latch */
221
222 /* Write Register 1 */
223
224 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
225 #define TxINT_ENAB 0x2 /* Tx Int Enable */
226 #define PAR_SPEC 0x4 /* Parity is special condition */
227
228 #define RxINT_DISAB 0 /* Rx Int Disable */
229 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
230 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
231 #define INT_ERR_Rx 0x18 /* Int on error only */
232
233 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
234 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
235 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
236
237 /* Write Register #2 (Interrupt Vector) */
238
239 /* Write Register 3 */
240
241 #define RxENABLE 0x1 /* Rx Enable */
242 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
243 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
244 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
245 #define ENT_HM 0x10 /* Enter Hunt Mode */
246 #define AUTO_ENAB 0x20 /* Auto Enables */
247 #define Rx5 0x0 /* Rx 5 Bits/Character */
248 #define Rx7 0x40 /* Rx 7 Bits/Character */
249 #define Rx6 0x80 /* Rx 6 Bits/Character */
250 #define Rx8 0xc0 /* Rx 8 Bits/Character */
251
252 /* Write Register 4 */
253
254 #define PAR_ENA 0x1 /* Parity Enable */
255 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
256
257 #define SYNC_ENAB 0 /* Sync Modes Enable */
258 #define SB1 0x4 /* 1 stop bit/char */
259 #define SB15 0x8 /* 1.5 stop bits/char */
260 #define SB2 0xc /* 2 stop bits/char */
261
262 #define MONSYNC 0 /* 8 Bit Sync character */
263 #define BISYNC 0x10 /* 16 bit sync character */
264 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
265 #define EXTSYNC 0x30 /* External Sync Mode */
266
267 #define X1CLK 0x0 /* x1 clock mode */
268 #define X16CLK 0x40 /* x16 clock mode */
269 #define X32CLK 0x80 /* x32 clock mode */
270 #define X64CLK 0xC0 /* x64 clock mode */
271
272 /* Write Register 5 */
273
274 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
275 #define RTS 0x2 /* RTS */
276 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
277 #define TxENAB 0x8 /* Tx Enable */
278 #define SND_BRK 0x10 /* Send Break */
279 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
280 #define Tx7 0x20 /* Tx 7 bits/character */
281 #define Tx6 0x40 /* Tx 6 bits/character */
282 #define Tx8 0x60 /* Tx 8 bits/character */
283 #define DTR 0x80 /* DTR */
284
285 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
286
287 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
288
289 /* Write Register 8 (transmit buffer) */
290
291 /* Write Register 9 (Master interrupt control) */
292 #define VIS 1 /* Vector Includes Status */
293 #define NV 2 /* No Vector */
294 #define DLC 4 /* Disable Lower Chain */
295 #define MIE 8 /* Master Interrupt Enable */
296 #define STATHI 0x10 /* Status high */
297 #define NORESET 0 /* No reset on write to R9 */
298 #define CHRB 0x40 /* Reset channel B */
299 #define CHRA 0x80 /* Reset channel A */
300 #define FHWRES 0xc0 /* Force hardware reset */
301
302 /* Write Register 10 (misc control bits) */
303 #define BIT6 1 /* 6 bit/8bit sync */
304 #define LOOPMODE 2 /* SDLC Loop mode */
305 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
306 #define MARKIDLE 8 /* Mark/flag on idle */
307 #define GAOP 0x10 /* Go active on poll */
308 #define NRZ 0 /* NRZ mode */
309 #define NRZI 0x20 /* NRZI mode */
310 #define FM1 0x40 /* FM1 (transition = 1) */
311 #define FM0 0x60 /* FM0 (transition = 0) */
312 #define CRCPS 0x80 /* CRC Preset I/O */
313
314 /* Write Register 11 (Clock Mode control) */
315 #define TRxCXT 0 /* TRxC = Xtal output */
316 #define TRxCTC 1 /* TRxC = Transmit clock */
317 #define TRxCBR 2 /* TRxC = BR Generator Output */
318 #define TRxCDP 3 /* TRxC = DPLL output */
319 #define TRxCOI 4 /* TRxC O/I */
320 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
321 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
322 #define TCBR 0x10 /* Transmit clock = BR Generator output */
323 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
324 #define RCRTxCP 0 /* Receive clock = RTxC pin */
325 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
326 #define RCBR 0x40 /* Receive clock = BR Generator output */
327 #define RCDPLL 0x60 /* Receive clock = DPLL output */
328 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
329
330 /* Write Register 12 (lower byte of baud rate generator time constant) */
331
332 /* Write Register 13 (upper byte of baud rate generator time constant) */
333
334 /* Write Register 14 (Misc control bits) */
335 #define BRENABL 1 /* Baud rate generator enable */
336 #define BRSRC 2 /* Baud rate generator source */
337 #define DTRREQ 4 /* DTR/Request function */
338 #define AUTOECHO 8 /* Auto Echo */
339 #define LOOPBAK 0x10 /* Local loopback */
340 #define SEARCH 0x20 /* Enter search mode */
341 #define RMC 0x40 /* Reset missing clock */
342 #define DISDPLL 0x60 /* Disable DPLL */
343 #define SSBR 0x80 /* Set DPLL source = BR generator */
344 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
345 #define SFMM 0xc0 /* Set FM mode */
346 #define SNRZI 0xe0 /* Set NRZI mode */
347
348 /* Write Register 15 (external/status interrupt control) */
349 #define ZCIE 2 /* Zero count IE */
350 #define DCDIE 8 /* DCD IE */
351 #define SYNCIE 0x10 /* Sync/hunt IE */
352 #define CTSIE 0x20 /* CTS IE */
353 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
354 #define BRKIE 0x80 /* Break/Abort IE */
355
356
357 /* Read Register 0 */
358 #define Rx_CH_AV 0x1 /* Rx Character Available */
359 #define ZCOUNT 0x2 /* Zero count */
360 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
361 #define DCD 0x8 /* DCD */
362 #define SYNC 0x10 /* Sync/hunt */
363 #define CTS 0x20 /* CTS */
364 #define TxEOM 0x40 /* Tx underrun */
365 #define BRK_ABRT 0x80 /* Break/Abort */
366
367 /* Read Register 1 */
368 #define ALL_SNT 0x1 /* All sent */
369 /* Residue Data for 8 Rx bits/char programmed */
370 #define RES3 0x8 /* 0/3 */
371 #define RES4 0x4 /* 0/4 */
372 #define RES5 0xc /* 0/5 */
373 #define RES6 0x2 /* 0/6 */
374 #define RES7 0xa /* 0/7 */
375 #define RES8 0x6 /* 0/8 */
376 #define RES18 0xe /* 1/8 */
377 #define RES28 0x0 /* 2/8 */
378 /* Special Rx Condition Interrupts */
379 #define PAR_ERR 0x10 /* Parity error */
380 #define Rx_OVR 0x20 /* Rx Overrun Error */
381 #define CRC_ERR 0x40 /* CRC/Framing Error */
382 #define END_FR 0x80 /* End of Frame (SDLC) */
383
384 /* Read Register 2 (channel b only) - Interrupt vector */
385
386 /* Read Register 3 (interrupt pending register) ch a only */
387 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
388 #define CHBTxIP 0x2 /* Channel B Tx IP */
389 #define CHBRxIP 0x4 /* Channel B Rx IP */
390 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
391 #define CHATxIP 0x10 /* Channel A Tx IP */
392 #define CHARxIP 0x20 /* Channel A Rx IP */
393
394 /* Read Register 8 (receive data register) */
395
396 /* Read Register 10 (misc status bits) */
397 #define ONLOOP 2 /* On loop */
398 #define LOOPSEND 0x10 /* Loop sending */
399 #define CLK2MIS 0x40 /* Two clocks missing */
400 #define CLK1MIS 0x80 /* One clock missing */
401
402 /* Read Register 12 (lower byte of baud rate generator constant) */
403
404 /* Read Register 13 (upper byte of baud rate generator constant) */
405
406 /* Read Register 15 (value of WR 15) */
407
408 /* Misc inlines */
409 extern inline void ZS_CLEARERR(struct sgi_zschannel *channel)
410 {
411 volatile unsigned char junk;
412
413 udelay(2);
414 channel->control = ERR_RES;
415 if (ioc_icontrol)
416 junk = ioc_icontrol->istat0;
417 }
418
419 extern inline void ZS_CLEARFIFO(struct sgi_zschannel *channel)
420 {
421 volatile unsigned char junk;
422
423 udelay(2);
424 junk = channel->data;
425 udelay(2);
426 if (ioc_icontrol)
427 junk = ioc_icontrol->istat0;
428 junk = channel->data;
429 udelay(2);
430 if (ioc_icontrol)
431 junk = ioc_icontrol->istat0;
432 junk = channel->data;
433 udelay(2);
434 if (ioc_icontrol)
435 junk = ioc_icontrol->istat0;
436 }
437
438 #if 0
439
440 #define ZS_CLEARERR(channel) (channel->control = ERR_RES)
441 #define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
442 garbage = channel->data; \
443 udelay(2); \
444 garbage = channel->data; \
445 udelay(2); \
446 garbage = channel->data; \
447 udelay(2); } while(0)
448
449 #endif
450
451 #endif /* !(_SPARC_SERIAL_H) */
452