File: /usr/src/linux/arch/i386/kernel/time.c
1 /*
2 * linux/arch/i386/kernel/time.c
3 *
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 *
6 * This file contains the PC-specific time handling details:
7 * reading the RTC at bootup, etc..
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1995-03-26 Markus Kuhn
11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12 * precision CMOS clock update
13 * 1996-05-03 Ingo Molnar
14 * fixed time warps in do_[slow|fast]_gettimeoffset()
15 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
16 * "A Kernel Model for Precision Timekeeping" by Dave Mills
17 * 1998-09-05 (Various)
18 * More robust do_fast_gettimeoffset() algorithm implemented
19 * (works with APM, Cyrix 6x86MX and Centaur C6),
20 * monotonic gettimeofday() with fast_get_timeoffset(),
21 * drift-proof precision TSC calibration on boot
22 * (C. Scott Ananian <cananian@alumni.princeton.edu>, Andrew D.
23 * Balsa <andrebalsa@altern.org>, Philip Gladstone <philip@raptor.com>;
24 * ported from 2.0.35 Jumbo-9 by Michael Krause <m.krause@tu-harburg.de>).
25 * 1998-12-16 Andrea Arcangeli
26 * Fixed Jumbo-9 code in 2.1.131: do_gettimeofday was missing 1 jiffy
27 * because was not accounting lost_ticks.
28 * 1998-12-24 Copyright (C) 1998 Andrea Arcangeli
29 * Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
30 * serialize accesses to xtime/lost_ticks).
31 */
32
33 #include <linux/errno.h>
34 #include <linux/sched.h>
35 #include <linux/kernel.h>
36 #include <linux/param.h>
37 #include <linux/string.h>
38 #include <linux/mm.h>
39 #include <linux/interrupt.h>
40 #include <linux/time.h>
41 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/smp.h>
44
45 #include <asm/io.h>
46 #include <asm/smp.h>
47 #include <asm/irq.h>
48 #include <asm/msr.h>
49 #include <asm/delay.h>
50 #include <asm/mpspec.h>
51 #include <asm/uaccess.h>
52 #include <asm/processor.h>
53
54 #include <linux/mc146818rtc.h>
55 #include <linux/timex.h>
56 #include <linux/config.h>
57
58 #include <asm/fixmap.h>
59 #include <asm/cobalt.h>
60
61 /*
62 * for x86_do_profile()
63 */
64 #include <linux/irq.h>
65
66
67 unsigned long cpu_khz; /* Detected as we calibrate the TSC */
68
69 /* Number of usecs that the last interrupt was delayed */
70 static int delay_at_last_interrupt;
71
72 static unsigned long last_tsc_low; /* lsb 32 bits of Time Stamp Counter */
73
74 /* Cached *multiplier* to convert TSC counts to microseconds.
75 * (see the equation below).
76 * Equal to 2^32 * (1 / (clocks per usec) ).
77 * Initialized in time_init.
78 */
79 unsigned long fast_gettimeoffset_quotient;
80
81 extern rwlock_t xtime_lock;
82 extern unsigned long wall_jiffies;
83
84 spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
85
86 static inline unsigned long do_fast_gettimeoffset(void)
87 {
88 register unsigned long eax, edx;
89
90 /* Read the Time Stamp Counter */
91
92 rdtsc(eax,edx);
93
94 /* .. relative to previous jiffy (32 bits is enough) */
95 eax -= last_tsc_low; /* tsc_low delta */
96
97 /*
98 * Time offset = (tsc_low delta) * fast_gettimeoffset_quotient
99 * = (tsc_low delta) * (usecs_per_clock)
100 * = (tsc_low delta) * (usecs_per_jiffy / clocks_per_jiffy)
101 *
102 * Using a mull instead of a divl saves up to 31 clock cycles
103 * in the critical path.
104 */
105
106 __asm__("mull %2"
107 :"=a" (eax), "=d" (edx)
108 :"rm" (fast_gettimeoffset_quotient),
109 "0" (eax));
110
111 /* our adjusted time offset in microseconds */
112 return delay_at_last_interrupt + edx;
113 }
114
115 #define TICK_SIZE tick
116
117 spinlock_t i8253_lock = SPIN_LOCK_UNLOCKED;
118
119 extern spinlock_t i8259A_lock;
120
121 #ifndef CONFIG_X86_TSC
122
123 /* This function must be called with interrupts disabled
124 * It was inspired by Steve McCanne's microtime-i386 for BSD. -- jrs
125 *
126 * However, the pc-audio speaker driver changes the divisor so that
127 * it gets interrupted rather more often - it loads 64 into the
128 * counter rather than 11932! This has an adverse impact on
129 * do_gettimeoffset() -- it stops working! What is also not
130 * good is that the interval that our timer function gets called
131 * is no longer 10.0002 ms, but 9.9767 ms. To get around this
132 * would require using a different timing source. Maybe someone
133 * could use the RTC - I know that this can interrupt at frequencies
134 * ranging from 8192Hz to 2Hz. If I had the energy, I'd somehow fix
135 * it so that at startup, the timer code in sched.c would select
136 * using either the RTC or the 8253 timer. The decision would be
137 * based on whether there was any other device around that needed
138 * to trample on the 8253. I'd set up the RTC to interrupt at 1024 Hz,
139 * and then do some jiggery to have a version of do_timer that
140 * advanced the clock by 1/1024 s. Every time that reached over 1/100
141 * of a second, then do all the old code. If the time was kept correct
142 * then do_gettimeoffset could just return 0 - there is no low order
143 * divider that can be accessed.
144 *
145 * Ideally, you would be able to use the RTC for the speaker driver,
146 * but it appears that the speaker driver really needs interrupt more
147 * often than every 120 us or so.
148 *
149 * Anyway, this needs more thought.... pjsg (1993-08-28)
150 *
151 * If you are really that interested, you should be reading
152 * comp.protocols.time.ntp!
153 */
154
155 static unsigned long do_slow_gettimeoffset(void)
156 {
157 int count;
158
159 static int count_p = LATCH; /* for the first call after boot */
160 static unsigned long jiffies_p = 0;
161
162 /*
163 * cache volatile jiffies temporarily; we have IRQs turned off.
164 */
165 unsigned long jiffies_t;
166
167 /* gets recalled with irq locally disabled */
168 spin_lock(&i8253_lock);
169 /* timer count may underflow right here */
170 outb_p(0x00, 0x43); /* latch the count ASAP */
171
172 count = inb_p(0x40); /* read the latched count */
173
174 /*
175 * We do this guaranteed double memory access instead of a _p
176 * postfix in the previous port access. Wheee, hackady hack
177 */
178 jiffies_t = jiffies;
179
180 count |= inb_p(0x40) << 8;
181
182 /* VIA686a test code... reset the latch if count > max + 1 */
183 if (count > LATCH) {
184 outb_p(0x34, 0x43);
185 outb_p(LATCH & 0xff, 0x40);
186 outb(LATCH >> 8, 0x40);
187 count = LATCH - 1;
188 }
189
190 spin_unlock(&i8253_lock);
191
192 /*
193 * avoiding timer inconsistencies (they are rare, but they happen)...
194 * there are two kinds of problems that must be avoided here:
195 * 1. the timer counter underflows
196 * 2. hardware problem with the timer, not giving us continuous time,
197 * the counter does small "jumps" upwards on some Pentium systems,
198 * (see c't 95/10 page 335 for Neptun bug.)
199 */
200
201 /* you can safely undefine this if you don't have the Neptune chipset */
202
203 #define BUGGY_NEPTUN_TIMER
204
205 if( jiffies_t == jiffies_p ) {
206 if( count > count_p ) {
207 /* the nutcase */
208
209 int i;
210
211 spin_lock(&i8259A_lock);
212 /*
213 * This is tricky when I/O APICs are used;
214 * see do_timer_interrupt().
215 */
216 i = inb(0x20);
217 spin_unlock(&i8259A_lock);
218
219 /* assumption about timer being IRQ0 */
220 if (i & 0x01) {
221 /*
222 * We cannot detect lost timer interrupts ...
223 * well, that's why we call them lost, don't we? :)
224 * [hmm, on the Pentium and Alpha we can ... sort of]
225 */
226 count -= LATCH;
227 } else {
228 #ifdef BUGGY_NEPTUN_TIMER
229 /*
230 * for the Neptun bug we know that the 'latch'
231 * command doesnt latch the high and low value
232 * of the counter atomically. Thus we have to
233 * substract 256 from the counter
234 * ... funny, isnt it? :)
235 */
236
237 count -= 256;
238 #else
239 printk("do_slow_gettimeoffset(): hardware timer problem?\n");
240 #endif
241 }
242 }
243 } else
244 jiffies_p = jiffies_t;
245
246 count_p = count;
247
248 count = ((LATCH-1) - count) * TICK_SIZE;
249 count = (count + LATCH/2) / LATCH;
250
251 return count;
252 }
253
254 static unsigned long (*do_gettimeoffset)(void) = do_slow_gettimeoffset;
255
256 #else
257
258 #define do_gettimeoffset() do_fast_gettimeoffset()
259
260 #endif
261
262 /*
263 * This version of gettimeofday has microsecond resolution
264 * and better than microsecond precision on fast x86 machines with TSC.
265 */
266 void do_gettimeofday(struct timeval *tv)
267 {
268 unsigned long flags;
269 unsigned long usec, sec;
270
271 read_lock_irqsave(&xtime_lock, flags);
272 usec = do_gettimeoffset();
273 {
274 unsigned long lost = jiffies - wall_jiffies;
275 if (lost)
276 usec += lost * (1000000 / HZ);
277 }
278 sec = xtime.tv_sec;
279 usec += xtime.tv_usec;
280 read_unlock_irqrestore(&xtime_lock, flags);
281
282 while (usec >= 1000000) {
283 usec -= 1000000;
284 sec++;
285 }
286
287 tv->tv_sec = sec;
288 tv->tv_usec = usec;
289 }
290
291 void do_settimeofday(struct timeval *tv)
292 {
293 write_lock_irq(&xtime_lock);
294 /*
295 * This is revolting. We need to set "xtime" correctly. However, the
296 * value in this location is the value at the most recent update of
297 * wall time. Discover what correction gettimeofday() would have
298 * made, and then undo it!
299 */
300 tv->tv_usec -= do_gettimeoffset();
301 tv->tv_usec -= (jiffies - wall_jiffies) * (1000000 / HZ);
302
303 while (tv->tv_usec < 0) {
304 tv->tv_usec += 1000000;
305 tv->tv_sec--;
306 }
307
308 xtime = *tv;
309 time_adjust = 0; /* stop active adjtime() */
310 time_status |= STA_UNSYNC;
311 time_maxerror = NTP_PHASE_LIMIT;
312 time_esterror = NTP_PHASE_LIMIT;
313 write_unlock_irq(&xtime_lock);
314 }
315
316 /*
317 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
318 * called 500 ms after the second nowtime has started, because when
319 * nowtime is written into the registers of the CMOS clock, it will
320 * jump to the next second precisely 500 ms later. Check the Motorola
321 * MC146818A or Dallas DS12887 data sheet for details.
322 *
323 * BUG: This routine does not handle hour overflow properly; it just
324 * sets the minutes. Usually you'll only notice that after reboot!
325 */
326 static int set_rtc_mmss(unsigned long nowtime)
327 {
328 int retval = 0;
329 int real_seconds, real_minutes, cmos_minutes;
330 unsigned char save_control, save_freq_select;
331
332 /* gets recalled with irq locally disabled */
333 spin_lock(&rtc_lock);
334 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
335 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
336
337 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
338 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
339
340 cmos_minutes = CMOS_READ(RTC_MINUTES);
341 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
342 BCD_TO_BIN(cmos_minutes);
343
344 /*
345 * since we're only adjusting minutes and seconds,
346 * don't interfere with hour overflow. This avoids
347 * messing with unknown time zones but requires your
348 * RTC not to be off by more than 15 minutes
349 */
350 real_seconds = nowtime % 60;
351 real_minutes = nowtime / 60;
352 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
353 real_minutes += 30; /* correct for half hour time zone */
354 real_minutes %= 60;
355
356 if (abs(real_minutes - cmos_minutes) < 30) {
357 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
358 BIN_TO_BCD(real_seconds);
359 BIN_TO_BCD(real_minutes);
360 }
361 CMOS_WRITE(real_seconds,RTC_SECONDS);
362 CMOS_WRITE(real_minutes,RTC_MINUTES);
363 } else {
364 printk(KERN_WARNING
365 "set_rtc_mmss: can't update from %d to %d\n",
366 cmos_minutes, real_minutes);
367 retval = -1;
368 }
369
370 /* The following flags have to be released exactly in this order,
371 * otherwise the DS12887 (popular MC146818A clone with integrated
372 * battery and quartz) will not reset the oscillator and will not
373 * update precisely 500 ms later. You won't find this mentioned in
374 * the Dallas Semiconductor data sheets, but who believes data
375 * sheets anyway ... -- Markus Kuhn
376 */
377 CMOS_WRITE(save_control, RTC_CONTROL);
378 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
379 spin_unlock(&rtc_lock);
380
381 return retval;
382 }
383
384 /* last time the cmos clock got updated */
385 static long last_rtc_update;
386
387 int timer_ack;
388
389 /*
390 * timer_interrupt() needs to keep up the real-time clock,
391 * as well as call the "do_timer()" routine every clocktick
392 */
393 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
394 {
395 #ifdef CONFIG_X86_IO_APIC
396 if (timer_ack) {
397 /*
398 * Subtle, when I/O APICs are used we have to ack timer IRQ
399 * manually to reset the IRR bit for do_slow_gettimeoffset().
400 * This will also deassert NMI lines for the watchdog if run
401 * on an 82489DX-based system.
402 */
403 spin_lock(&i8259A_lock);
404 outb(0x0c, 0x20);
405 /* Ack the IRQ; AEOI will end it automatically. */
406 inb(0x20);
407 spin_unlock(&i8259A_lock);
408 }
409 #endif
410
411 #ifdef CONFIG_VISWS
412 /* Clear the interrupt */
413 co_cpu_write(CO_CPU_STAT,co_cpu_read(CO_CPU_STAT) & ~CO_STAT_TIMEINTR);
414 #endif
415 do_timer(regs);
416 /*
417 * In the SMP case we use the local APIC timer interrupt to do the
418 * profiling, except when we simulate SMP mode on a uniprocessor
419 * system, in that case we have to call the local interrupt handler.
420 */
421 #ifndef CONFIG_X86_LOCAL_APIC
422 if (!user_mode(regs))
423 x86_do_profile(regs->eip);
424 #else
425 if (!using_apic_timer)
426 smp_local_timer_interrupt(regs);
427 #endif
428
429 /*
430 * If we have an externally synchronized Linux clock, then update
431 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
432 * called as close as possible to 500 ms before the new second starts.
433 */
434 if ((time_status & STA_UNSYNC) == 0 &&
435 xtime.tv_sec > last_rtc_update + 660 &&
436 xtime.tv_usec >= 500000 - ((unsigned) tick) / 2 &&
437 xtime.tv_usec <= 500000 + ((unsigned) tick) / 2) {
438 if (set_rtc_mmss(xtime.tv_sec) == 0)
439 last_rtc_update = xtime.tv_sec;
440 else
441 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
442 }
443
444 #ifdef CONFIG_MCA
445 if( MCA_bus ) {
446 /* The PS/2 uses level-triggered interrupts. You can't
447 turn them off, nor would you want to (any attempt to
448 enable edge-triggered interrupts usually gets intercepted by a
449 special hardware circuit). Hence we have to acknowledge
450 the timer interrupt. Through some incredibly stupid
451 design idea, the reset for IRQ 0 is done by setting the
452 high bit of the PPI port B (0x61). Note that some PS/2s,
453 notably the 55SX, work fine if this is removed. */
454
455 irq = inb_p( 0x61 ); /* read the current state */
456 outb_p( irq|0x80, 0x61 ); /* reset the IRQ */
457 }
458 #endif
459 }
460
461 static int use_tsc;
462
463 /*
464 * This is the same as the above, except we _also_ save the current
465 * Time Stamp Counter value at the time of the timer interrupt, so that
466 * we later on can estimate the time of day more exactly.
467 */
468 static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
469 {
470 int count;
471
472 /*
473 * Here we are in the timer irq handler. We just have irqs locally
474 * disabled but we don't know if the timer_bh is running on the other
475 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
476 * the irq version of write_lock because as just said we have irq
477 * locally disabled. -arca
478 */
479 write_lock(&xtime_lock);
480
481 if (use_tsc)
482 {
483 /*
484 * It is important that these two operations happen almost at
485 * the same time. We do the RDTSC stuff first, since it's
486 * faster. To avoid any inconsistencies, we need interrupts
487 * disabled locally.
488 */
489
490 /*
491 * Interrupts are just disabled locally since the timer irq
492 * has the SA_INTERRUPT flag set. -arca
493 */
494
495 /* read Pentium cycle counter */
496
497 rdtscl(last_tsc_low);
498
499 spin_lock(&i8253_lock);
500 outb_p(0x00, 0x43); /* latch the count ASAP */
501
502 count = inb_p(0x40); /* read the latched count */
503 count |= inb(0x40) << 8;
504 spin_unlock(&i8253_lock);
505
506 count = ((LATCH-1) - count) * TICK_SIZE;
507 delay_at_last_interrupt = (count + LATCH/2) / LATCH;
508 }
509
510 do_timer_interrupt(irq, NULL, regs);
511
512 write_unlock(&xtime_lock);
513
514 }
515
516 /* not static: needed by APM */
517 unsigned long get_cmos_time(void)
518 {
519 unsigned int year, mon, day, hour, min, sec;
520 int i;
521
522 /* The Linux interpretation of the CMOS clock register contents:
523 * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
524 * RTC registers show the second which has precisely just started.
525 * Let's hope other operating systems interpret the RTC the same way.
526 */
527 /* read RTC exactly on falling edge of update flag */
528 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
529 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
530 break;
531 for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */
532 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
533 break;
534 do { /* Isn't this overkill ? UIP above should guarantee consistency */
535 sec = CMOS_READ(RTC_SECONDS);
536 min = CMOS_READ(RTC_MINUTES);
537 hour = CMOS_READ(RTC_HOURS);
538 day = CMOS_READ(RTC_DAY_OF_MONTH);
539 mon = CMOS_READ(RTC_MONTH);
540 year = CMOS_READ(RTC_YEAR);
541 } while (sec != CMOS_READ(RTC_SECONDS));
542 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
543 {
544 BCD_TO_BIN(sec);
545 BCD_TO_BIN(min);
546 BCD_TO_BIN(hour);
547 BCD_TO_BIN(day);
548 BCD_TO_BIN(mon);
549 BCD_TO_BIN(year);
550 }
551 if ((year += 1900) < 1970)
552 year += 100;
553 return mktime(year, mon, day, hour, min, sec);
554 }
555
556 static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};
557
558 /* ------ Calibrate the TSC -------
559 * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
560 * Too much 64-bit arithmetic here to do this cleanly in C, and for
561 * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
562 * output busy loop as low as possible. We avoid reading the CTC registers
563 * directly because of the awkward 8-bit access mechanism of the 82C54
564 * device.
565 */
566
567 #define CALIBRATE_LATCH (5 * LATCH)
568 #define CALIBRATE_TIME (5 * 1000020/HZ)
569
570 static unsigned long __init calibrate_tsc(void)
571 {
572 /* Set the Gate high, disable speaker */
573 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
574
575 /*
576 * Now let's take care of CTC channel 2
577 *
578 * Set the Gate high, program CTC channel 2 for mode 0,
579 * (interrupt on terminal count mode), binary count,
580 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
581 */
582 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
583 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
584 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
585
586 {
587 unsigned long startlow, starthigh;
588 unsigned long endlow, endhigh;
589 unsigned long count;
590
591 rdtsc(startlow,starthigh);
592 count = 0;
593 do {
594 count++;
595 } while ((inb(0x61) & 0x20) == 0);
596 rdtsc(endlow,endhigh);
597
598 last_tsc_low = endlow;
599
600 /* Error: ECTCNEVERSET */
601 if (count <= 1)
602 goto bad_ctc;
603
604 /* 64-bit subtract - gcc just messes up with long longs */
605 __asm__("subl %2,%0\n\t"
606 "sbbl %3,%1"
607 :"=a" (endlow), "=d" (endhigh)
608 :"g" (startlow), "g" (starthigh),
609 "0" (endlow), "1" (endhigh));
610
611 /* Error: ECPUTOOFAST */
612 if (endhigh)
613 goto bad_ctc;
614
615 /* Error: ECPUTOOSLOW */
616 if (endlow <= CALIBRATE_TIME)
617 goto bad_ctc;
618
619 __asm__("divl %2"
620 :"=a" (endlow), "=d" (endhigh)
621 :"r" (endlow), "0" (0), "1" (CALIBRATE_TIME));
622
623 return endlow;
624 }
625
626 /*
627 * The CTC wasn't reliable: we got a hit on the very first read,
628 * or the CPU was so fast/slow that the quotient wouldn't fit in
629 * 32 bits..
630 */
631 bad_ctc:
632 return 0;
633 }
634
635 void __init time_init(void)
636 {
637 extern int x86_udelay_tsc;
638
639 xtime.tv_sec = get_cmos_time();
640 xtime.tv_usec = 0;
641
642 /*
643 * If we have APM enabled or the CPU clock speed is variable
644 * (CPU stops clock on HLT or slows clock to save power)
645 * then the TSC timestamps may diverge by up to 1 jiffy from
646 * 'real time' but nothing will break.
647 * The most frequent case is that the CPU is "woken" from a halt
648 * state by the timer interrupt itself, so we get 0 error. In the
649 * rare cases where a driver would "wake" the CPU and request a
650 * timestamp, the maximum error is < 1 jiffy. But timestamps are
651 * still perfectly ordered.
652 * Note that the TSC counter will be reset if APM suspends
653 * to disk; this won't break the kernel, though, 'cuz we're
654 * smart. See arch/i386/kernel/apm.c.
655 */
656 /*
657 * Firstly we have to do a CPU check for chips with
658 * a potentially buggy TSC. At this point we haven't run
659 * the ident/bugs checks so we must run this hook as it
660 * may turn off the TSC flag.
661 *
662 * NOTE: this doesnt yet handle SMP 486 machines where only
663 * some CPU's have a TSC. Thats never worked and nobody has
664 * moaned if you have the only one in the world - you fix it!
665 */
666
667 dodgy_tsc();
668
669 if (cpu_has_tsc) {
670 unsigned long tsc_quotient = calibrate_tsc();
671 if (tsc_quotient) {
672 fast_gettimeoffset_quotient = tsc_quotient;
673 use_tsc = 1;
674 /*
675 * We could be more selective here I suspect
676 * and just enable this for the next intel chips ?
677 */
678 x86_udelay_tsc = 1;
679 #ifndef do_gettimeoffset
680 do_gettimeoffset = do_fast_gettimeoffset;
681 #endif
682 do_get_fast_time = do_gettimeofday;
683
684 /* report CPU clock rate in Hz.
685 * The formula is (10^6 * 2^32) / (2^32 * 1 / (clocks/us)) =
686 * clock/second. Our precision is about 100 ppm.
687 */
688 { unsigned long eax=0, edx=1000;
689 __asm__("divl %2"
690 :"=a" (cpu_khz), "=d" (edx)
691 :"r" (tsc_quotient),
692 "0" (eax), "1" (edx));
693 printk("Detected %lu.%03lu MHz processor.\n", cpu_khz / 1000, cpu_khz % 1000);
694 }
695 }
696 }
697
698 #ifdef CONFIG_VISWS
699 printk("Starting Cobalt Timer system clock\n");
700
701 /* Set the countdown value */
702 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
703
704 /* Start the timer */
705 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
706
707 /* Enable (unmask) the timer interrupt */
708 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
709
710 /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */
711 setup_irq(CO_IRQ_TIMER, &irq0);
712 #else
713 setup_irq(0, &irq0);
714 #endif
715 }
716