File: /usr/src/linux/drivers/sound/cs4281/cs4281m.c
1 /*******************************************************************************
2 *
3 * "cs4281.c" -- Cirrus Logic-Crystal CS4281 linux audio driver.
4 *
5 * Copyright (C) 2000,2001 Cirrus Logic Corp.
6 * -- adapted from drivers by Thomas Sailer,
7 * -- but don't bug him; Problems should go to:
8 * -- tom woller (twoller@crystal.cirrus.com) or
9 * (audio@crystal.cirrus.com).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Module command line parameters:
26 * none
27 *
28 * Supported devices:
29 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
30 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
31 * /dev/midi simple MIDI UART interface, no ioctl
32 *
33 * Modification History
34 * 08/20/00 trw - silence and no stopping DAC until release
35 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
36 * 09/18/00 trw - added 16bit only record with conversion
37 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
38 * capture/playback rates)
39 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
40 * libOSSm.so)
41 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
42 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
43 * 11/10/00 bkz - added __devinit to cs4281_hw_init()
44 * 11/10/00 trw - fixed SMP and capture spinlock hang.
45 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
46 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
47 * 12/08/00 trw - added PM support.
48 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
49 * (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
50 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
51 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
52 * defaultorder-100 as power of 2 for the buffer size. example:
53 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
54 *
55 *******************************************************************************/
56
57 /* uncomment the following line to disable building PM support into the driver */
58 //#define NOT_CS4281_PM 1
59
60 #include <linux/list.h>
61 #include <linux/version.h>
62 #include <linux/module.h>
63 #include <linux/string.h>
64 #include <linux/ioport.h>
65 #include <linux/sched.h>
66 #include <linux/delay.h>
67 #include <linux/sound.h>
68 #include <linux/slab.h>
69 #include <linux/soundcard.h>
70 #include <linux/pci.h>
71 #include <linux/bitops.h>
72 #include <asm/io.h>
73 #include <asm/dma.h>
74 #include <linux/init.h>
75 #include <linux/poll.h>
76 #include <linux/smp_lock.h>
77 #include <linux/wrapper.h>
78 #include <asm/uaccess.h>
79 #include <asm/hardirq.h>
80 //#include "cs_dm.h"
81 #include "cs4281_hwdefs.h"
82 #include "cs4281pm.h"
83
84 struct cs4281_state;
85 EXPORT_NO_SYMBOLS;
86
87 static void stop_dac(struct cs4281_state *s);
88 static void stop_adc(struct cs4281_state *s);
89 static void start_dac(struct cs4281_state *s);
90 static void start_adc(struct cs4281_state *s);
91 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
92
93 // ---------------------------------------------------------------------
94
95 #ifndef PCI_VENDOR_ID_CIRRUS
96 #define PCI_VENDOR_ID_CIRRUS 0x1013
97 #endif
98 #ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
99 #define PCI_DEVICE_ID_CRYSTAL_CS4281 0x6005
100 #endif
101
102 #define CS4281_MAGIC ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
103 #define CS4281_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
104
105 // buffer order determines the size of the dma buffer for the driver.
106 // under Linux, a smaller buffer allows more responsiveness from many of the
107 // applications (e.g. games). A larger buffer allows some of the apps (esound)
108 // to not underrun the dma buffer as easily. As default, use 32k (order=3)
109 // rather than 64k as some of the games work more responsively.
110 // log base 2( buff sz = 32k).
111 static unsigned long defaultorder = 3;
112 MODULE_PARM(defaultorder, "i");
113
114 //
115 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
116 //
117 #define CSDEBUG 1
118 #if CSDEBUG
119 #define CSDEBUG_INTERFACE 1
120 #else
121 #undef CSDEBUG_INTERFACE
122 #endif
123 //
124 // cs_debugmask areas
125 //
126 #define CS_INIT 0x00000001 // initialization and probe functions
127 #define CS_ERROR 0x00000002 // tmp debugging bit placeholder
128 #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
129 #define CS_FUNCTION 0x00000008 // enter/leave functions
130 #define CS_WAVE_WRITE 0x00000010 // write information for wave
131 #define CS_WAVE_READ 0x00000020 // read information for wave
132 #define CS_MIDI_WRITE 0x00000040 // write information for midi
133 #define CS_MIDI_READ 0x00000080 // read information for midi
134 #define CS_MPU401_WRITE 0x00000100 // write information for mpu401
135 #define CS_MPU401_READ 0x00000200 // read information for mpu401
136 #define CS_OPEN 0x00000400 // all open functions in the driver
137 #define CS_RELEASE 0x00000800 // all release functions in the driver
138 #define CS_PARMS 0x00001000 // functional and operational parameters
139 #define CS_IOCTL 0x00002000 // ioctl (non-mixer)
140 #define CS_PM 0x00004000 // power management
141 #define CS_TMP 0x10000000 // tmp debug mask bit
142
143 #define CS_IOCTL_CMD_SUSPEND 0x1 // suspend
144 #define CS_IOCTL_CMD_RESUME 0x2 // resume
145 //
146 // CSDEBUG is usual mode is set to 1, then use the
147 // cs_debuglevel and cs_debugmask to turn on or off debugging.
148 // Debug level of 1 has been defined to be kernel errors and info
149 // that should be printed on any released driver.
150 //
151 #if CSDEBUG
152 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
153 #else
154 #define CS_DBGOUT(mask,level,x)
155 #endif
156
157 #if CSDEBUG
158 static unsigned long cs_debuglevel = 1; // levels range from 1-9
159 static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values
160 MODULE_PARM(cs_debuglevel, "i");
161 MODULE_PARM(cs_debugmask, "i");
162 #endif
163 #define CS_TRUE 1
164 #define CS_FALSE 0
165
166 // MIDI buffer sizes
167 #define MIDIINBUF 500
168 #define MIDIOUTBUF 500
169
170 #define FMODE_MIDI_SHIFT 3
171 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
172 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
173
174 #define CS4281_MAJOR_VERSION 1
175 #define CS4281_MINOR_VERSION 13
176 #ifdef __ia64__
177 #define CS4281_ARCH 64 //architecture key
178 #else
179 #define CS4281_ARCH 32 //architecture key
180 #endif
181
182 #define CS_TYPE_ADC 0
183 #define CS_TYPE_DAC 1
184
185
186 static const char invalid_magic[] =
187 KERN_CRIT "cs4281: invalid magic value\n";
188
189 #define VALIDATE_STATE(s) \
190 ({ \
191 if (!(s) || (s)->magic != CS4281_MAGIC) { \
192 printk(invalid_magic); \
193 return -ENXIO; \
194 } \
195 })
196
197 //LIST_HEAD(cs4281_devs);
198 struct list_head cs4281_devs = { &cs4281_devs, &cs4281_devs };
199
200 struct cs4281_state;
201
202 #include "cs4281_wrapper-24.c"
203
204 struct cs4281_state {
205 // magic
206 unsigned int magic;
207
208 // we keep the cards in a linked list
209 struct cs4281_state *next;
210
211 // pcidev is needed to turn off the DDMA controller at driver shutdown
212 struct pci_dev *pcidev;
213 struct list_head list;
214
215 // soundcore stuff
216 int dev_audio;
217 int dev_mixer;
218 int dev_midi;
219
220 // hardware resources
221 unsigned int pBA0phys, pBA1phys;
222 char *pBA0, *pBA1;
223 unsigned int irq;
224
225 // mixer registers
226 struct {
227 unsigned short vol[10];
228 unsigned int recsrc;
229 unsigned int modcnt;
230 unsigned short micpreamp;
231 } mix;
232
233 // wave stuff
234 struct properties {
235 unsigned fmt;
236 unsigned fmt_original; // original requested format
237 unsigned channels;
238 unsigned rate;
239 unsigned char clkdiv;
240 } prop_dac, prop_adc;
241 unsigned conversion:1; // conversion from 16 to 8 bit in progress
242 void *tmpbuff; // tmp buffer for sample conversions
243 unsigned ena;
244 spinlock_t lock;
245 struct semaphore open_sem;
246 struct semaphore open_sem_adc;
247 struct semaphore open_sem_dac;
248 mode_t open_mode;
249 wait_queue_head_t open_wait;
250 wait_queue_head_t open_wait_adc;
251 wait_queue_head_t open_wait_dac;
252
253 dma_addr_t dmaaddr_tmpbuff;
254 unsigned buforder_tmpbuff; // Log base 2 of 'rawbuf' size in bytes..
255 struct dmabuf {
256 void *rawbuf; // Physical address of
257 dma_addr_t dmaaddr;
258 unsigned buforder; // Log base 2 of 'rawbuf' size in bytes..
259 unsigned numfrag; // # of 'fragments' in the buffer.
260 unsigned fragshift; // Log base 2 of fragment size.
261 unsigned hwptr, swptr;
262 unsigned total_bytes; // # bytes process since open.
263 unsigned blocks; // last returned blocks value GETOPTR
264 unsigned wakeup; // interrupt occurred on block
265 int count;
266 unsigned underrun; // underrun flag
267 unsigned error; // over/underrun
268 wait_queue_head_t wait;
269 // redundant, but makes calculations easier
270 unsigned fragsize; // 2**fragshift..
271 unsigned dmasize; // 2**buforder.
272 unsigned fragsamples;
273 // OSS stuff
274 unsigned mapped:1; // Buffer mapped in cs4281_mmap()?
275 unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
276 unsigned endcleared:1;
277 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
278 unsigned ossfragshift;
279 int ossmaxfrags;
280 unsigned subdivision;
281 } dma_dac, dma_adc;
282
283 // midi stuff
284 struct {
285 unsigned ird, iwr, icnt;
286 unsigned ord, owr, ocnt;
287 wait_queue_head_t iwait;
288 wait_queue_head_t owait;
289 struct timer_list timer;
290 unsigned char ibuf[MIDIINBUF];
291 unsigned char obuf[MIDIOUTBUF];
292 } midi;
293
294 struct cs4281_pm pm;
295 struct cs4281_pipeline pl[CS4281_NUMBER_OF_PIPELINES];
296 };
297
298 #include "cs4281pm-24.c"
299
300 #if CSDEBUG
301
302 // DEBUG ROUTINES
303
304 #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
305 #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
306 #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
307 #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
308
309 #define SOUND_MIXER_CS_APM _SIOWR('M',124, int)
310
311
312 static void cs_printioctl(unsigned int x)
313 {
314 unsigned int i;
315 unsigned char vidx;
316 // Index of mixtable1[] member is Device ID
317 // and must be <= SOUND_MIXER_NRDEVICES.
318 // Value of array member is index into s->mix.vol[]
319 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
320 [SOUND_MIXER_PCM] = 1, // voice
321 [SOUND_MIXER_LINE1] = 2, // AUX
322 [SOUND_MIXER_CD] = 3, // CD
323 [SOUND_MIXER_LINE] = 4, // Line
324 [SOUND_MIXER_SYNTH] = 5, // FM
325 [SOUND_MIXER_MIC] = 6, // Mic
326 [SOUND_MIXER_SPEAKER] = 7, // Speaker
327 [SOUND_MIXER_RECLEV] = 8, // Recording level
328 [SOUND_MIXER_VOLUME] = 9 // Master Volume
329 };
330
331 switch (x) {
332 case SOUND_MIXER_CS_GETDBGMASK:
333 CS_DBGOUT(CS_IOCTL, 4,
334 printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
335 break;
336 case SOUND_MIXER_CS_GETDBGLEVEL:
337 CS_DBGOUT(CS_IOCTL, 4,
338 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
339 break;
340 case SOUND_MIXER_CS_SETDBGMASK:
341 CS_DBGOUT(CS_IOCTL, 4,
342 printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
343 break;
344 case SOUND_MIXER_CS_SETDBGLEVEL:
345 CS_DBGOUT(CS_IOCTL, 4,
346 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
347 break;
348 case OSS_GETVERSION:
349 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
350 break;
351 case SNDCTL_DSP_SYNC:
352 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
353 break;
354 case SNDCTL_DSP_SETDUPLEX:
355 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
356 break;
357 case SNDCTL_DSP_GETCAPS:
358 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
359 break;
360 case SNDCTL_DSP_RESET:
361 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
362 break;
363 case SNDCTL_DSP_SPEED:
364 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
365 break;
366 case SNDCTL_DSP_STEREO:
367 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
368 break;
369 case SNDCTL_DSP_CHANNELS:
370 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
371 break;
372 case SNDCTL_DSP_GETFMTS:
373 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
374 break;
375 case SNDCTL_DSP_SETFMT:
376 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
377 break;
378 case SNDCTL_DSP_POST:
379 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
380 break;
381 case SNDCTL_DSP_GETTRIGGER:
382 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
383 break;
384 case SNDCTL_DSP_SETTRIGGER:
385 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
386 break;
387 case SNDCTL_DSP_GETOSPACE:
388 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
389 break;
390 case SNDCTL_DSP_GETISPACE:
391 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
392 break;
393 case SNDCTL_DSP_NONBLOCK:
394 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
395 break;
396 case SNDCTL_DSP_GETODELAY:
397 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
398 break;
399 case SNDCTL_DSP_GETIPTR:
400 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
401 break;
402 case SNDCTL_DSP_GETOPTR:
403 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
404 break;
405 case SNDCTL_DSP_GETBLKSIZE:
406 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
407 break;
408 case SNDCTL_DSP_SETFRAGMENT:
409 CS_DBGOUT(CS_IOCTL, 4,
410 printk("SNDCTL_DSP_SETFRAGMENT:\n"));
411 break;
412 case SNDCTL_DSP_SUBDIVIDE:
413 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
414 break;
415 case SOUND_PCM_READ_RATE:
416 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
417 break;
418 case SOUND_PCM_READ_CHANNELS:
419 CS_DBGOUT(CS_IOCTL, 4,
420 printk("SOUND_PCM_READ_CHANNELS:\n"));
421 break;
422 case SOUND_PCM_READ_BITS:
423 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
424 break;
425 case SOUND_PCM_WRITE_FILTER:
426 CS_DBGOUT(CS_IOCTL, 4,
427 printk("SOUND_PCM_WRITE_FILTER:\n"));
428 break;
429 case SNDCTL_DSP_SETSYNCRO:
430 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
431 break;
432 case SOUND_PCM_READ_FILTER:
433 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
434 break;
435 case SOUND_MIXER_PRIVATE1:
436 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
437 break;
438 case SOUND_MIXER_PRIVATE2:
439 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
440 break;
441 case SOUND_MIXER_PRIVATE3:
442 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
443 break;
444 case SOUND_MIXER_PRIVATE4:
445 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
446 break;
447 case SOUND_MIXER_PRIVATE5:
448 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
449 break;
450 case SOUND_MIXER_INFO:
451 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
452 break;
453 case SOUND_OLD_MIXER_INFO:
454 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
455 break;
456
457 default:
458 switch (_IOC_NR(x)) {
459 case SOUND_MIXER_VOLUME:
460 CS_DBGOUT(CS_IOCTL, 4,
461 printk("SOUND_MIXER_VOLUME:\n"));
462 break;
463 case SOUND_MIXER_SPEAKER:
464 CS_DBGOUT(CS_IOCTL, 4,
465 printk("SOUND_MIXER_SPEAKER:\n"));
466 break;
467 case SOUND_MIXER_RECLEV:
468 CS_DBGOUT(CS_IOCTL, 4,
469 printk("SOUND_MIXER_RECLEV:\n"));
470 break;
471 case SOUND_MIXER_MIC:
472 CS_DBGOUT(CS_IOCTL, 4,
473 printk("SOUND_MIXER_MIC:\n"));
474 break;
475 case SOUND_MIXER_SYNTH:
476 CS_DBGOUT(CS_IOCTL, 4,
477 printk("SOUND_MIXER_SYNTH:\n"));
478 break;
479 case SOUND_MIXER_RECSRC:
480 CS_DBGOUT(CS_IOCTL, 4,
481 printk("SOUND_MIXER_RECSRC:\n"));
482 break;
483 case SOUND_MIXER_DEVMASK:
484 CS_DBGOUT(CS_IOCTL, 4,
485 printk("SOUND_MIXER_DEVMASK:\n"));
486 break;
487 case SOUND_MIXER_RECMASK:
488 CS_DBGOUT(CS_IOCTL, 4,
489 printk("SOUND_MIXER_RECMASK:\n"));
490 break;
491 case SOUND_MIXER_STEREODEVS:
492 CS_DBGOUT(CS_IOCTL, 4,
493 printk("SOUND_MIXER_STEREODEVS:\n"));
494 break;
495 case SOUND_MIXER_CAPS:
496 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
497 break;
498 default:
499 i = _IOC_NR(x);
500 if (i >= SOUND_MIXER_NRDEVICES
501 || !(vidx = mixtable1[i])) {
502 CS_DBGOUT(CS_IOCTL, 4, printk
503 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
504 x, i));
505 } else {
506 CS_DBGOUT(CS_IOCTL, 4, printk
507 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
508 x, i));
509 }
510 break;
511 }
512 }
513 }
514 #endif
515 static int prog_dmabuf_adc(struct cs4281_state *s);
516 static void prog_codec(struct cs4281_state *s, unsigned type);
517
518 // ---------------------------------------------------------------------
519 //
520 // Hardware Interfaces For the CS4281
521 //
522
523
524 //******************************************************************************
525 // "delayus()-- Delay for the specified # of microseconds.
526 //******************************************************************************
527 static void delayus(struct cs4281_state *s, u32 delay)
528 {
529 u32 j;
530 if ((delay > 9999) && (s->pm.flags & CS4281_PM_IDLE)) {
531 j = (delay * HZ) / 1000000; /* calculate delay in jiffies */
532 if (j < 1)
533 j = 1; /* minimum one jiffy. */
534 current->state = TASK_UNINTERRUPTIBLE;
535 schedule_timeout(j);
536 } else
537 udelay(delay);
538 return;
539 }
540
541
542 //******************************************************************************
543 // "cs4281_read_ac97" -- Reads a word from the specified location in the
544 // CS4281's address space(based on the BA0 register).
545 //
546 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
547 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
548 // 0h for reads.
549 // 3. Write ACCTL = Control Register = 460h for initiating the write
550 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
551 // 5. if DCV not cleared, break and return error
552 // 6. Read ACSTS = Status Register = 464h, check VSTS bit
553 //****************************************************************************
554 static int cs4281_read_ac97(struct cs4281_state *card, u32 offset,
555 u32 * value)
556 {
557 u32 count, status;
558
559 // Make sure that there is not data sitting
560 // around from a previous uncompleted access.
561 // ACSDA = Status Data Register = 47Ch
562 status = readl(card->pBA0 + BA0_ACSDA);
563
564 // Setup the AC97 control registers on the CS4281 to send the
565 // appropriate command to the AC97 to perform the read.
566 // ACCAD = Command Address Register = 46Ch
567 // ACCDA = Command Data Register = 470h
568 // ACCTL = Control Register = 460h
569 // bit DCV - will clear when process completed
570 // bit CRW - Read command
571 // bit VFRM - valid frame enabled
572 // bit ESYN - ASYNC generation enabled
573
574 // Get the actual AC97 register from the offset
575 writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
576 writel(0, card->pBA0 + BA0_ACCDA);
577 writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN,
578 card->pBA0 + BA0_ACCTL);
579
580 // Wait for the read to occur.
581 for (count = 0; count < 10; count++) {
582 // First, we want to wait for a short time.
583 udelay(25);
584
585 // Now, check to see if the read has completed.
586 // ACCTL = 460h, DCV should be reset by now and 460h = 17h
587 if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV))
588 break;
589 }
590
591 // Make sure the read completed.
592 if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)
593 return 1;
594
595 // Wait for the valid status bit to go active.
596 for (count = 0; count < 10; count++) {
597 // Read the AC97 status register.
598 // ACSTS = Status Register = 464h
599 status = readl(card->pBA0 + BA0_ACSTS);
600
601 // See if we have valid status.
602 // VSTS - Valid Status
603 if (status & ACSTS_VSTS)
604 break;
605 // Wait for a short while.
606 udelay(25);
607 }
608
609 // Make sure we got valid status.
610 if (!(status & ACSTS_VSTS))
611 return 1;
612
613 // Read the data returned from the AC97 register.
614 // ACSDA = Status Data Register = 474h
615 *value = readl(card->pBA0 + BA0_ACSDA);
616
617 // Success.
618 return (0);
619 }
620
621
622 //****************************************************************************
623 //
624 // "cs4281_write_ac97()"-- writes a word to the specified location in the
625 // CS461x's address space (based on the part's base address zero register).
626 //
627 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
628 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
629 // 3. Write ACCTL = Control Register = 460h for initiating the write
630 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
631 // 5. if DCV not cleared, break and return error
632 //
633 //****************************************************************************
634 static int cs4281_write_ac97(struct cs4281_state *card, u32 offset,
635 u32 value)
636 {
637 u32 count, status=0;
638
639 CS_DBGOUT(CS_FUNCTION, 2,
640 printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ \n"));
641
642 // Setup the AC97 control registers on the CS4281 to send the
643 // appropriate command to the AC97 to perform the read.
644 // ACCAD = Command Address Register = 46Ch
645 // ACCDA = Command Data Register = 470h
646 // ACCTL = Control Register = 460h
647 // set DCV - will clear when process completed
648 // reset CRW - Write command
649 // set VFRM - valid frame enabled
650 // set ESYN - ASYNC generation enabled
651 // set RSTN - ARST# inactive, AC97 codec not reset
652
653 // Get the actual AC97 register from the offset
654
655 writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
656 writel(value, card->pBA0 + BA0_ACCDA);
657 writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN,
658 card->pBA0 + BA0_ACCTL);
659
660 // Wait for the write to occur.
661 for (count = 0; count < 100; count++) {
662 // First, we want to wait for a short time.
663 udelay(25);
664 // Now, check to see if the write has completed.
665 // ACCTL = 460h, DCV should be reset by now and 460h = 07h
666 status = readl(card->pBA0 + BA0_ACCTL);
667 if (!(status & ACCTL_DCV))
668 break;
669 }
670
671 // Make sure the write completed.
672 if (status & ACCTL_DCV) {
673 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
674 "cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV active\n"));
675 return 1;
676 }
677 CS_DBGOUT(CS_FUNCTION, 2,
678 printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0\n"));
679 // Success.
680 return 0;
681 }
682
683
684 //******************************************************************************
685 // "Init4281()" -- Bring up the part.
686 //******************************************************************************
687 static __devinit int cs4281_hw_init(struct cs4281_state *card)
688 {
689 u32 ac97_slotid;
690 u32 temp1, temp2;
691
692 CS_DBGOUT(CS_FUNCTION, 2,
693 printk(KERN_INFO "cs4281: cs4281_hw_init()+ \n"));
694 #ifndef NOT_CS4281_PM
695 if(!card)
696 return 1;
697 #endif
698 temp2 = readl(card->pBA0 + BA0_CFLR);
699 CS_DBGOUT(CS_INIT | CS_ERROR | CS_PARMS, 4, printk(KERN_INFO
700 "cs4281: cs4281_hw_init() CFLR 0x%x\n", temp2));
701 if(temp2 != CS4281_CFLR_DEFAULT)
702 {
703 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
704 "cs4281: cs4281_hw_init() CFLR invalid - resetting from 0x%x to 0x%x\n",
705 temp2,CS4281_CFLR_DEFAULT));
706 writel(CS4281_CFLR_DEFAULT, card->pBA0 + BA0_CFLR);
707 temp2 = readl(card->pBA0 + BA0_CFLR);
708 if(temp2 != CS4281_CFLR_DEFAULT)
709 {
710 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
711 "cs4281: cs4281_hw_init() Invalid hardware - unable to configure CFLR\n"));
712 return 1;
713 }
714 }
715
716 //***************************************7
717 // Set up the Sound System Configuration
718 //***************************************
719
720 // Set the 'Configuration Write Protect' register
721 // to 4281h. Allows vendor-defined configuration
722 // space between 0e4h and 0ffh to be written.
723
724 writel(0x4281, card->pBA0 + BA0_CWPR); // (3e0h)
725
726 // (0), Blast the clock control register to zero so that the
727 // PLL starts out in a known state, and blast the master serial
728 // port control register to zero so that the serial ports also
729 // start out in a known state.
730
731 writel(0, card->pBA0 + BA0_CLKCR1); // (400h)
732 writel(0, card->pBA0 + BA0_SERMC); // (420h)
733
734
735 // (1), Make ESYN go to zero to turn off
736 // the Sync pulse on the AC97 link.
737
738 writel(0, card->pBA0 + BA0_ACCTL);
739 udelay(50);
740
741
742 // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
743 // the AC97 spec) and then drive it high. This is done for non
744 // AC97 modes since there might be logic external to the CS461x
745 // that uses the ARST# line for a reset.
746
747 writel(0, card->pBA0 + BA0_SPMC); // (3ech)
748 udelay(100);
749 writel(SPMC_RSTN, card->pBA0 + BA0_SPMC);
750 delayus(card,50000); // Wait 50 ms for ABITCLK to become stable.
751
752 // (3) Turn on the Sound System Clocks.
753 writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1); // (400h)
754 delayus(card,50000); // Wait for the PLL to stabilize.
755 // Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
756 writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1);
757
758 // (4) Power on everything for now..
759 writel(0x7E, card->pBA0 + BA0_SSPM); // (740h)
760
761 // (5) Wait for clock stabilization.
762 for (temp1 = 0; temp1 < 1000; temp1++) {
763 udelay(1000);
764 if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)
765 break;
766 }
767 if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) {
768 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
769 "cs4281: DLLRDY failed!\n"));
770 return -EIO;
771 }
772 // (6) Enable ASYNC generation.
773 writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
774
775 // Now wait 'for a short while' to allow the AC97
776 // part to start generating bit clock. (so we don't
777 // Try to start the PLL without an input clock.)
778 delayus(card,50000);
779
780 // Set the serial port timing configuration, so that the
781 // clock control circuit gets its clock from the right place.
782 writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
783
784 // (7) Wait for the codec ready signal from the AC97 codec.
785
786 for (temp1 = 0; temp1 < 1000; temp1++) {
787 // Delay a mil to let things settle out and
788 // to prevent retrying the read too quickly.
789 udelay(1000);
790 if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready, (464h)
791 break; // exit the 'for' loop.
792 }
793 if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY)) // If never came ready,
794 {
795 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
796 "cs4281: ACSTS never came ready!\n"));
797 return -EIO; // exit initialization.
798 }
799 // (8) Assert the 'valid frame' signal so we can
800 // begin sending commands to the AC97 codec.
801 writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
802
803 // (9), Wait until CODEC calibration is finished.
804 // Print an error message if it doesn't.
805 for (temp1 = 0; temp1 < 1000; temp1++) {
806 delayus(card,10000);
807 // Read the AC97 Powerdown Control/Status Register.
808 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
809 if ((temp2 & 0x0000000F) == 0x0000000F)
810 break;
811 }
812 if ((temp2 & 0x0000000F) != 0x0000000F) {
813 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
814 "cs4281: Codec failed to calibrate. Status = %.8x.\n",
815 temp2));
816 return -EIO;
817 }
818 // (10), Set the serial port timing configuration, so that the
819 // clock control circuit gets its clock from the right place.
820 writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
821
822
823 // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
824 // that the codec is pumping ADC data across the AC link.
825 for (temp1 = 0; temp1 < 1000; temp1++) {
826 // Delay a mil to let things settle out and
827 // to prevent retrying the read too quickly.
828 delayus(card,1000); //(test)
829
830 // Read the input slot valid register; See
831 // if input slots 3 and 4 are valid yet.
832 if (
833 (readl(card->pBA0 + BA0_ACISV) &
834 (ACISV_ISV3 | ACISV_ISV4)) ==
835 (ACISV_ISV3 | ACISV_ISV4)) break; // Exit the 'for' if slots are valid.
836 }
837 // If we never got valid data, exit initialization.
838 if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4))
839 != (ACISV_ISV3 | ACISV_ISV4)) {
840 CS_DBGOUT(CS_FUNCTION, 2,
841 printk(KERN_ERR
842 "cs4281: Never got valid data!\n"));
843 return -EIO; // If no valid data, exit initialization.
844 }
845 // (12), Start digital data transfer of audio data to the codec.
846 writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV); // (468h)
847
848
849 //**************************************
850 // Unmute the Master and Alternate
851 // (headphone) volumes. Set to max.
852 //**************************************
853 cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0);
854 cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0);
855
856 //******************************************
857 // Power on the DAC(AddDACUser()from main())
858 //******************************************
859 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
860 cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
861
862 // Wait until we sample a DAC ready state.
863 for (temp2 = 0; temp2 < 32; temp2++) {
864 // Let's wait a mil to let things settle.
865 delayus(card,1000);
866 // Read the current state of the power control reg.
867 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
868 // If the DAC ready state bit is set, stop waiting.
869 if (temp1 & 0x2)
870 break;
871 }
872
873 //******************************************
874 // Power on the ADC(AddADCUser()from main())
875 //******************************************
876 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
877 cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
878
879 // Wait until we sample ADC ready state.
880 for (temp2 = 0; temp2 < 32; temp2++) {
881 // Let's wait a mil to let things settle.
882 delayus(card,1000);
883 // Read the current state of the power control reg.
884 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
885 // If the ADC ready state bit is set, stop waiting.
886 if (temp1 & 0x1)
887 break;
888 }
889 // Set up 4281 Register contents that
890 // don't change for boot duration.
891
892 // For playback, we map AC97 slot 3 and 4(Left
893 // & Right PCM playback) to DMA Channel 0.
894 // Set the fifo to be 15 bytes at offset zero.
895
896 ac97_slotid = 0x01000f00; // FCR0.RS[4:0]=1(=>slot4, right PCM playback).
897 // FCR0.LS[4:0]=0(=>slot3, left PCM playback).
898 // FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
899 writel(ac97_slotid, card->pBA0 + BA0_FCR0); // (180h)
900 writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0); // Turn on FIFO Enable.
901
902 // For capture, we map AC97 slot 10 and 11(Left
903 // and Right PCM Record) to DMA Channel 1.
904 // Set the fifo to be 15 bytes at offset sixteen.
905 ac97_slotid = 0x0B0A0f10; // FCR1.RS[4:0]=11(=>slot11, right PCM record).
906 // FCR1.LS[4:0]=10(=>slot10, left PCM record).
907 // FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
908 writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1); // (184h)
909 writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1); // Turn on FIFO Enable.
910
911 // Map the Playback SRC to the same AC97 slots(3 & 4--
912 // --Playback left & right)as DMA channel 0.
913 // Map the record SRC to the same AC97 slots(10 & 11--
914 // -- Record left & right) as DMA channel 1.
915
916 ac97_slotid = 0x0b0a0100; // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
917 // SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
918 // SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
919 // SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
920 writel(ac97_slotid, card->pBA0 + BA0_SRCSA); // (75ch)
921
922 // Set 'Half Terminal Count Interrupt Enable' and 'Terminal
923 // Count Interrupt Enable' in DMA Control Registers 0 & 1.
924 // Set 'MSK' flag to 1 to keep the DMA engines paused.
925 temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK); // (00030001h)
926 writel(temp1, card->pBA0 + BA0_DCR0); // (154h
927 writel(temp1, card->pBA0 + BA0_DCR1); // (15ch)
928
929 // Set 'Auto-Initialize Control' to 'enabled'; For playback,
930 // set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
931 // for record, set Transfer Type Control to 'write transfer'.
932 // All other bits set to zero; Some will be changed @ transfer start.
933 temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); // (20000018h)
934 writel(temp1, card->pBA0 + BA0_DMR0); // (150h)
935 temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h)
936 writel(temp1, card->pBA0 + BA0_DMR1); // (158h)
937
938 // Enable DMA interrupts generally, and
939 // DMA0 & DMA1 interrupts specifically.
940 temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff;
941 writel(temp1, card->pBA0 + BA0_HIMR);
942
943 CS_DBGOUT(CS_FUNCTION, 2,
944 printk(KERN_INFO "cs4281: cs4281_hw_init()- 0\n"));
945 return 0;
946 }
947
948 #ifndef NOT_CS4281_PM
949 static void printpm(struct cs4281_state *s)
950 {
951 CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
952 CS_DBGOUT(CS_PM, 9, printk("flags:0x%x u32CLKCR1_SAVE: 0%x u32SSPMValue: 0x%x\n",
953 (unsigned)s->pm.flags,s->pm.u32CLKCR1_SAVE,s->pm.u32SSPMValue));
954 CS_DBGOUT(CS_PM, 9, printk("u32PPLVCvalue: 0x%x u32PPRVCvalue: 0x%x\n",
955 s->pm.u32PPLVCvalue,s->pm.u32PPRVCvalue));
956 CS_DBGOUT(CS_PM, 9, printk("u32FMLVCvalue: 0x%x u32FMRVCvalue: 0x%x\n",
957 s->pm.u32FMLVCvalue,s->pm.u32FMRVCvalue));
958 CS_DBGOUT(CS_PM, 9, printk("u32GPIORvalue: 0x%x u32JSCTLvalue: 0x%x\n",
959 s->pm.u32GPIORvalue,s->pm.u32JSCTLvalue));
960 CS_DBGOUT(CS_PM, 9, printk("u32SSCR: 0x%x u32SRCSA: 0x%x\n",
961 s->pm.u32SSCR,s->pm.u32SRCSA));
962 CS_DBGOUT(CS_PM, 9, printk("u32DacASR: 0x%x u32AdcASR: 0x%x\n",
963 s->pm.u32DacASR,s->pm.u32AdcASR));
964 CS_DBGOUT(CS_PM, 9, printk("u32DacSR: 0x%x u32AdcSR: 0x%x\n",
965 s->pm.u32DacSR,s->pm.u32AdcSR));
966 CS_DBGOUT(CS_PM, 9, printk("u32MIDCR_Save: 0x%x\n",
967 s->pm.u32MIDCR_Save));
968
969 }
970 static void printpipe(struct cs4281_pipeline *pl)
971 {
972
973 CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
974 CS_DBGOUT(CS_PM, 9, printk("flags:0x%x number: 0%x\n",
975 (unsigned)pl->flags,pl->number));
976 CS_DBGOUT(CS_PM, 9, printk("u32DBAnValue: 0%x u32DBCnValue: 0x%x\n",
977 pl->u32DBAnValue,pl->u32DBCnValue));
978 CS_DBGOUT(CS_PM, 9, printk("u32DMRnValue: 0x%x u32DCRnValue: 0x%x\n",
979 pl->u32DMRnValue,pl->u32DCRnValue));
980 CS_DBGOUT(CS_PM, 9, printk("u32DBAnAddress: 0x%x u32DBCnAddress: 0x%x\n",
981 pl->u32DBAnAddress,pl->u32DBCnAddress));
982 CS_DBGOUT(CS_PM, 9, printk("u32DCAnAddress: 0x%x u32DCCnAddress: 0x%x\n",
983 pl->u32DCCnAddress,pl->u32DCCnAddress));
984 CS_DBGOUT(CS_PM, 9, printk("u32DMRnAddress: 0x%x u32DCRnAddress: 0x%x\n",
985 pl->u32DMRnAddress,pl->u32DCRnAddress));
986 CS_DBGOUT(CS_PM, 9, printk("u32HDSRnAddress: 0x%x u32DBAn_Save: 0x%x\n",
987 pl->u32HDSRnAddress,pl->u32DBAn_Save));
988 CS_DBGOUT(CS_PM, 9, printk("u32DBCn_Save: 0x%x u32DMRn_Save: 0x%x\n",
989 pl->u32DBCn_Save,pl->u32DMRn_Save));
990 CS_DBGOUT(CS_PM, 9, printk("u32DCRn_Save: 0x%x u32DCCn_Save: 0x%x\n",
991 pl->u32DCRn_Save,pl->u32DCCn_Save));
992 CS_DBGOUT(CS_PM, 9, printk("u32DCAn_Save: 0x%x\n",
993 pl->u32DCAn_Save));
994 CS_DBGOUT(CS_PM, 9, printk("u32FCRn_Save: 0x%x u32FSICn_Save: 0x%x\n",
995 pl->u32FCRn_Save,pl->u32FSICn_Save));
996 CS_DBGOUT(CS_PM, 9, printk("u32FCRnValue: 0x%x u32FSICnValue: 0x%x\n",
997 pl->u32FCRnValue,pl->u32FSICnValue));
998 CS_DBGOUT(CS_PM, 9, printk("u32FCRnAddress: 0x%x u32FSICnAddress: 0x%x\n",
999 pl->u32FCRnAddress,pl->u32FSICnAddress));
1000 CS_DBGOUT(CS_PM, 9, printk("u32FPDRnValue: 0x%x u32FPDRnAddress: 0x%x\n",
1001 pl->u32FPDRnValue,pl->u32FPDRnAddress));
1002 }
1003 static void printpipelines(struct cs4281_state *s)
1004 {
1005 int i;
1006 for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
1007 {
1008 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1009 {
1010 printpipe(&s->pl[i]);
1011 }
1012 }
1013 }
1014 /****************************************************************************
1015 *
1016 * Suspend - save the ac97 regs, mute the outputs and power down the part.
1017 *
1018 ****************************************************************************/
1019 void cs4281_ac97_suspend(struct cs4281_state *s)
1020 {
1021 int Count,i;
1022
1023 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()+\n"));
1024 /*
1025 * change the state, save the current hwptr, then stop the dac/adc
1026 */
1027 s->pm.flags &= ~CS4281_PM_IDLE;
1028 s->pm.flags |= CS4281_PM_SUSPENDING;
1029 s->pm.u32hwptr_playback = readl(s->pBA0 + BA0_DCA0);
1030 s->pm.u32hwptr_capture = readl(s->pBA0 + BA0_DCA1);
1031 stop_dac(s);
1032 stop_adc(s);
1033
1034 for(Count = 0x2, i=0; (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1035 && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1036 Count += 2, i++)
1037 {
1038 cs4281_read_ac97(s, BA0_AC97_RESET + Count, &s->pm.ac97[i]);
1039 }
1040 /*
1041 * Save the ac97 volume registers as well as the current powerdown state.
1042 * Now, mute the all the outputs (master, headphone, and mono), as well
1043 * as the PCM volume, in preparation for powering down the entire part.
1044 */
1045 cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME, &s->pm.u32AC97_master_volume);
1046 cs4281_read_ac97(s, BA0_AC97_HEADPHONE_VOLUME, &s->pm.u32AC97_headphone_volume);
1047 cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, &s->pm.u32AC97_master_volume_mono);
1048 cs4281_read_ac97(s, BA0_AC97_PCM_OUT_VOLUME, &s->pm.u32AC97_pcm_out_volume);
1049
1050 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, 0x8000);
1051 cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, 0x8000);
1052 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, 0x8000);
1053 cs4281_write_ac97(s, BA0_AC97_PCM_OUT_VOLUME, 0x8000);
1054
1055 cs4281_read_ac97(s, BA0_AC97_POWERDOWN, &s->pm.u32AC97_powerdown);
1056 cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &s->pm.u32AC97_general_purpose);
1057
1058 /*
1059 * And power down everything on the AC97 codec.
1060 */
1061 cs4281_write_ac97(s, BA0_AC97_POWERDOWN, 0xff00);
1062 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()-\n"));
1063 }
1064
1065 /****************************************************************************
1066 *
1067 * Resume - power up the part and restore its registers..
1068 *
1069 ****************************************************************************/
1070 void cs4281_ac97_resume(struct cs4281_state *s)
1071 {
1072 int Count,i;
1073
1074 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()+\n"));
1075
1076 /* do not save the power state registers at this time
1077 //
1078 // If we saved away the power control registers, write them into the
1079 // shadows so those saved values get restored instead of the current
1080 // shadowed value.
1081 //
1082 if( bPowerStateSaved )
1083 {
1084 PokeShadow( 0x26, ulSaveReg0x26 );
1085 bPowerStateSaved = FALSE;
1086 }
1087 */
1088
1089 //
1090 // First, we restore the state of the general purpose register. This
1091 // contains the mic select (mic1 or mic2) and if we restore this after
1092 // we restore the mic volume/boost state and mic2 was selected at
1093 // suspend time, we will end up with a brief period of time where mic1
1094 // is selected with the volume/boost settings for mic2, causing
1095 // acoustic feedback. So we restore the general purpose register
1096 // first, thereby getting the correct mic selected before we restore
1097 // the mic volume/boost.
1098 //
1099 cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, s->pm.u32AC97_general_purpose);
1100
1101 //
1102 // Now, while the outputs are still muted, restore the state of power
1103 // on the AC97 part.
1104 //
1105 cs4281_write_ac97(s, BA0_AC97_POWERDOWN, s->pm.u32AC97_powerdown);
1106
1107 /*
1108 * Restore just the first set of registers, from register number
1109 * 0x02 to the register number that ulHighestRegToRestore specifies.
1110 */
1111 for( Count = 0x2, i=0;
1112 (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1113 && (i < CS4281_AC97_NUMBER_RESTORE_REGS);
1114 Count += 2, i++)
1115 {
1116 cs4281_write_ac97(s, BA0_AC97_RESET + Count, s->pm.ac97[i]);
1117 }
1118 CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()-\n"));
1119 }
1120
1121 /* do not save the power state registers at this time
1122 ****************************************************************************
1123 *
1124 * SavePowerState - Save the power registers away.
1125 *
1126 ****************************************************************************
1127 void
1128 HWAC97codec::SavePowerState(void)
1129 {
1130 ENTRY(TM_OBJECTCALLS, "HWAC97codec::SavePowerState()\r\n");
1131
1132 ulSaveReg0x26 = PeekShadow(0x26);
1133
1134 //
1135 // Note that we have saved registers that need to be restored during a
1136 // resume instead of ulAC97Regs[].
1137 //
1138 bPowerStateSaved = TRUE;
1139
1140 } // SavePowerState
1141 */
1142
1143 void cs4281_SuspendFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1144 {
1145 /*
1146 * We need to save the contents of the BASIC FIFO Registers.
1147 */
1148 pl->u32FCRn_Save = readl(s->pBA0 + pl->u32FCRnAddress);
1149 pl->u32FSICn_Save = readl(s->pBA0 + pl->u32FSICnAddress);
1150 }
1151 void cs4281_ResumeFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1152 {
1153 /*
1154 * We need to restore the contents of the BASIC FIFO Registers.
1155 */
1156 writel(pl->u32FCRn_Save,s->pBA0 + pl->u32FCRnAddress);
1157 writel(pl->u32FSICn_Save,s->pBA0 + pl->u32FSICnAddress);
1158 }
1159 void cs4281_SuspendDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1160 {
1161 //
1162 // We need to save the contents of the BASIC DMA Registers.
1163 //
1164 pl->u32DBAn_Save = readl(s->pBA0 + pl->u32DBAnAddress);
1165 pl->u32DBCn_Save = readl(s->pBA0 + pl->u32DBCnAddress);
1166 pl->u32DMRn_Save = readl(s->pBA0 + pl->u32DMRnAddress);
1167 pl->u32DCRn_Save = readl(s->pBA0 + pl->u32DCRnAddress);
1168 pl->u32DCCn_Save = readl(s->pBA0 + pl->u32DCCnAddress);
1169 pl->u32DCAn_Save = readl(s->pBA0 + pl->u32DCAnAddress);
1170 }
1171 void cs4281_ResumeDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1172 {
1173 //
1174 // We need to save the contents of the BASIC DMA Registers.
1175 //
1176 writel( pl->u32DBAn_Save, s->pBA0 + pl->u32DBAnAddress);
1177 writel( pl->u32DBCn_Save, s->pBA0 + pl->u32DBCnAddress);
1178 writel( pl->u32DMRn_Save, s->pBA0 + pl->u32DMRnAddress);
1179 writel( pl->u32DCRn_Save, s->pBA0 + pl->u32DCRnAddress);
1180 writel( pl->u32DCCn_Save, s->pBA0 + pl->u32DCCnAddress);
1181 writel( pl->u32DCAn_Save, s->pBA0 + pl->u32DCAnAddress);
1182 }
1183
1184 int cs4281_suspend(struct cs4281_state *s)
1185 {
1186 int i;
1187 u32 u32CLKCR1;
1188 struct cs4281_pm *pm = &s->pm;
1189 CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1190 printk("cs4281: cs4281_suspend()+ flags=%d\n",
1191 (unsigned)s->pm.flags));
1192 /*
1193 * check the current state, only suspend if IDLE
1194 */
1195 if(!(s->pm.flags & CS4281_PM_IDLE))
1196 {
1197 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1198 printk("cs4281: cs4281_suspend() unable to suspend, not IDLE\n"));
1199 return 1;
1200 }
1201 s->pm.flags &= ~CS4281_PM_IDLE;
1202 s->pm.flags |= CS4281_PM_SUSPENDING;
1203
1204 //
1205 // Gershwin CLKRUN - Set CKRA
1206 //
1207 u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1208
1209 pm->u32CLKCR1_SAVE = u32CLKCR1;
1210 if(!(u32CLKCR1 & 0x00010000 ) )
1211 writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1212
1213 //
1214 // First, turn on the clocks (yikes) to the devices, so that they will
1215 // respond when we try to save their state.
1216 //
1217 if(!(u32CLKCR1 & CLKCR1_SWCE))
1218 {
1219 writel(u32CLKCR1 | CLKCR1_SWCE , s->pBA0 + BA0_CLKCR1);
1220 }
1221
1222 //
1223 // Save the power state
1224 //
1225 pm->u32SSPMValue = readl(s->pBA0 + BA0_SSPM);
1226
1227 //
1228 // Disable interrupts.
1229 //
1230 writel(HICR_CHGM, s->pBA0 + BA0_HICR);
1231
1232 //
1233 // Save the PCM Playback Left and Right Volume Control.
1234 //
1235 pm->u32PPLVCvalue = readl(s->pBA0 + BA0_PPLVC);
1236 pm->u32PPRVCvalue = readl(s->pBA0 + BA0_PPRVC);
1237
1238 //
1239 // Save the FM Synthesis Left and Right Volume Control.
1240 //
1241 pm->u32FMLVCvalue = readl(s->pBA0 + BA0_FMLVC);
1242 pm->u32FMRVCvalue = readl(s->pBA0 + BA0_FMRVC);
1243
1244 //
1245 // Save the GPIOR value.
1246 //
1247 pm->u32GPIORvalue = readl(s->pBA0 + BA0_GPIOR);
1248
1249 //
1250 // Save the JSCTL value.
1251 //
1252 pm->u32JSCTLvalue = readl(s->pBA0 + BA0_GPIOR);
1253
1254 //
1255 // Save Sound System Control Register
1256 //
1257 pm->u32SSCR = readl(s->pBA0 + BA0_SSCR);
1258
1259 //
1260 // Save SRC Slot Assinment register
1261 //
1262 pm->u32SRCSA = readl(s->pBA0 + BA0_SRCSA);
1263
1264 //
1265 // Save sample rate
1266 //
1267 pm->u32DacASR = readl(s->pBA0 + BA0_PASR);
1268 pm->u32AdcASR = readl(s->pBA0 + BA0_CASR);
1269 pm->u32DacSR = readl(s->pBA0 + BA0_DACSR);
1270 pm->u32AdcSR = readl(s->pBA0 + BA0_ADCSR);
1271
1272 //
1273 // Loop through all of the PipeLines
1274 //
1275 for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1276 {
1277 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1278 {
1279 //
1280 // Ask the DMAengines and FIFOs to Suspend.
1281 //
1282 cs4281_SuspendDMAengine(s,&s->pl[i]);
1283 cs4281_SuspendFIFO(s,&s->pl[i]);
1284 }
1285 }
1286 //
1287 // We need to save the contents of the Midi Control Register.
1288 //
1289 pm->u32MIDCR_Save = readl(s->pBA0 + BA0_MIDCR);
1290 /*
1291 * save off the AC97 part information
1292 */
1293 cs4281_ac97_suspend(s);
1294
1295 //
1296 // Turn off the serial ports.
1297 //
1298 writel(0, s->pBA0 + BA0_SERMC);
1299
1300 //
1301 // Power off FM, Joystick, AC link,
1302 //
1303 writel(0, s->pBA0 + BA0_SSPM);
1304
1305 //
1306 // DLL off.
1307 //
1308 writel(0, s->pBA0 + BA0_CLKCR1);
1309
1310 //
1311 // AC link off.
1312 //
1313 writel(0, s->pBA0 + BA0_SPMC);
1314
1315 //
1316 // Put the chip into D3(hot) state.
1317 //
1318 // PokeBA0(BA0_PMCS, 0x00000003);
1319
1320 //
1321 // Gershwin CLKRUN - Clear CKRA
1322 //
1323 u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1324 writel(u32CLKCR1 & 0xFFFEFFFF, s->pBA0 + BA0_CLKCR1);
1325
1326 #ifdef CSDEBUG
1327 printpm(s);
1328 printpipelines(s);
1329 #endif
1330
1331 s->pm.flags &= ~CS4281_PM_SUSPENDING;
1332 s->pm.flags |= CS4281_PM_SUSPENDED;
1333
1334 CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
1335 printk("cs4281: cs4281_suspend()- flags=%d\n",
1336 (unsigned)s->pm.flags));
1337 return 0;
1338 }
1339
1340 int cs4281_resume(struct cs4281_state *s)
1341 {
1342 int i;
1343 unsigned temp1;
1344 u32 u32CLKCR1;
1345 struct cs4281_pm *pm = &s->pm;
1346 CS_DBGOUT(CS_PM | CS_FUNCTION, 4,
1347 printk( "cs4281: cs4281_resume()+ flags=%d\n",
1348 (unsigned)s->pm.flags));
1349 if(!(s->pm.flags & CS4281_PM_SUSPENDED))
1350 {
1351 CS_DBGOUT(CS_PM | CS_ERROR, 2,
1352 printk("cs4281: cs4281_resume() unable to resume, not SUSPENDED\n"));
1353 return 1;
1354 }
1355 s->pm.flags &= ~CS4281_PM_SUSPENDED;
1356 s->pm.flags |= CS4281_PM_RESUMING;
1357
1358 //
1359 // Gershwin CLKRUN - Set CKRA
1360 //
1361 u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1362 writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1363
1364 //
1365 // set the power state.
1366 //
1367 //old PokeBA0(BA0_PMCS, 0);
1368
1369 //
1370 // Program the clock circuit and serial ports.
1371 //
1372 temp1 = cs4281_hw_init(s);
1373 if (temp1) {
1374 CS_DBGOUT(CS_ERROR | CS_INIT, 1,
1375 printk(KERN_ERR
1376 "cs4281: resume cs4281_hw_init() error.\n"));
1377 return -1;
1378 }
1379
1380 //
1381 // restore the Power state
1382 //
1383 writel(pm->u32SSPMValue, s->pBA0 + BA0_SSPM);
1384
1385 //
1386 // Set post SRC mix setting (FM or ALT48K)
1387 //
1388 writel(pm->u32SSPM_BITS, s->pBA0 + BA0_SSPM);
1389
1390 //
1391 // Loop through all of the PipeLines
1392 //
1393 for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1394 {
1395 if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1396 {
1397 //
1398 // Ask the DMAengines and FIFOs to Resume.
1399 //
1400 cs4281_ResumeDMAengine(s,&s->pl[i]);
1401 cs4281_ResumeFIFO(s,&s->pl[i]);
1402 }
1403 }
1404 //
1405 // We need to restore the contents of the Midi Control Register.
1406 //
1407 writel(pm->u32MIDCR_Save, s->pBA0 + BA0_MIDCR);
1408
1409 cs4281_ac97_resume(s);
1410 //
1411 // Restore the PCM Playback Left and Right Volume Control.
1412 //
1413 writel(pm->u32PPLVCvalue, s->pBA0 + BA0_PPLVC);
1414 writel(pm->u32PPRVCvalue, s->pBA0 + BA0_PPRVC);
1415
1416 //
1417 // Restore the FM Synthesis Left and Right Volume Control.
1418 //
1419 writel(pm->u32FMLVCvalue, s->pBA0 + BA0_FMLVC);
1420 writel(pm->u32FMRVCvalue, s->pBA0 + BA0_FMRVC);
1421
1422 //
1423 // Restore the JSCTL value.
1424 //
1425 writel(pm->u32JSCTLvalue, s->pBA0 + BA0_JSCTL);
1426
1427 //
1428 // Restore the GPIOR register value.
1429 //
1430 writel(pm->u32GPIORvalue, s->pBA0 + BA0_GPIOR);
1431
1432 //
1433 // Restore Sound System Control Register
1434 //
1435 writel(pm->u32SSCR, s->pBA0 + BA0_SSCR);
1436
1437 //
1438 // Restore SRC Slot Assignment register
1439 //
1440 writel(pm->u32SRCSA, s->pBA0 + BA0_SRCSA);
1441
1442 //
1443 // Restore sample rate
1444 //
1445 writel(pm->u32DacASR, s->pBA0 + BA0_PASR);
1446 writel(pm->u32AdcASR, s->pBA0 + BA0_CASR);
1447 writel(pm->u32DacSR, s->pBA0 + BA0_DACSR);
1448 writel(pm->u32AdcSR, s->pBA0 + BA0_ADCSR);
1449
1450 //
1451 // Restore CFL1/2 registers we saved to compensate for OEM bugs.
1452 //
1453 // PokeBA0(BA0_CFLR, ulConfig);
1454
1455 //
1456 // Gershwin CLKRUN - Clear CKRA
1457 //
1458 writel(pm->u32CLKCR1_SAVE, s->pBA0 + BA0_CLKCR1);
1459
1460 //
1461 // Enable interrupts on the part.
1462 //
1463 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
1464
1465 #ifdef CSDEBUG
1466 printpm(s);
1467 printpipelines(s);
1468 #endif
1469 /*
1470 * change the state, restore the current hwptrs, then stop the dac/adc
1471 */
1472 s->pm.flags |= CS4281_PM_IDLE;
1473 s->pm.flags &= ~(CS4281_PM_SUSPENDING | CS4281_PM_SUSPENDED
1474 | CS4281_PM_RESUMING | CS4281_PM_RESUMED);
1475
1476 writel(s->pm.u32hwptr_playback, s->pBA0 + BA0_DCA0);
1477 writel(s->pm.u32hwptr_capture, s->pBA0 + BA0_DCA1);
1478 start_dac(s);
1479 start_adc(s);
1480
1481 CS_DBGOUT(CS_PM | CS_FUNCTION, 9, printk("cs4281: cs4281_resume()- flags=%d\n",
1482 (unsigned)s->pm.flags));
1483 return 0;
1484 }
1485
1486 #endif
1487
1488 //******************************************************************************
1489 // "cs4281_play_rate()" --
1490 //******************************************************************************
1491 static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
1492 {
1493 u32 DACSRvalue = 1;
1494
1495 // Based on the sample rate, program the DACSR register.
1496 if (playrate == 8000)
1497 DACSRvalue = 5;
1498 if (playrate == 11025)
1499 DACSRvalue = 4;
1500 else if (playrate == 22050)
1501 DACSRvalue = 2;
1502 else if (playrate == 44100)
1503 DACSRvalue = 1;
1504 else if ((playrate <= 48000) && (playrate >= 6023))
1505 DACSRvalue = 24576000 / (playrate * 16);
1506 else if (playrate < 6023)
1507 // Not allowed by open.
1508 return;
1509 else if (playrate > 48000)
1510 // Not allowed by open.
1511 return;
1512 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO
1513 "cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%d\n",
1514 DACSRvalue, playrate));
1515 // Write the 'sample rate select code'
1516 // to the 'DAC Sample Rate' register.
1517 writel(DACSRvalue, card->pBA0 + BA0_DACSR); // (744h)
1518 }
1519
1520 //******************************************************************************
1521 // "cs4281_record_rate()" -- Initialize the record sample rate converter.
1522 //******************************************************************************
1523 static void cs4281_record_rate(struct cs4281_state *card, u32 outrate)
1524 {
1525 u32 ADCSRvalue = 1;
1526
1527 //
1528 // Based on the sample rate, program the ADCSR register
1529 //
1530 if (outrate == 8000)
1531 ADCSRvalue = 5;
1532 if (outrate == 11025)
1533 ADCSRvalue = 4;
1534 else if (outrate == 22050)
1535 ADCSRvalue = 2;
1536 else if (outrate == 44100)
1537 ADCSRvalue = 1;
1538 else if ((outrate <= 48000) && (outrate >= 6023))
1539 ADCSRvalue = 24576000 / (outrate * 16);
1540 else if (outrate < 6023) {
1541 // Not allowed by open.
1542 return;
1543 } else if (outrate > 48000) {
1544 // Not allowed by open.
1545 return;
1546 }
1547 CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO
1548 "cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%d\n",
1549 ADCSRvalue, outrate));
1550 // Write the 'sample rate select code
1551 // to the 'ADC Sample Rate' register.
1552 writel(ADCSRvalue, card->pBA0 + BA0_ADCSR); // (748h)
1553 }
1554
1555
1556
1557 static void stop_dac(struct cs4281_state *s)
1558 {
1559 unsigned long flags;
1560 unsigned temp1;
1561
1562 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4281: stop_dac():\n"));
1563 spin_lock_irqsave(&s->lock, flags);
1564 s->ena &= ~FMODE_WRITE;
1565 temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK;
1566 writel(temp1, s->pBA0 + BA0_DCR0);
1567
1568 spin_unlock_irqrestore(&s->lock, flags);
1569 }
1570
1571
1572 static void start_dac(struct cs4281_state *s)
1573 {
1574 unsigned long flags;
1575 unsigned temp1;
1576
1577 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4281: start_dac()+\n"));
1578 spin_lock_irqsave(&s->lock, flags);
1579 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
1580 (s->dma_dac.count > 0
1581 && s->dma_dac.ready))
1582 #ifndef NOT_CS4281_PM
1583 && (s->pm.flags & CS4281_PM_IDLE))
1584 #else
1585 )
1586 #endif
1587 {
1588 s->ena |= FMODE_WRITE;
1589 temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK; // Clear DMA0 channel mask.
1590 writel(temp1, s->pBA0 + BA0_DCR0); // Start DMA'ing.
1591 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
1592
1593 writel(7, s->pBA0 + BA0_PPRVC);
1594 writel(7, s->pBA0 + BA0_PPLVC);
1595 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
1596 "cs4281: start_dac(): writel 0x%x start dma\n", temp1));
1597
1598 }
1599 spin_unlock_irqrestore(&s->lock, flags);
1600 CS_DBGOUT(CS_FUNCTION, 3,
1601 printk(KERN_INFO "cs4281: start_dac()-\n"));
1602 }
1603
1604
1605 static void stop_adc(struct cs4281_state *s)
1606 {
1607 unsigned long flags;
1608 unsigned temp1;
1609
1610 CS_DBGOUT(CS_FUNCTION, 3,
1611 printk(KERN_INFO "cs4281: stop_adc()+\n"));
1612
1613 spin_lock_irqsave(&s->lock, flags);
1614 s->ena &= ~FMODE_READ;
1615
1616 if (s->conversion == 1) {
1617 s->conversion = 0;
1618 s->prop_adc.fmt = s->prop_adc.fmt_original;
1619 }
1620 temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK;
1621 writel(temp1, s->pBA0 + BA0_DCR1);
1622 spin_unlock_irqrestore(&s->lock, flags);
1623 CS_DBGOUT(CS_FUNCTION, 3,
1624 printk(KERN_INFO "cs4281: stop_adc()-\n"));
1625 }
1626
1627
1628 static void start_adc(struct cs4281_state *s)
1629 {
1630 unsigned long flags;
1631 unsigned temp1;
1632
1633 CS_DBGOUT(CS_FUNCTION, 2,
1634 printk(KERN_INFO "cs4281: start_adc()+\n"));
1635
1636 if (!(s->ena & FMODE_READ) &&
1637 (s->dma_adc.mapped || s->dma_adc.count <=
1638 (signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize))
1639 && s->dma_adc.ready
1640 #ifndef NOT_CS4281_PM
1641 && (s->pm.flags & CS4281_PM_IDLE))
1642 #else
1643 )
1644 #endif
1645 {
1646 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
1647 //
1648 // now only use 16 bit capture, due to truncation issue
1649 // in the chip, noticable distortion occurs.
1650 // allocate buffer and then convert from 16 bit to
1651 // 8 bit for the user buffer.
1652 //
1653 s->prop_adc.fmt_original = s->prop_adc.fmt;
1654 if (s->prop_adc.fmt & AFMT_S8) {
1655 s->prop_adc.fmt &= ~AFMT_S8;
1656 s->prop_adc.fmt |= AFMT_S16_LE;
1657 }
1658 if (s->prop_adc.fmt & AFMT_U8) {
1659 s->prop_adc.fmt &= ~AFMT_U8;
1660 s->prop_adc.fmt |= AFMT_U16_LE;
1661 }
1662 //
1663 // prog_dmabuf_adc performs a stop_adc() but that is
1664 // ok since we really haven't started the DMA yet.
1665 //
1666 prog_codec(s, CS_TYPE_ADC);
1667
1668 if (prog_dmabuf_adc(s) != 0) {
1669 CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO
1670 "cs4281: start_adc(): error in prog_dmabuf_adc\n"));
1671 }
1672 s->conversion = 1;
1673 }
1674 spin_lock_irqsave(&s->lock, flags);
1675 s->ena |= FMODE_READ;
1676 temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK; // Clear DMA1 channel mask bit.
1677 writel(temp1, s->pBA0 + BA0_DCR1); // Start recording
1678 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
1679 spin_unlock_irqrestore(&s->lock, flags);
1680
1681 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
1682 "cs4281: start_adc(): writel 0x%x \n", temp1));
1683 }
1684 CS_DBGOUT(CS_FUNCTION, 2,
1685 printk(KERN_INFO "cs4281: start_adc()-\n"));
1686
1687 }
1688
1689
1690 // ---------------------------------------------------------------------
1691
1692 #define DMABUF_MINORDER 1 // ==> min buffer size = 8K.
1693
1694
1695 extern void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1696 {
1697 struct page *map, *mapend;
1698
1699 if (db->rawbuf) {
1700 // Undo prog_dmabuf()'s marking the pages as reserved
1701 mapend =
1702 virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -
1703 1);
1704 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1705 cs4x_mem_map_unreserve(map);
1706 free_dmabuf(s, db);
1707 }
1708 if (s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1709 // Undo prog_dmabuf()'s marking the pages as reserved
1710 mapend =
1711 virt_to_page(s->tmpbuff +
1712 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1713 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1714 cs4x_mem_map_unreserve(map);
1715 free_dmabuf2(s, db);
1716 }
1717 s->tmpbuff = NULL;
1718 db->rawbuf = NULL;
1719 db->mapped = db->ready = 0;
1720 }
1721
1722 static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1723 {
1724 int order;
1725 unsigned bytespersec, temp1;
1726 unsigned bufs, sample_shift = 0;
1727 struct page *map, *mapend;
1728 unsigned long df;
1729
1730 CS_DBGOUT(CS_FUNCTION, 2,
1731 printk(KERN_INFO "cs4281: prog_dmabuf()+\n"));
1732 db->hwptr = db->swptr = db->total_bytes = db->count = db->error =
1733 db->endcleared = db->blocks = db->wakeup = db->underrun = 0;
1734 /*
1735 * check for order within limits, but do not overwrite value, check
1736 * later for a fractional defaultorder (i.e. 100+).
1737 */
1738 if((defaultorder > 0) && (defaultorder < 12))
1739 df = defaultorder;
1740 else
1741 df = 1;
1742
1743 if (!db->rawbuf) {
1744 db->ready = db->mapped = 0;
1745 for (order = df; order >= DMABUF_MINORDER; order--)
1746 if ( (db->rawbuf = (void *) pci_alloc_consistent(
1747 s->pcidev, PAGE_SIZE << order, &db-> dmaaddr)))
1748 break;
1749 if (!db->rawbuf) {
1750 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1751 "cs4281: prog_dmabuf(): unable to allocate rawbuf\n"));
1752 return -ENOMEM;
1753 }
1754 db->buforder = order;
1755 // Now mark the pages as reserved; otherwise the
1756 // remap_page_range() in cs4281_mmap doesn't work.
1757 // 1. get index to last page in mem_map array for rawbuf.
1758 mapend = virt_to_page(db->rawbuf +
1759 (PAGE_SIZE << db->buforder) - 1);
1760
1761 // 2. mark each physical page in range as 'reserved'.
1762 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1763 cs4x_mem_map_reserve(map);
1764 }
1765 if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1766 for (order = df; order >= DMABUF_MINORDER;
1767 order--)
1768 if ( (s->tmpbuff = (void *) pci_alloc_consistent(
1769 s->pcidev, PAGE_SIZE << order,
1770 &s->dmaaddr_tmpbuff)))
1771 break;
1772 if (!s->tmpbuff) {
1773 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1774 "cs4281: prog_dmabuf(): unable to allocate tmpbuff\n"));
1775 return -ENOMEM;
1776 }
1777 s->buforder_tmpbuff = order;
1778 // Now mark the pages as reserved; otherwise the
1779 // remap_page_range() in cs4281_mmap doesn't work.
1780 // 1. get index to last page in mem_map array for rawbuf.
1781 mapend = virt_to_page(s->tmpbuff +
1782 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1783
1784 // 2. mark each physical page in range as 'reserved'.
1785 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1786 cs4x_mem_map_reserve(map);
1787 }
1788 if (db->type == CS_TYPE_DAC) {
1789 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1790 sample_shift++;
1791 if (s->prop_dac.channels > 1)
1792 sample_shift++;
1793 bytespersec = s->prop_dac.rate << sample_shift;
1794 } else // CS_TYPE_ADC
1795 {
1796 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1797 sample_shift++;
1798 if (s->prop_adc.channels > 1)
1799 sample_shift++;
1800 bytespersec = s->prop_adc.rate << sample_shift;
1801 }
1802 bufs = PAGE_SIZE << db->buforder;
1803
1804 /*
1805 * added fractional "defaultorder" inputs. if >100 then use
1806 * defaultorder-100 as power of 2 for the buffer size. example:
1807 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
1808 */
1809 if(defaultorder >= 100)
1810 {
1811 bufs = 1 << (defaultorder-100);
1812 }
1813
1814 #define INTERRUPT_RATE_MS 100 // Interrupt rate in milliseconds.
1815 db->numfrag = 2;
1816 /*
1817 * Nominal frag size(bytes/interrupt)
1818 */
1819 temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS);
1820 db->fragshift = 8; // Min 256 bytes.
1821 while (1 << db->fragshift < temp1) // Calc power of 2 frag size.
1822 db->fragshift += 1;
1823 db->fragsize = 1 << db->fragshift;
1824 db->dmasize = db->fragsize * 2;
1825 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1826
1827 // If the calculated size is larger than the allocated
1828 // buffer, divide the allocated buffer into 2 fragments.
1829 if (db->dmasize > bufs) {
1830
1831 db->numfrag = 2; // Two fragments.
1832 db->fragsize = bufs >> 1; // Each 1/2 the alloc'ed buffer.
1833 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1834 db->dmasize = bufs; // Use all the alloc'ed buffer.
1835
1836 db->fragshift = 0; // Calculate 'fragshift'.
1837 temp1 = db->fragsize; // update_ptr() uses it
1838 while ((temp1 >>= 1) > 1) // to calc 'total-bytes'
1839 db->fragshift += 1; // returned in DSP_GETI/OPTR.
1840 }
1841 CS_DBGOUT(CS_PARMS, 3, printk(KERN_INFO
1842 "cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%d\n",
1843 db->numfrag, db->fragsize, db->fragsamples,
1844 db->fragshift, bufs,
1845 (db->type == CS_TYPE_DAC) ? s->prop_dac.fmt :
1846 s->prop_adc.fmt,
1847 (db->type == CS_TYPE_DAC) ? s->prop_dac.channels :
1848 s->prop_adc.channels));
1849 CS_DBGOUT(CS_FUNCTION, 2,
1850 printk(KERN_INFO "cs4281: prog_dmabuf()-\n"));
1851 return 0;
1852 }
1853
1854
1855 static int prog_dmabuf_adc(struct cs4281_state *s)
1856 {
1857 unsigned long va;
1858 unsigned count;
1859 int c;
1860 stop_adc(s);
1861 s->dma_adc.type = CS_TYPE_ADC;
1862 if ((c = prog_dmabuf(s, &s->dma_adc)))
1863 return c;
1864
1865 if (s->dma_adc.rawbuf) {
1866 memset(s->dma_adc.rawbuf,
1867 (s->prop_adc.
1868 fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1869 s->dma_adc.dmasize);
1870 }
1871 if (s->tmpbuff) {
1872 memset(s->tmpbuff,
1873 (s->prop_adc.
1874 fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1875 PAGE_SIZE << s->buforder_tmpbuff);
1876 }
1877
1878 va = virt_to_bus(s->dma_adc.rawbuf);
1879
1880 count = s->dma_adc.dmasize;
1881
1882 if (s->prop_adc.
1883 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1884 count /= 2; // 16-bit.
1885
1886 if (s->prop_adc.channels > 1)
1887 count /= 2; // Assume stereo.
1888
1889 CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO
1890 "cs4281: prog_dmabuf_adc(): count=%d va=0x%.8x\n",
1891 count, (unsigned) va));
1892
1893 writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address.
1894 writel(count - 1, s->pBA0 + BA0_DBC1); // Set count.
1895 s->dma_adc.ready = 1;
1896 return 0;
1897 }
1898
1899
1900 static int prog_dmabuf_dac(struct cs4281_state *s)
1901 {
1902 unsigned long va;
1903 unsigned count;
1904 int c;
1905 stop_dac(s);
1906 s->dma_dac.type = CS_TYPE_DAC;
1907 if ((c = prog_dmabuf(s, &s->dma_dac)))
1908 return c;
1909 memset(s->dma_dac.rawbuf,
1910 (s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1911 s->dma_dac.dmasize);
1912
1913 va = virt_to_bus(s->dma_dac.rawbuf);
1914
1915 count = s->dma_dac.dmasize;
1916 if (s->prop_dac.
1917 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1918 count /= 2; // 16-bit.
1919
1920 if (s->prop_dac.channels > 1)
1921 count /= 2; // Assume stereo.
1922
1923 writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address.
1924 writel(count - 1, s->pBA0 + BA0_DBC0); // Set count.
1925
1926 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO
1927 "cs4281: prog_dmabuf_dac(): count=%d va=0x%.8x\n",
1928 count, (unsigned) va));
1929
1930 s->dma_dac.ready = 1;
1931 return 0;
1932 }
1933
1934
1935 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
1936 unsigned len, unsigned char c)
1937 {
1938 if (bptr + len > bsize) {
1939 unsigned x = bsize - bptr;
1940 memset(((char *) buf) + bptr, c, x);
1941 bptr = 0;
1942 len -= x;
1943 }
1944 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1945 "cs4281: clear_advance(): memset %d at 0x%.8x for %d size \n",
1946 (unsigned)c, (unsigned)((char *) buf) + bptr, len));
1947 memset(((char *) buf) + bptr, c, len);
1948 }
1949
1950
1951
1952 // call with spinlock held!
1953 static void cs4281_update_ptr(struct cs4281_state *s, int intflag)
1954 {
1955 int diff;
1956 unsigned hwptr, va;
1957
1958 // update ADC pointer
1959 if (s->ena & FMODE_READ) {
1960 hwptr = readl(s->pBA0 + BA0_DCA1); // Read capture DMA address.
1961 va = virt_to_bus(s->dma_adc.rawbuf);
1962 hwptr -= (unsigned) va;
1963 diff =
1964 (s->dma_adc.dmasize + hwptr -
1965 s->dma_adc.hwptr) % s->dma_adc.dmasize;
1966 s->dma_adc.hwptr = hwptr;
1967 s->dma_adc.total_bytes += diff;
1968 s->dma_adc.count += diff;
1969 if (s->dma_adc.count > s->dma_adc.dmasize)
1970 s->dma_adc.count = s->dma_adc.dmasize;
1971 if (s->dma_adc.mapped) {
1972 if (s->dma_adc.count >=
1973 (signed) s->dma_adc.fragsize) wake_up(&s->
1974 dma_adc.
1975 wait);
1976 } else {
1977 if (s->dma_adc.count > 0)
1978 wake_up(&s->dma_adc.wait);
1979 }
1980 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1981 "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1982 (unsigned)s, s->dma_adc.hwptr,
1983 s->dma_adc.total_bytes, s->dma_adc.count));
1984 }
1985 // update DAC pointer
1986 //
1987 // check for end of buffer, means that we are going to wait for another interrupt
1988 // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1989 //
1990 if (s->ena & FMODE_WRITE) {
1991 hwptr = readl(s->pBA0 + BA0_DCA0); // Read play DMA address.
1992 va = virt_to_bus(s->dma_dac.rawbuf);
1993 hwptr -= (unsigned) va;
1994 diff = (s->dma_dac.dmasize + hwptr -
1995 s->dma_dac.hwptr) % s->dma_dac.dmasize;
1996 s->dma_dac.hwptr = hwptr;
1997 s->dma_dac.total_bytes += diff;
1998 if (s->dma_dac.mapped) {
1999 s->dma_dac.count += diff;
2000 if (s->dma_dac.count >= s->dma_dac.fragsize) {
2001 s->dma_dac.wakeup = 1;
2002 wake_up(&s->dma_dac.wait);
2003 if (s->dma_dac.count > s->dma_dac.dmasize)
2004 s->dma_dac.count &=
2005 s->dma_dac.dmasize - 1;
2006 }
2007 } else {
2008 s->dma_dac.count -= diff;
2009 if (s->dma_dac.count <= 0) {
2010 //
2011 // fill with silence, and do not shut down the DAC.
2012 // Continue to play silence until the _release.
2013 //
2014 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
2015 "cs4281: cs4281_update_ptr(): memset %d at 0x%.8x for %d size \n",
2016 (unsigned)(s->prop_dac.fmt &
2017 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
2018 (unsigned)s->dma_dac.rawbuf,
2019 s->dma_dac.dmasize));
2020 memset(s->dma_dac.rawbuf,
2021 (s->prop_dac.
2022 fmt & (AFMT_U8 | AFMT_U16_LE)) ?
2023 0x80 : 0, s->dma_dac.dmasize);
2024 if (s->dma_dac.count < 0) {
2025 s->dma_dac.underrun = 1;
2026 s->dma_dac.count = 0;
2027 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
2028 "cs4281: cs4281_update_ptr(): underrun\n"));
2029 }
2030 } else if (s->dma_dac.count <=
2031 (signed) s->dma_dac.fragsize
2032 && !s->dma_dac.endcleared) {
2033 clear_advance(s->dma_dac.rawbuf,
2034 s->dma_dac.dmasize,
2035 s->dma_dac.swptr,
2036 s->dma_dac.fragsize,
2037 (s->prop_dac.
2038 fmt & (AFMT_U8 |
2039 AFMT_U16_LE)) ? 0x80
2040 : 0);
2041 s->dma_dac.endcleared = 1;
2042 }
2043 if ( (s->dma_dac.count <= (signed) s->dma_dac.dmasize/2) ||
2044 intflag)
2045 {
2046 wake_up(&s->dma_dac.wait);
2047 }
2048 }
2049 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
2050 "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
2051 (unsigned) s, s->dma_dac.hwptr,
2052 s->dma_dac.total_bytes, s->dma_dac.count));
2053 }
2054 }
2055
2056
2057 // ---------------------------------------------------------------------
2058
2059 static void prog_codec(struct cs4281_state *s, unsigned type)
2060 {
2061 unsigned long flags;
2062 unsigned temp1, format;
2063
2064 CS_DBGOUT(CS_FUNCTION, 2,
2065 printk(KERN_INFO "cs4281: prog_codec()+ \n"));
2066
2067 spin_lock_irqsave(&s->lock, flags);
2068 if (type == CS_TYPE_ADC) {
2069 temp1 = readl(s->pBA0 + BA0_DCR1);
2070 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1); // Stop capture DMA, if active.
2071
2072 // program sampling rates
2073 // Note, for CS4281, capture & play rates can be set independently.
2074 cs4281_record_rate(s, s->prop_adc.rate);
2075
2076 // program ADC parameters
2077 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
2078 if (s->prop_adc.
2079 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
2080 if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE)) // Big-endian?
2081 format |= DMRn_BEND;
2082 if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2083 format |= DMRn_USIGN; // Unsigned.
2084 } else
2085 format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
2086 if (s->prop_adc.channels < 2)
2087 format |= DMRn_MONO;
2088
2089 writel(format, s->pBA0 + BA0_DMR1);
2090
2091 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2092 "cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8x\n",
2093 (format & DMRn_SIZE8) ? "8" : "16",
2094 (format & DMRn_USIGN) ? "Unsigned" : "Signed",
2095 (format & DMRn_MONO) ? "Mono" : "Stereo",
2096 s->prop_adc.rate, format));
2097
2098 s->ena &= ~FMODE_READ; // not capturing data yet
2099 }
2100
2101
2102 if (type == CS_TYPE_DAC) {
2103 temp1 = readl(s->pBA0 + BA0_DCR0);
2104 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0); // Stop play DMA, if active.
2105
2106 // program sampling rates
2107 // Note, for CS4281, capture & play rates can be set independently.
2108 cs4281_play_rate(s, s->prop_dac.rate);
2109
2110 // program DAC parameters
2111 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
2112 if (s->prop_dac.
2113 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
2114 if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE))
2115 format |= DMRn_BEND; // Big Endian.
2116 if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2117 format |= DMRn_USIGN; // Unsigned.
2118 } else
2119 format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
2120
2121 if (s->prop_dac.channels < 2)
2122 format |= DMRn_MONO;
2123
2124 writel(format, s->pBA0 + BA0_DMR0);
2125
2126
2127 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2128 "cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8x\n",
2129 (format & DMRn_SIZE8) ? "8" : "16",
2130 (format & DMRn_USIGN) ? "Unsigned" : "Signed",
2131 (format & DMRn_MONO) ? "Mono" : "Stereo",
2132 s->prop_dac.rate, format));
2133
2134 s->ena &= ~FMODE_WRITE; // not capturing data yet
2135
2136 }
2137 spin_unlock_irqrestore(&s->lock, flags);
2138 CS_DBGOUT(CS_FUNCTION, 2,
2139 printk(KERN_INFO "cs4281: prog_codec()- \n"));
2140 }
2141
2142
2143 static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd,
2144 unsigned long arg)
2145 {
2146 // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
2147 // Value of array member is recording source Device ID Mask.
2148 static const unsigned int mixer_src[8] = {
2149 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
2150 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
2151 };
2152
2153 // Index of mixtable1[] member is Device ID
2154 // and must be <= SOUND_MIXER_NRDEVICES.
2155 // Value of array member is index into s->mix.vol[]
2156 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
2157 [SOUND_MIXER_PCM] = 1, // voice
2158 [SOUND_MIXER_LINE1] = 2, // AUX
2159 [SOUND_MIXER_CD] = 3, // CD
2160 [SOUND_MIXER_LINE] = 4, // Line
2161 [SOUND_MIXER_SYNTH] = 5, // FM
2162 [SOUND_MIXER_MIC] = 6, // Mic
2163 [SOUND_MIXER_SPEAKER] = 7, // Speaker
2164 [SOUND_MIXER_RECLEV] = 8, // Recording level
2165 [SOUND_MIXER_VOLUME] = 9 // Master Volume
2166 };
2167
2168
2169 static const unsigned mixreg[] = {
2170 BA0_AC97_PCM_OUT_VOLUME,
2171 BA0_AC97_AUX_VOLUME,
2172 BA0_AC97_CD_VOLUME,
2173 BA0_AC97_LINE_IN_VOLUME
2174 };
2175 unsigned char l, r, rl, rr, vidx;
2176 unsigned char attentbl[11] =
2177 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
2178 unsigned temp1;
2179 int i, val;
2180
2181 VALIDATE_STATE(s);
2182 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
2183 "cs4281: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
2184 (unsigned) s, cmd));
2185 #if CSDEBUG
2186 cs_printioctl(cmd);
2187 #endif
2188 #if CSDEBUG_INTERFACE
2189
2190 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
2191 (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
2192 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
2193 (cmd == SOUND_MIXER_CS_SETDBGLEVEL) ||
2194 (cmd == SOUND_MIXER_CS_APM))
2195 {
2196 switch (cmd) {
2197
2198 case SOUND_MIXER_CS_GETDBGMASK:
2199 return put_user(cs_debugmask,
2200 (unsigned long *) arg);
2201
2202 case SOUND_MIXER_CS_GETDBGLEVEL:
2203 return put_user(cs_debuglevel,
2204 (unsigned long *) arg);
2205
2206 case SOUND_MIXER_CS_SETDBGMASK:
2207 if (get_user(val, (unsigned long *) arg))
2208 return -EFAULT;
2209 cs_debugmask = val;
2210 return 0;
2211
2212 case SOUND_MIXER_CS_SETDBGLEVEL:
2213 if (get_user(val, (unsigned long *) arg))
2214 return -EFAULT;
2215 cs_debuglevel = val;
2216 return 0;
2217 #ifndef NOT_CS4281_PM
2218 case SOUND_MIXER_CS_APM:
2219 if (get_user(val, (unsigned long *) arg))
2220 return -EFAULT;
2221 if(val == CS_IOCTL_CMD_SUSPEND)
2222 cs4281_suspend(s);
2223 else if(val == CS_IOCTL_CMD_RESUME)
2224 cs4281_resume(s);
2225 else
2226 {
2227 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2228 "cs4281: mixer_ioctl(): invalid APM cmd (%d)\n",
2229 val));
2230 }
2231 return 0;
2232 #endif
2233 default:
2234 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2235 "cs4281: mixer_ioctl(): ERROR unknown debug cmd\n"));
2236 return 0;
2237 }
2238 }
2239 #endif
2240
2241 if (cmd == SOUND_MIXER_PRIVATE1) {
2242 // enable/disable/query mixer preamp
2243 if (get_user(val, (int *) arg))
2244 return -EFAULT;
2245 if (val != -1) {
2246 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2247 temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
2248 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2249 }
2250 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2251 val = (temp1 & 0x40) ? 1 : 0;
2252 return put_user(val, (int *) arg);
2253 }
2254 if (cmd == SOUND_MIXER_PRIVATE2) {
2255 // enable/disable/query spatializer
2256 if (get_user(val, (int *) arg))
2257 return -EFAULT;
2258 if (val != -1) {
2259 temp1 = (val & 0x3f) >> 2;
2260 cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
2261 cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2262 &temp1);
2263 cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2264 temp1 | 0x2000);
2265 }
2266 cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
2267 return put_user((temp1 << 2) | 3, (int *) arg);
2268 }
2269 if (cmd == SOUND_MIXER_INFO) {
2270 mixer_info info;
2271 strncpy(info.id, "CS4281", sizeof(info.id));
2272 strncpy(info.name, "Crystal CS4281", sizeof(info.name));
2273 info.modify_counter = s->mix.modcnt;
2274 if (copy_to_user((void *) arg, &info, sizeof(info)))
2275 return -EFAULT;
2276 return 0;
2277 }
2278 if (cmd == SOUND_OLD_MIXER_INFO) {
2279 _old_mixer_info info;
2280 strncpy(info.id, "CS4281", sizeof(info.id));
2281 strncpy(info.name, "Crystal CS4281", sizeof(info.name));
2282 if (copy_to_user((void *) arg, &info, sizeof(info)))
2283 return -EFAULT;
2284 return 0;
2285 }
2286 if (cmd == OSS_GETVERSION)
2287 return put_user(SOUND_VERSION, (int *) arg);
2288
2289 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
2290 return -EINVAL;
2291
2292 // If ioctl has only the SIOC_READ bit(bit 31)
2293 // on, process the only-read commands.
2294 if (_SIOC_DIR(cmd) == _SIOC_READ) {
2295 switch (_IOC_NR(cmd)) {
2296 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
2297 cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT,
2298 &temp1);
2299 return put_user(mixer_src[temp1 & 7], (int *) arg);
2300
2301 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
2302 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2303 SOUND_MASK_CD | SOUND_MASK_LINE |
2304 SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2305 SOUND_MASK_VOLUME |
2306 SOUND_MASK_RECLEV |
2307 SOUND_MASK_SPEAKER, (int *) arg);
2308
2309 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
2310 return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC |
2311 SOUND_MASK_CD | SOUND_MASK_VOLUME |
2312 SOUND_MASK_LINE1, (int *) arg);
2313
2314 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
2315 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2316 SOUND_MASK_CD | SOUND_MASK_LINE |
2317 SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2318 SOUND_MASK_VOLUME |
2319 SOUND_MASK_RECLEV, (int *) arg);
2320
2321 case SOUND_MIXER_CAPS:
2322 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
2323
2324 default:
2325 i = _IOC_NR(cmd);
2326 if (i >= SOUND_MIXER_NRDEVICES
2327 || !(vidx = mixtable1[i]))
2328 return -EINVAL;
2329 return put_user(s->mix.vol[vidx - 1], (int *) arg);
2330 }
2331 }
2332 // If ioctl doesn't have both the SIOC_READ and
2333 // the SIOC_WRITE bit set, return invalid.
2334 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
2335 return -EINVAL;
2336
2337 // Increment the count of volume writes.
2338 s->mix.modcnt++;
2339
2340 // Isolate the command; it must be a write.
2341 switch (_IOC_NR(cmd)) {
2342
2343 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
2344 if (get_user(val, (int *) arg))
2345 return -EFAULT;
2346 i = hweight32(val); // i = # bits on in val.
2347 if (i != 1) // One & only 1 bit must be on.
2348 return 0;
2349 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
2350 if (val == mixer_src[i]) {
2351 temp1 = (i << 8) | i;
2352 cs4281_write_ac97(s,
2353 BA0_AC97_RECORD_SELECT,
2354 temp1);
2355 return 0;
2356 }
2357 }
2358 return 0;
2359
2360 case SOUND_MIXER_VOLUME:
2361 if (get_user(val, (int *) arg))
2362 return -EFAULT;
2363 l = val & 0xff;
2364 if (l > 100)
2365 l = 100; // Max soundcard.h vol is 100.
2366 if (l < 6) {
2367 rl = 63;
2368 l = 0;
2369 } else
2370 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
2371
2372 r = (val >> 8) & 0xff;
2373 if (r > 100)
2374 r = 100; // Max right volume is 100, too
2375 if (r < 6) {
2376 rr = 63;
2377 r = 0;
2378 } else
2379 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
2380
2381 if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
2382 temp1 = 0x8000; // turn on the mute bit.
2383 else
2384 temp1 = 0;
2385
2386 temp1 |= (rl << 8) | rr;
2387
2388 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1);
2389 cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1);
2390
2391 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2392 s->mix.vol[8] = ((unsigned int) r << 8) | l;
2393 #else
2394 s->mix.vol[8] = val;
2395 #endif
2396 return put_user(s->mix.vol[8], (int *) arg);
2397
2398 case SOUND_MIXER_SPEAKER:
2399 if (get_user(val, (int *) arg))
2400 return -EFAULT;
2401 l = val & 0xff;
2402 if (l > 100)
2403 l = 100;
2404 if (l < 3) {
2405 rl = 0;
2406 l = 0;
2407 } else {
2408 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
2409 l = (rl * 13 + 5) / 2;
2410 }
2411
2412 if (rl < 3) {
2413 temp1 = 0x8000;
2414 rl = 0;
2415 } else
2416 temp1 = 0;
2417 rl = 15 - rl; // Convert volume to attenuation.
2418 temp1 |= rl << 1;
2419 cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1);
2420
2421 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2422 s->mix.vol[6] = l << 8;
2423 #else
2424 s->mix.vol[6] = val;
2425 #endif
2426 return put_user(s->mix.vol[6], (int *) arg);
2427
2428 case SOUND_MIXER_RECLEV:
2429 if (get_user(val, (int *) arg))
2430 return -EFAULT;
2431 l = val & 0xff;
2432 if (l > 100)
2433 l = 100;
2434 r = (val >> 8) & 0xff;
2435 if (r > 100)
2436 r = 100;
2437 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
2438 rr = (r * 2 - 5) / 13;
2439 if (rl < 3 && rr < 3)
2440 temp1 = 0x8000;
2441 else
2442 temp1 = 0;
2443
2444 temp1 = temp1 | (rl << 8) | rr;
2445 cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1);
2446
2447 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2448 s->mix.vol[7] = ((unsigned int) r << 8) | l;
2449 #else
2450 s->mix.vol[7] = val;
2451 #endif
2452 return put_user(s->mix.vol[7], (int *) arg);
2453
2454 case SOUND_MIXER_MIC:
2455 if (get_user(val, (int *) arg))
2456 return -EFAULT;
2457 l = val & 0xff;
2458 if (l > 100)
2459 l = 100;
2460 if (l < 1) {
2461 l = 0;
2462 rl = 0;
2463 } else {
2464 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
2465 l = (rl * 16 + 4) / 5;
2466 }
2467 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2468 temp1 &= 0x40; // Isolate 20db gain bit.
2469 if (rl < 3) {
2470 temp1 |= 0x8000;
2471 rl = 0;
2472 }
2473 rl = 31 - rl; // Convert volume to attenuation.
2474 temp1 |= rl;
2475 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2476
2477 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2478 s->mix.vol[5] = val << 8;
2479 #else
2480 s->mix.vol[5] = val;
2481 #endif
2482 return put_user(s->mix.vol[5], (int *) arg);
2483
2484
2485 case SOUND_MIXER_SYNTH:
2486 if (get_user(val, (int *) arg))
2487 return -EFAULT;
2488 l = val & 0xff;
2489 if (l > 100)
2490 l = 100;
2491 if (get_user(val, (int *) arg))
2492 return -EFAULT;
2493 r = (val >> 8) & 0xff;
2494 if (r > 100)
2495 r = 100;
2496 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
2497 rr = (r * 2 - 11) / 3;
2498 if (rl < 3) // If l is low, turn on
2499 temp1 = 0x0080; // the mute bit.
2500 else
2501 temp1 = 0;
2502
2503 rl = 63 - rl; // Convert vol to attenuation.
2504 writel(temp1 | rl, s->pBA0 + BA0_FMLVC);
2505 if (rr < 3) // If rr is low, turn on
2506 temp1 = 0x0080; // the mute bit.
2507 else
2508 temp1 = 0;
2509 rr = 63 - rr; // Convert vol to attenuation.
2510 writel(temp1 | rr, s->pBA0 + BA0_FMRVC);
2511
2512 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2513 s->mix.vol[4] = (r << 8) | l;
2514 #else
2515 s->mix.vol[4] = val;
2516 #endif
2517 return put_user(s->mix.vol[4], (int *) arg);
2518
2519
2520 default:
2521 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2522 "cs4281: mixer_ioctl(): default\n"));
2523
2524 i = _IOC_NR(cmd);
2525 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
2526 return -EINVAL;
2527 if (get_user(val, (int *) arg))
2528 return -EFAULT;
2529 l = val & 0xff;
2530 if (l > 100)
2531 l = 100;
2532 if (l < 1) {
2533 l = 0;
2534 rl = 31;
2535 } else
2536 rl = (attentbl[(l * 10) / 100]) >> 1;
2537
2538 r = (val >> 8) & 0xff;
2539 if (r > 100)
2540 r = 100;
2541 if (r < 1) {
2542 r = 0;
2543 rr = 31;
2544 } else
2545 rr = (attentbl[(r * 10) / 100]) >> 1;
2546 if ((rl > 30) && (rr > 30))
2547 temp1 = 0x8000;
2548 else
2549 temp1 = 0;
2550 temp1 = temp1 | (rl << 8) | rr;
2551 cs4281_write_ac97(s, mixreg[vidx - 1], temp1);
2552
2553 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2554 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
2555 #else
2556 s->mix.vol[vidx - 1] = val;
2557 #endif
2558 #ifndef NOT_CS4281_PM
2559 CS_DBGOUT(CS_PM, 9, printk(KERN_INFO
2560 "write ac97 mixreg[%d]=0x%x mix.vol[]=0x%x\n",
2561 vidx-1,temp1,s->mix.vol[vidx-1]));
2562 #endif
2563 return put_user(s->mix.vol[vidx - 1], (int *) arg);
2564 }
2565 }
2566
2567
2568 // ---------------------------------------------------------------------
2569
2570 static int cs4281_open_mixdev(struct inode *inode, struct file *file)
2571 {
2572 int minor = MINOR(inode->i_rdev);
2573 struct cs4281_state *s=NULL;
2574 struct list_head *entry;
2575
2576 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2577 printk(KERN_INFO "cs4281: cs4281_open_mixdev()+\n"));
2578
2579 list_for_each(entry, &cs4281_devs)
2580 {
2581 s = list_entry(entry, struct cs4281_state, list);
2582 if(s->dev_mixer == minor)
2583 break;
2584 }
2585 if (!s)
2586 {
2587 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
2588 printk(KERN_INFO "cs4281: cs4281_open_mixdev()- -ENODEV\n"));
2589 return -ENODEV;
2590 }
2591 VALIDATE_STATE(s);
2592 file->private_data = s;
2593 MOD_INC_USE_COUNT;
2594
2595 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2596 printk(KERN_INFO "cs4281: cs4281_open_mixdev()- 0\n"));
2597
2598 return 0;
2599 }
2600
2601
2602 static int cs4281_release_mixdev(struct inode *inode, struct file *file)
2603 {
2604 struct cs4281_state *s =
2605 (struct cs4281_state *) file->private_data;
2606
2607 VALIDATE_STATE(s);
2608 MOD_DEC_USE_COUNT;
2609 return 0;
2610 }
2611
2612
2613 static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file,
2614 unsigned int cmd, unsigned long arg)
2615 {
2616 return mixer_ioctl((struct cs4281_state *) file->private_data, cmd,
2617 arg);
2618 }
2619
2620
2621 // ******************************************************************************************
2622 // Mixer file operations struct.
2623 // ******************************************************************************************
2624 static /*const */ struct file_operations cs4281_mixer_fops = {
2625 llseek:no_llseek,
2626 ioctl:cs4281_ioctl_mixdev,
2627 open:cs4281_open_mixdev,
2628 release:cs4281_release_mixdev,
2629 };
2630
2631 // ---------------------------------------------------------------------
2632
2633
2634 static int drain_adc(struct cs4281_state *s, int nonblock)
2635 {
2636 DECLARE_WAITQUEUE(wait, current);
2637 unsigned long flags;
2638 int count;
2639 unsigned tmo;
2640
2641 if (s->dma_adc.mapped)
2642 return 0;
2643 add_wait_queue(&s->dma_adc.wait, &wait);
2644 for (;;) {
2645 set_current_state(TASK_INTERRUPTIBLE);
2646 spin_lock_irqsave(&s->lock, flags);
2647 count = s->dma_adc.count;
2648 CS_DBGOUT(CS_FUNCTION, 2,
2649 printk(KERN_INFO "cs4281: drain_adc() %d\n", count));
2650 spin_unlock_irqrestore(&s->lock, flags);
2651 if (count <= 0) {
2652 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2653 "cs4281: drain_adc() count<0\n"));
2654 break;
2655 }
2656 if (signal_pending(current))
2657 break;
2658 if (nonblock) {
2659 remove_wait_queue(&s->dma_adc.wait, &wait);
2660 current->state = TASK_RUNNING;
2661 return -EBUSY;
2662 }
2663 tmo =
2664 3 * HZ * (count +
2665 s->dma_adc.fragsize) / 2 / s->prop_adc.rate;
2666 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2667 tmo >>= 1;
2668 if (s->prop_adc.channels > 1)
2669 tmo >>= 1;
2670 if (!schedule_timeout(tmo + 1))
2671 printk(KERN_DEBUG "cs4281: dma timed out??\n");
2672 }
2673 remove_wait_queue(&s->dma_adc.wait, &wait);
2674 current->state = TASK_RUNNING;
2675 if (signal_pending(current))
2676 return -ERESTARTSYS;
2677 return 0;
2678 }
2679
2680 static int drain_dac(struct cs4281_state *s, int nonblock)
2681 {
2682 DECLARE_WAITQUEUE(wait, current);
2683 unsigned long flags;
2684 int count;
2685 unsigned tmo;
2686
2687 if (s->dma_dac.mapped)
2688 return 0;
2689 add_wait_queue(&s->dma_dac.wait, &wait);
2690 for (;;) {
2691 set_current_state(TASK_INTERRUPTIBLE);
2692 spin_lock_irqsave(&s->lock, flags);
2693 count = s->dma_dac.count;
2694 spin_unlock_irqrestore(&s->lock, flags);
2695 if (count <= 0)
2696 break;
2697 if (signal_pending(current))
2698 break;
2699 if (nonblock) {
2700 remove_wait_queue(&s->dma_dac.wait, &wait);
2701 current->state = TASK_RUNNING;
2702 return -EBUSY;
2703 }
2704 tmo =
2705 3 * HZ * (count +
2706 s->dma_dac.fragsize) / 2 / s->prop_dac.rate;
2707 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2708 tmo >>= 1;
2709 if (s->prop_dac.channels > 1)
2710 tmo >>= 1;
2711 if (!schedule_timeout(tmo + 1))
2712 printk(KERN_DEBUG "cs4281: dma timed out??\n");
2713 }
2714 remove_wait_queue(&s->dma_dac.wait, &wait);
2715 current->state = TASK_RUNNING;
2716 if (signal_pending(current))
2717 return -ERESTARTSYS;
2718 return 0;
2719 }
2720
2721 //****************************************************************************
2722 //
2723 // CopySamples copies 16-bit stereo samples from the source to the
2724 // destination, possibly converting down to either 8-bit or mono or both.
2725 // count specifies the number of output bytes to write.
2726 //
2727 // Arguments:
2728 //
2729 // dst - Pointer to a destination buffer.
2730 // src - Pointer to a source buffer
2731 // count - The number of bytes to copy into the destination buffer.
2732 // iChannels - Stereo - 2
2733 // Mono - 1
2734 // fmt - AFMT_xxx (soundcard.h formats)
2735 //
2736 // NOTES: only call this routine for conversion to 8bit from 16bit
2737 //
2738 //****************************************************************************
2739 static void CopySamples(char *dst, char *src, int count, int iChannels,
2740 unsigned fmt)
2741 {
2742
2743 unsigned short *psSrc;
2744 long lAudioSample;
2745
2746 CS_DBGOUT(CS_FUNCTION, 2,
2747 printk(KERN_INFO "cs4281: CopySamples()+ "));
2748 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2749 " dst=0x%x src=0x%x count=%d iChannels=%d fmt=0x%x\n",
2750 (unsigned) dst, (unsigned) src, (unsigned) count,
2751 (unsigned) iChannels, (unsigned) fmt));
2752
2753 // Gershwin does format conversion in hardware so normally
2754 // we don't do any host based coversion. The data formatter
2755 // truncates 16 bit data to 8 bit and that causes some hiss.
2756 // We have already forced the HW to do 16 bit sampling and
2757 // 2 channel so that we can use software to round instead
2758 // of truncate
2759
2760 //
2761 // See if the data should be output as 8-bit unsigned stereo.
2762 // or if the data should be output at 8-bit unsigned mono.
2763 //
2764 if ( ((iChannels == 2) && (fmt & AFMT_U8)) ||
2765 ((iChannels == 1) && (fmt & AFMT_U8)) ) {
2766 //
2767 // Convert each 16-bit unsigned stereo sample to 8-bit unsigned
2768 // stereo using rounding.
2769 //
2770 psSrc = (unsigned short *) src;
2771 count = count / 2;
2772 while (count--) {
2773 lAudioSample = (long) psSrc[count] + (long) 0x80;
2774 if (lAudioSample > 0xffff) {
2775 lAudioSample = 0xffff;
2776 }
2777 dst[count] = (char) (lAudioSample >> 8);
2778 }
2779 }
2780 //
2781 // check for 8-bit signed stereo.
2782 //
2783 else if ((iChannels == 2) && (fmt & AFMT_S8)) {
2784 //
2785 // Convert each 16-bit stereo sample to 8-bit stereo using rounding.
2786 //
2787 psSrc = (short *) src;
2788 while (count--) {
2789 lAudioSample =
2790 (((long) psSrc[0] + (long) psSrc[1]) / 2);
2791 psSrc += 2;
2792 *dst++ = (char) ((short) lAudioSample >> 8);
2793 }
2794 }
2795 //
2796 // Otherwise, the data should be output as 8-bit signed mono.
2797 //
2798 else if ((iChannels == 1) && (fmt & AFMT_S8)) {
2799 //
2800 // Convert each 16-bit signed mono sample to 8-bit signed mono
2801 // using rounding.
2802 //
2803 psSrc = (short *) src;
2804 count = count / 2;
2805 while (count--) {
2806 lAudioSample =
2807 (((long) psSrc[0] + (long) psSrc[1]) / 2);
2808 if (lAudioSample > 0x7fff) {
2809 lAudioSample = 0x7fff;
2810 }
2811 psSrc += 2;
2812 *dst++ = (char) ((short) lAudioSample >> 8);
2813 }
2814 }
2815 }
2816
2817 //
2818 // cs_copy_to_user()
2819 // replacement for the standard copy_to_user, to allow for a conversion from
2820 // 16 bit to 8 bit if the record conversion is active. the cs4281 has some
2821 // issues with 8 bit capture, so the driver always captures data in 16 bit
2822 // and then if the user requested 8 bit, converts from 16 to 8 bit.
2823 //
2824 static unsigned cs_copy_to_user(struct cs4281_state *s, void *dest,
2825 unsigned *hwsrc, unsigned cnt,
2826 unsigned *copied)
2827 {
2828 void *src = hwsrc; //default to the standard destination buffer addr
2829
2830 CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO
2831 "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=0x%.8x\n",
2832 s->prop_adc.fmt, s->prop_adc.fmt_original,
2833 (unsigned) cnt, (unsigned) dest));
2834
2835 if (cnt > s->dma_adc.dmasize) {
2836 cnt = s->dma_adc.dmasize;
2837 }
2838 if (!cnt) {
2839 *copied = 0;
2840 return 0;
2841 }
2842 if (s->conversion) {
2843 if (!s->tmpbuff) {
2844 *copied = cnt / 2;
2845 return 0;
2846 }
2847 CopySamples(s->tmpbuff, (void *) hwsrc, cnt,
2848 (unsigned) s->prop_adc.channels,
2849 s->prop_adc.fmt_original);
2850 src = s->tmpbuff;
2851 cnt = cnt / 2;
2852 }
2853
2854 if (copy_to_user(dest, src, cnt)) {
2855 *copied = 0;
2856 return -EFAULT;
2857 }
2858 *copied = cnt;
2859 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2860 "cs4281: cs_copy_to_user()- copied bytes is %d \n", cnt));
2861 return 0;
2862 }
2863
2864 // ---------------------------------------------------------------------
2865
2866 static ssize_t cs4281_read(struct file *file, char *buffer, size_t count,
2867 loff_t * ppos)
2868 {
2869 struct cs4281_state *s =
2870 (struct cs4281_state *) file->private_data;
2871 ssize_t ret;
2872 unsigned long flags;
2873 unsigned swptr;
2874 int cnt;
2875 unsigned copied = 0;
2876
2877 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2878 printk(KERN_INFO "cs4281: cs4281_read()+ %d \n", count));
2879
2880 VALIDATE_STATE(s);
2881 if (ppos != &file->f_pos)
2882 return -ESPIPE;
2883 if (s->dma_adc.mapped)
2884 return -ENXIO;
2885 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
2886 return ret;
2887 if (!access_ok(VERIFY_WRITE, buffer, count))
2888 return -EFAULT;
2889 ret = 0;
2890 //
2891 // "count" is the amount of bytes to read (from app), is decremented each loop
2892 // by the amount of bytes that have been returned to the user buffer.
2893 // "cnt" is the running total of each read from the buffer (changes each loop)
2894 // "buffer" points to the app's buffer
2895 // "ret" keeps a running total of the amount of bytes that have been copied
2896 // to the user buffer.
2897 // "copied" is the total bytes copied into the user buffer for each loop.
2898 //
2899 while (count > 0) {
2900 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2901 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
2902 count, s->dma_adc.count,
2903 s->dma_adc.swptr, s->dma_adc.hwptr));
2904 spin_lock_irqsave(&s->lock, flags);
2905
2906 // get the current copy point of the sw buffer
2907 swptr = s->dma_adc.swptr;
2908
2909 // cnt is the amount of unread bytes from the end of the
2910 // hw buffer to the current sw pointer
2911 cnt = s->dma_adc.dmasize - swptr;
2912
2913 // dma_adc.count is the current total bytes that have not been read.
2914 // if the amount of unread bytes from the current sw pointer to the
2915 // end of the buffer is greater than the current total bytes that
2916 // have not been read, then set the "cnt" (unread bytes) to the
2917 // amount of unread bytes.
2918
2919 if (s->dma_adc.count < cnt)
2920 cnt = s->dma_adc.count;
2921 spin_unlock_irqrestore(&s->lock, flags);
2922 //
2923 // if we are converting from 8/16 then we need to copy
2924 // twice the number of 16 bit bytes then 8 bit bytes.
2925 //
2926 if (s->conversion) {
2927 if (cnt > (count * 2))
2928 cnt = (count * 2);
2929 } else {
2930 if (cnt > count)
2931 cnt = count;
2932 }
2933 //
2934 // "cnt" NOW is the smaller of the amount that will be read,
2935 // and the amount that is requested in this read (or partial).
2936 // if there are no bytes in the buffer to read, then start the
2937 // ADC and wait for the interrupt handler to wake us up.
2938 //
2939 if (cnt <= 0) {
2940
2941 // start up the dma engine and then continue back to the top of
2942 // the loop when wake up occurs.
2943 start_adc(s);
2944 if (file->f_flags & O_NONBLOCK)
2945 return ret ? ret : -EAGAIN;
2946 interruptible_sleep_on(&s->dma_adc.wait);
2947 if (signal_pending(current))
2948 return ret ? ret : -ERESTARTSYS;
2949 continue;
2950 }
2951 // there are bytes in the buffer to read.
2952 // copy from the hw buffer over to the user buffer.
2953 // user buffer is designated by "buffer"
2954 // virtual address to copy from is rawbuf+swptr
2955 // the "cnt" is the number of bytes to read.
2956
2957 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
2958 "_read() copy_to cnt=%d count=%d ", cnt, count));
2959 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2960 " .dmasize=%d .count=%d buffer=0x%.8x ret=%d\n",
2961 s->dma_adc.dmasize, s->dma_adc.count,
2962 (unsigned) buffer, ret));
2963
2964 if (cs_copy_to_user
2965 (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied))
2966 return ret ? ret : -EFAULT;
2967 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2968 spin_lock_irqsave(&s->lock, flags);
2969 s->dma_adc.swptr = swptr;
2970 s->dma_adc.count -= cnt;
2971 spin_unlock_irqrestore(&s->lock, flags);
2972 count -= copied;
2973 buffer += copied;
2974 ret += copied;
2975 start_adc(s);
2976 }
2977 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2978 printk(KERN_INFO "cs4281: cs4281_read()- %d\n", ret));
2979 return ret;
2980 }
2981
2982
2983 static ssize_t cs4281_write(struct file *file, const char *buffer,
2984 size_t count, loff_t * ppos)
2985 {
2986 struct cs4281_state *s =
2987 (struct cs4281_state *) file->private_data;
2988 ssize_t ret;
2989 unsigned long flags;
2990 unsigned swptr, hwptr, busaddr;
2991 int cnt;
2992
2993 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
2994 printk(KERN_INFO "cs4281: cs4281_write()+ count=%d\n",
2995 count));
2996 VALIDATE_STATE(s);
2997
2998 if (ppos != &file->f_pos)
2999 return -ESPIPE;
3000 if (s->dma_dac.mapped)
3001 return -ENXIO;
3002 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
3003 return ret;
3004 if (!access_ok(VERIFY_READ, buffer, count))
3005 return -EFAULT;
3006 ret = 0;
3007 while (count > 0) {
3008 spin_lock_irqsave(&s->lock, flags);
3009 if (s->dma_dac.count < 0) {
3010 s->dma_dac.count = 0;
3011 s->dma_dac.swptr = s->dma_dac.hwptr;
3012 }
3013 if (s->dma_dac.underrun) {
3014 s->dma_dac.underrun = 0;
3015 hwptr = readl(s->pBA0 + BA0_DCA0);
3016 busaddr = virt_to_bus(s->dma_dac.rawbuf);
3017 hwptr -= (unsigned) busaddr;
3018 s->dma_dac.swptr = s->dma_dac.hwptr = hwptr;
3019 }
3020 swptr = s->dma_dac.swptr;
3021 cnt = s->dma_dac.dmasize - swptr;
3022 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
3023 cnt = s->dma_dac.dmasize - s->dma_dac.count;
3024 spin_unlock_irqrestore(&s->lock, flags);
3025 if (cnt > count)
3026 cnt = count;
3027 if (cnt <= 0) {
3028 start_dac(s);
3029 if (file->f_flags & O_NONBLOCK)
3030 return ret ? ret : -EAGAIN;
3031 interruptible_sleep_on(&s->dma_dac.wait);
3032 if (signal_pending(current))
3033 return ret ? ret : -ERESTARTSYS;
3034 continue;
3035 }
3036 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt))
3037 return ret ? ret : -EFAULT;
3038 swptr = (swptr + cnt) % s->dma_dac.dmasize;
3039 spin_lock_irqsave(&s->lock, flags);
3040 s->dma_dac.swptr = swptr;
3041 s->dma_dac.count += cnt;
3042 s->dma_dac.endcleared = 0;
3043 spin_unlock_irqrestore(&s->lock, flags);
3044 count -= cnt;
3045 buffer += cnt;
3046 ret += cnt;
3047 start_dac(s);
3048 }
3049 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
3050 printk(KERN_INFO "cs4281: cs4281_write()- %d\n", ret));
3051 return ret;
3052 }
3053
3054
3055 static unsigned int cs4281_poll(struct file *file,
3056 struct poll_table_struct *wait)
3057 {
3058 struct cs4281_state *s =
3059 (struct cs4281_state *) file->private_data;
3060 unsigned long flags;
3061 unsigned int mask = 0;
3062
3063 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3064 printk(KERN_INFO "cs4281: cs4281_poll()+\n"));
3065 VALIDATE_STATE(s);
3066 if (file->f_mode & FMODE_WRITE) {
3067 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3068 printk(KERN_INFO
3069 "cs4281: cs4281_poll() wait on FMODE_WRITE\n"));
3070 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3071 return 0;
3072 poll_wait(file, &s->dma_dac.wait, wait);
3073 }
3074 if (file->f_mode & FMODE_READ) {
3075 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3076 printk(KERN_INFO
3077 "cs4281: cs4281_poll() wait on FMODE_READ\n"));
3078 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
3079 return 0;
3080 poll_wait(file, &s->dma_adc.wait, wait);
3081 }
3082 spin_lock_irqsave(&s->lock, flags);
3083 cs4281_update_ptr(s,CS_FALSE);
3084 if (file->f_mode & FMODE_WRITE) {
3085 if (s->dma_dac.mapped) {
3086 if (s->dma_dac.count >=
3087 (signed) s->dma_dac.fragsize) {
3088 if (s->dma_dac.wakeup)
3089 mask |= POLLOUT | POLLWRNORM;
3090 else
3091 mask = 0;
3092 s->dma_dac.wakeup = 0;
3093 }
3094 } else {
3095 if ((signed) (s->dma_dac.dmasize/2) >= s->dma_dac.count)
3096 mask |= POLLOUT | POLLWRNORM;
3097 }
3098 } else if (file->f_mode & FMODE_READ) {
3099 if (s->dma_adc.mapped) {
3100 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
3101 mask |= POLLIN | POLLRDNORM;
3102 } else {
3103 if (s->dma_adc.count > 0)
3104 mask |= POLLIN | POLLRDNORM;
3105 }
3106 }
3107 spin_unlock_irqrestore(&s->lock, flags);
3108 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3109 printk(KERN_INFO "cs4281: cs4281_poll()- 0x%.8x\n",
3110 mask));
3111 return mask;
3112 }
3113
3114
3115 static int cs4281_mmap(struct file *file, struct vm_area_struct *vma)
3116 {
3117 struct cs4281_state *s =
3118 (struct cs4281_state *) file->private_data;
3119 struct dmabuf *db;
3120 int ret;
3121 unsigned long size;
3122
3123 CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3124 printk(KERN_INFO "cs4281: cs4281_mmap()+\n"));
3125
3126 VALIDATE_STATE(s);
3127 if (vma->vm_flags & VM_WRITE) {
3128 if ((ret = prog_dmabuf_dac(s)) != 0)
3129 return ret;
3130 db = &s->dma_dac;
3131 } else if (vma->vm_flags & VM_READ) {
3132 if ((ret = prog_dmabuf_adc(s)) != 0)
3133 return ret;
3134 db = &s->dma_adc;
3135 } else
3136 return -EINVAL;
3137 //
3138 // only support PLAYBACK for now
3139 //
3140 db = &s->dma_dac;
3141
3142 if (cs4x_pgoff(vma) != 0)
3143 return -EINVAL;
3144 size = vma->vm_end - vma->vm_start;
3145 if (size > (PAGE_SIZE << db->buforder))
3146 return -EINVAL;
3147 if (remap_page_range
3148 (vma->vm_start, virt_to_phys(db->rawbuf), size,
3149 vma->vm_page_prot)) return -EAGAIN;
3150 db->mapped = 1;
3151
3152 CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3153 printk(KERN_INFO "cs4281: cs4281_mmap()- 0 size=%d\n",
3154 (unsigned) size));
3155
3156 return 0;
3157 }
3158
3159
3160 static int cs4281_ioctl(struct inode *inode, struct file *file,
3161 unsigned int cmd, unsigned long arg)
3162 {
3163 struct cs4281_state *s =
3164 (struct cs4281_state *) file->private_data;
3165 unsigned long flags;
3166 audio_buf_info abinfo;
3167 count_info cinfo;
3168 int val, mapped, ret;
3169
3170 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
3171 "cs4281: cs4281_ioctl(): file=0x%.8x cmd=0x%.8x\n",
3172 (unsigned) file, cmd));
3173 #if CSDEBUG
3174 cs_printioctl(cmd);
3175 #endif
3176 VALIDATE_STATE(s);
3177 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
3178 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
3179 switch (cmd) {
3180 case OSS_GETVERSION:
3181 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3182 "cs4281: cs4281_ioctl(): SOUND_VERSION=0x%.8x\n",
3183 SOUND_VERSION));
3184 return put_user(SOUND_VERSION, (int *) arg);
3185
3186 case SNDCTL_DSP_SYNC:
3187 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3188 "cs4281: cs4281_ioctl(): DSP_SYNC\n"));
3189 if (file->f_mode & FMODE_WRITE)
3190 return drain_dac(s,
3191 0 /*file->f_flags & O_NONBLOCK */
3192 );
3193 return 0;
3194
3195 case SNDCTL_DSP_SETDUPLEX:
3196 return 0;
3197
3198 case SNDCTL_DSP_GETCAPS:
3199 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
3200 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
3201 (int *) arg);
3202
3203 case SNDCTL_DSP_RESET:
3204 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3205 "cs4281: cs4281_ioctl(): DSP_RESET\n"));
3206 if (file->f_mode & FMODE_WRITE) {
3207 stop_dac(s);
3208 synchronize_irq();
3209 s->dma_dac.swptr = s->dma_dac.hwptr =
3210 s->dma_dac.count = s->dma_dac.total_bytes =
3211 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
3212 prog_codec(s, CS_TYPE_DAC);
3213 }
3214 if (file->f_mode & FMODE_READ) {
3215 stop_adc(s);
3216 synchronize_irq();
3217 s->dma_adc.swptr = s->dma_adc.hwptr =
3218 s->dma_adc.count = s->dma_adc.total_bytes =
3219 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
3220 prog_codec(s, CS_TYPE_ADC);
3221 }
3222 return 0;
3223
3224 case SNDCTL_DSP_SPEED:
3225 if (get_user(val, (int *) arg))
3226 return -EFAULT;
3227 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3228 "cs4281: cs4281_ioctl(): DSP_SPEED val=%d\n", val));
3229 //
3230 // support independent capture and playback channels
3231 // assume that the file mode bit determines the
3232 // direction of the data flow.
3233 //
3234 if (file->f_mode & FMODE_READ) {
3235 if (val >= 0) {
3236 stop_adc(s);
3237 s->dma_adc.ready = 0;
3238 // program sampling rates
3239 if (val > 48000)
3240 val = 48000;
3241 if (val < 6300)
3242 val = 6300;
3243 s->prop_adc.rate = val;
3244 prog_codec(s, CS_TYPE_ADC);
3245 }
3246 }
3247 if (file->f_mode & FMODE_WRITE) {
3248 if (val >= 0) {
3249 stop_dac(s);
3250 s->dma_dac.ready = 0;
3251 // program sampling rates
3252 if (val > 48000)
3253 val = 48000;
3254 if (val < 6300)
3255 val = 6300;
3256 s->prop_dac.rate = val;
3257 prog_codec(s, CS_TYPE_DAC);
3258 }
3259 }
3260
3261 if (file->f_mode & FMODE_WRITE)
3262 val = s->prop_dac.rate;
3263 else if (file->f_mode & FMODE_READ)
3264 val = s->prop_adc.rate;
3265
3266 return put_user(val, (int *) arg);
3267
3268 case SNDCTL_DSP_STEREO:
3269 if (get_user(val, (int *) arg))
3270 return -EFAULT;
3271 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3272 "cs4281: cs4281_ioctl(): DSP_STEREO val=%d\n", val));
3273 if (file->f_mode & FMODE_READ) {
3274 stop_adc(s);
3275 s->dma_adc.ready = 0;
3276 s->prop_adc.channels = val ? 2 : 1;
3277 prog_codec(s, CS_TYPE_ADC);
3278 }
3279 if (file->f_mode & FMODE_WRITE) {
3280 stop_dac(s);
3281 s->dma_dac.ready = 0;
3282 s->prop_dac.channels = val ? 2 : 1;
3283 prog_codec(s, CS_TYPE_DAC);
3284 }
3285 return 0;
3286
3287 case SNDCTL_DSP_CHANNELS:
3288 if (get_user(val, (int *) arg))
3289 return -EFAULT;
3290 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3291 "cs4281: cs4281_ioctl(): DSP_CHANNELS val=%d\n",
3292 val));
3293 if (val != 0) {
3294 if (file->f_mode & FMODE_READ) {
3295 stop_adc(s);
3296 s->dma_adc.ready = 0;
3297 if (val >= 2)
3298 s->prop_adc.channels = 2;
3299 else
3300 s->prop_adc.channels = 1;
3301 prog_codec(s, CS_TYPE_ADC);
3302 }
3303 if (file->f_mode & FMODE_WRITE) {
3304 stop_dac(s);
3305 s->dma_dac.ready = 0;
3306 if (val >= 2)
3307 s->prop_dac.channels = 2;
3308 else
3309 s->prop_dac.channels = 1;
3310 prog_codec(s, CS_TYPE_DAC);
3311 }
3312 }
3313
3314 if (file->f_mode & FMODE_WRITE)
3315 val = s->prop_dac.channels;
3316 else if (file->f_mode & FMODE_READ)
3317 val = s->prop_adc.channels;
3318
3319 return put_user(val, (int *) arg);
3320
3321 case SNDCTL_DSP_GETFMTS: // Returns a mask
3322 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3323 "cs4281: cs4281_ioctl(): DSP_GETFMT val=0x%.8x\n",
3324 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3325 AFMT_U8));
3326 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3327 AFMT_U8, (int *) arg);
3328
3329 case SNDCTL_DSP_SETFMT:
3330 if (get_user(val, (int *) arg))
3331 return -EFAULT;
3332 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3333 "cs4281: cs4281_ioctl(): DSP_SETFMT val=0x%.8x\n",
3334 val));
3335 if (val != AFMT_QUERY) {
3336 if (file->f_mode & FMODE_READ) {
3337 stop_adc(s);
3338 s->dma_adc.ready = 0;
3339 if (val != AFMT_S16_LE
3340 && val != AFMT_U16_LE && val != AFMT_S8
3341 && val != AFMT_U8)
3342 val = AFMT_U8;
3343 s->prop_adc.fmt = val;
3344 s->prop_adc.fmt_original = s->prop_adc.fmt;
3345 prog_codec(s, CS_TYPE_ADC);
3346 }
3347 if (file->f_mode & FMODE_WRITE) {
3348 stop_dac(s);
3349 s->dma_dac.ready = 0;
3350 if (val != AFMT_S16_LE
3351 && val != AFMT_U16_LE && val != AFMT_S8
3352 && val != AFMT_U8)
3353 val = AFMT_U8;
3354 s->prop_dac.fmt = val;
3355 s->prop_dac.fmt_original = s->prop_dac.fmt;
3356 prog_codec(s, CS_TYPE_DAC);
3357 }
3358 } else {
3359 if (file->f_mode & FMODE_WRITE)
3360 val = s->prop_dac.fmt_original;
3361 else if (file->f_mode & FMODE_READ)
3362 val = s->prop_adc.fmt_original;
3363 }
3364 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3365 "cs4281: cs4281_ioctl(): DSP_SETFMT return val=0x%.8x\n",
3366 val));
3367 return put_user(val, (int *) arg);
3368
3369 case SNDCTL_DSP_POST:
3370 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3371 "cs4281: cs4281_ioctl(): DSP_POST\n"));
3372 return 0;
3373
3374 case SNDCTL_DSP_GETTRIGGER:
3375 val = 0;
3376 if (file->f_mode & s->ena & FMODE_READ)
3377 val |= PCM_ENABLE_INPUT;
3378 if (file->f_mode & s->ena & FMODE_WRITE)
3379 val |= PCM_ENABLE_OUTPUT;
3380 return put_user(val, (int *) arg);
3381
3382 case SNDCTL_DSP_SETTRIGGER:
3383 if (get_user(val, (int *) arg))
3384 return -EFAULT;
3385 if (file->f_mode & FMODE_READ) {
3386 if (val & PCM_ENABLE_INPUT) {
3387 if (!s->dma_adc.ready
3388 && (ret = prog_dmabuf_adc(s)))
3389 return ret;
3390 start_adc(s);
3391 } else
3392 stop_adc(s);
3393 }
3394 if (file->f_mode & FMODE_WRITE) {
3395 if (val & PCM_ENABLE_OUTPUT) {
3396 if (!s->dma_dac.ready
3397 && (ret = prog_dmabuf_dac(s)))
3398 return ret;
3399 start_dac(s);
3400 } else
3401 stop_dac(s);
3402 }
3403 return 0;
3404
3405 case SNDCTL_DSP_GETOSPACE:
3406 if (!(file->f_mode & FMODE_WRITE))
3407 return -EINVAL;
3408 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
3409 return val;
3410 spin_lock_irqsave(&s->lock, flags);
3411 cs4281_update_ptr(s,CS_FALSE);
3412 abinfo.fragsize = s->dma_dac.fragsize;
3413 if (s->dma_dac.mapped)
3414 abinfo.bytes = s->dma_dac.dmasize;
3415 else
3416 abinfo.bytes =
3417 s->dma_dac.dmasize - s->dma_dac.count;
3418 abinfo.fragstotal = s->dma_dac.numfrag;
3419 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
3420 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
3421 "cs4281: cs4281_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
3422 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
3423 abinfo.fragments));
3424 spin_unlock_irqrestore(&s->lock, flags);
3425 return copy_to_user((void *) arg, &abinfo,
3426 sizeof(abinfo)) ? -EFAULT : 0;
3427
3428 case SNDCTL_DSP_GETISPACE:
3429 if (!(file->f_mode & FMODE_READ))
3430 return -EINVAL;
3431 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
3432 return val;
3433 spin_lock_irqsave(&s->lock, flags);
3434 cs4281_update_ptr(s,CS_FALSE);
3435 if (s->conversion) {
3436 abinfo.fragsize = s->dma_adc.fragsize / 2;
3437 abinfo.bytes = s->dma_adc.count / 2;
3438 abinfo.fragstotal = s->dma_adc.numfrag;
3439 abinfo.fragments =
3440 abinfo.bytes >> (s->dma_adc.fragshift - 1);
3441 } else {
3442 abinfo.fragsize = s->dma_adc.fragsize;
3443 abinfo.bytes = s->dma_adc.count;
3444 abinfo.fragstotal = s->dma_adc.numfrag;
3445 abinfo.fragments =
3446 abinfo.bytes >> s->dma_adc.fragshift;
3447 }
3448 spin_unlock_irqrestore(&s->lock, flags);
3449 return copy_to_user((void *) arg, &abinfo,
3450 sizeof(abinfo)) ? -EFAULT : 0;
3451
3452 case SNDCTL_DSP_NONBLOCK:
3453 file->f_flags |= O_NONBLOCK;
3454 return 0;
3455
3456 case SNDCTL_DSP_GETODELAY:
3457 if (!(file->f_mode & FMODE_WRITE))
3458 return -EINVAL;
3459 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3460 return 0;
3461 spin_lock_irqsave(&s->lock, flags);
3462 cs4281_update_ptr(s,CS_FALSE);
3463 val = s->dma_dac.count;
3464 spin_unlock_irqrestore(&s->lock, flags);
3465 return put_user(val, (int *) arg);
3466
3467 case SNDCTL_DSP_GETIPTR:
3468 if (!(file->f_mode & FMODE_READ))
3469 return -EINVAL;
3470 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
3471 return 0;
3472 spin_lock_irqsave(&s->lock, flags);
3473 cs4281_update_ptr(s,CS_FALSE);
3474 cinfo.bytes = s->dma_adc.total_bytes;
3475 if (s->dma_adc.mapped) {
3476 cinfo.blocks =
3477 (cinfo.bytes >> s->dma_adc.fragshift) -
3478 s->dma_adc.blocks;
3479 s->dma_adc.blocks =
3480 cinfo.bytes >> s->dma_adc.fragshift;
3481 } else {
3482 if (s->conversion) {
3483 cinfo.blocks =
3484 s->dma_adc.count /
3485 2 >> (s->dma_adc.fragshift - 1);
3486 } else
3487 cinfo.blocks =
3488 s->dma_adc.count >> s->dma_adc.
3489 fragshift;
3490 }
3491 if (s->conversion)
3492 cinfo.ptr = s->dma_adc.hwptr / 2;
3493 else
3494 cinfo.ptr = s->dma_adc.hwptr;
3495 if (s->dma_adc.mapped)
3496 s->dma_adc.count &= s->dma_adc.fragsize - 1;
3497 spin_unlock_irqrestore(&s->lock, flags);
3498 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
3499
3500 case SNDCTL_DSP_GETOPTR:
3501 if (!(file->f_mode & FMODE_WRITE))
3502 return -EINVAL;
3503 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3504 return 0;
3505 spin_lock_irqsave(&s->lock, flags);
3506 cs4281_update_ptr(s,CS_FALSE);
3507 cinfo.bytes = s->dma_dac.total_bytes;
3508 if (s->dma_dac.mapped) {
3509 cinfo.blocks =
3510 (cinfo.bytes >> s->dma_dac.fragshift) -
3511 s->dma_dac.blocks;
3512 s->dma_dac.blocks =
3513 cinfo.bytes >> s->dma_dac.fragshift;
3514 } else {
3515 cinfo.blocks =
3516 s->dma_dac.count >> s->dma_dac.fragshift;
3517 }
3518 cinfo.ptr = s->dma_dac.hwptr;
3519 if (s->dma_dac.mapped)
3520 s->dma_dac.count &= s->dma_dac.fragsize - 1;
3521 spin_unlock_irqrestore(&s->lock, flags);
3522 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
3523
3524 case SNDCTL_DSP_GETBLKSIZE:
3525 if (file->f_mode & FMODE_WRITE) {
3526 if ((val = prog_dmabuf_dac(s)))
3527 return val;
3528 return put_user(s->dma_dac.fragsize, (int *) arg);
3529 }
3530 if ((val = prog_dmabuf_adc(s)))
3531 return val;
3532 if (s->conversion)
3533 return put_user(s->dma_adc.fragsize / 2,
3534 (int *) arg);
3535 else
3536 return put_user(s->dma_adc.fragsize, (int *) arg);
3537
3538 case SNDCTL_DSP_SETFRAGMENT:
3539 if (get_user(val, (int *) arg))
3540 return -EFAULT;
3541 return 0; // Say OK, but do nothing.
3542
3543 case SNDCTL_DSP_SUBDIVIDE:
3544 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
3545 || (file->f_mode & FMODE_WRITE
3546 && s->dma_dac.subdivision)) return -EINVAL;
3547 if (get_user(val, (int *) arg))
3548 return -EFAULT;
3549 if (val != 1 && val != 2 && val != 4)
3550 return -EINVAL;
3551 if (file->f_mode & FMODE_READ)
3552 s->dma_adc.subdivision = val;
3553 else if (file->f_mode & FMODE_WRITE)
3554 s->dma_dac.subdivision = val;
3555 return 0;
3556
3557 case SOUND_PCM_READ_RATE:
3558 if (file->f_mode & FMODE_READ)
3559 return put_user(s->prop_adc.rate, (int *) arg);
3560 else if (file->f_mode & FMODE_WRITE)
3561 return put_user(s->prop_dac.rate, (int *) arg);
3562
3563 case SOUND_PCM_READ_CHANNELS:
3564 if (file->f_mode & FMODE_READ)
3565 return put_user(s->prop_adc.channels, (int *) arg);
3566 else if (file->f_mode & FMODE_WRITE)
3567 return put_user(s->prop_dac.channels, (int *) arg);
3568
3569 case SOUND_PCM_READ_BITS:
3570 if (file->f_mode & FMODE_READ)
3571 return
3572 put_user(
3573 (s->prop_adc.
3574 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3575 (int *) arg);
3576 else if (file->f_mode & FMODE_WRITE)
3577 return
3578 put_user(
3579 (s->prop_dac.
3580 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3581 (int *) arg);
3582
3583 case SOUND_PCM_WRITE_FILTER:
3584 case SNDCTL_DSP_SETSYNCRO:
3585 case SOUND_PCM_READ_FILTER:
3586 return -EINVAL;
3587 }
3588 return mixer_ioctl(s, cmd, arg);
3589 }
3590
3591
3592 static int cs4281_release(struct inode *inode, struct file *file)
3593 {
3594 struct cs4281_state *s =
3595 (struct cs4281_state *) file->private_data;
3596
3597 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
3598 "cs4281: cs4281_release(): inode=0x%.8x file=0x%.8x f_mode=%d\n",
3599 (unsigned) inode, (unsigned) file, file->f_mode));
3600
3601 VALIDATE_STATE(s);
3602
3603 if (file->f_mode & FMODE_WRITE) {
3604 drain_dac(s, file->f_flags & O_NONBLOCK);
3605 down(&s->open_sem_dac);
3606 stop_dac(s);
3607 dealloc_dmabuf(s, &s->dma_dac);
3608 s->open_mode &= ~FMODE_WRITE;
3609 up(&s->open_sem_dac);
3610 wake_up(&s->open_wait_dac);
3611 MOD_DEC_USE_COUNT;
3612 }
3613 if (file->f_mode & FMODE_READ) {
3614 drain_adc(s, file->f_flags & O_NONBLOCK);
3615 down(&s->open_sem_adc);
3616 stop_adc(s);
3617 dealloc_dmabuf(s, &s->dma_adc);
3618 s->open_mode &= ~FMODE_READ;
3619 up(&s->open_sem_adc);
3620 wake_up(&s->open_wait_adc);
3621 MOD_DEC_USE_COUNT;
3622 }
3623 return 0;
3624 }
3625
3626 static int cs4281_open(struct inode *inode, struct file *file)
3627 {
3628 int minor = MINOR(inode->i_rdev);
3629 struct cs4281_state *s=NULL;
3630 struct list_head *entry;
3631
3632 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3633 "cs4281: cs4281_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
3634 (unsigned) inode, (unsigned) file, file->f_mode));
3635
3636 list_for_each(entry, &cs4281_devs)
3637 {
3638 s = list_entry(entry, struct cs4281_state, list);
3639
3640 if (!((s->dev_audio ^ minor) & ~0xf))
3641 break;
3642 }
3643 if (entry == &cs4281_devs)
3644 return -ENODEV;
3645 if (!s) {
3646 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3647 "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3648 return -ENODEV;
3649 }
3650 VALIDATE_STATE(s);
3651 file->private_data = s;
3652
3653 // wait for device to become free
3654 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
3655 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
3656 "cs4281: cs4281_open(): Error - must open READ and/or WRITE\n"));
3657 return -ENODEV;
3658 }
3659 if (file->f_mode & FMODE_WRITE) {
3660 down(&s->open_sem_dac);
3661 while (s->open_mode & FMODE_WRITE) {
3662 if (file->f_flags & O_NONBLOCK) {
3663 up(&s->open_sem_dac);
3664 return -EBUSY;
3665 }
3666 up(&s->open_sem_dac);
3667 interruptible_sleep_on(&s->open_wait_dac);
3668
3669 if (signal_pending(current))
3670 return -ERESTARTSYS;
3671 down(&s->open_sem_dac);
3672 }
3673 }
3674 if (file->f_mode & FMODE_READ) {
3675 down(&s->open_sem_adc);
3676 while (s->open_mode & FMODE_READ) {
3677 if (file->f_flags & O_NONBLOCK) {
3678 up(&s->open_sem_adc);
3679 return -EBUSY;
3680 }
3681 up(&s->open_sem_adc);
3682 interruptible_sleep_on(&s->open_wait_adc);
3683
3684 if (signal_pending(current))
3685 return -ERESTARTSYS;
3686 down(&s->open_sem_adc);
3687 }
3688 }
3689 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
3690 if (file->f_mode & FMODE_READ) {
3691 s->prop_adc.fmt = AFMT_U8;
3692 s->prop_adc.fmt_original = s->prop_adc.fmt;
3693 s->prop_adc.channels = 1;
3694 s->prop_adc.rate = 8000;
3695 s->prop_adc.clkdiv = 96 | 0x80;
3696 s->conversion = 0;
3697 s->ena &= ~FMODE_READ;
3698 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
3699 s->dma_adc.subdivision = 0;
3700 up(&s->open_sem_adc);
3701 MOD_INC_USE_COUNT;
3702
3703 if (prog_dmabuf_adc(s)) {
3704 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3705 "cs4281: adc Program dmabufs failed.\n"));
3706 cs4281_release(inode, file);
3707 return -ENOMEM;
3708 }
3709 prog_codec(s, CS_TYPE_ADC);
3710 }
3711 if (file->f_mode & FMODE_WRITE) {
3712 s->prop_dac.fmt = AFMT_U8;
3713 s->prop_dac.fmt_original = s->prop_dac.fmt;
3714 s->prop_dac.channels = 1;
3715 s->prop_dac.rate = 8000;
3716 s->prop_dac.clkdiv = 96 | 0x80;
3717 s->conversion = 0;
3718 s->ena &= ~FMODE_WRITE;
3719 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
3720 s->dma_dac.subdivision = 0;
3721 up(&s->open_sem_dac);
3722 MOD_INC_USE_COUNT;
3723
3724 if (prog_dmabuf_dac(s)) {
3725 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3726 "cs4281: dac Program dmabufs failed.\n"));
3727 cs4281_release(inode, file);
3728 return -ENOMEM;
3729 }
3730 prog_codec(s, CS_TYPE_DAC);
3731 }
3732 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
3733 printk(KERN_INFO "cs4281: cs4281_open()- 0\n"));
3734 return 0;
3735 }
3736
3737
3738 // ******************************************************************************************
3739 // Wave (audio) file operations struct.
3740 // ******************************************************************************************
3741 static /*const */ struct file_operations cs4281_audio_fops = {
3742 llseek:no_llseek,
3743 read:cs4281_read,
3744 write:cs4281_write,
3745 poll:cs4281_poll,
3746 ioctl:cs4281_ioctl,
3747 mmap:cs4281_mmap,
3748 open:cs4281_open,
3749 release:cs4281_release,
3750 };
3751
3752 // ---------------------------------------------------------------------
3753
3754 // hold spinlock for the following!
3755 static void cs4281_handle_midi(struct cs4281_state *s)
3756 {
3757 unsigned char ch;
3758 int wake;
3759 unsigned temp1;
3760
3761 wake = 0;
3762 while (!(readl(s->pBA0 + BA0_MIDSR) & 0x80)) {
3763 ch = readl(s->pBA0 + BA0_MIDRP);
3764 if (s->midi.icnt < MIDIINBUF) {
3765 s->midi.ibuf[s->midi.iwr] = ch;
3766 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
3767 s->midi.icnt++;
3768 }
3769 wake = 1;
3770 }
3771 if (wake)
3772 wake_up(&s->midi.iwait);
3773 wake = 0;
3774 while (!(readl(s->pBA0 + BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) {
3775 temp1 = (s->midi.obuf[s->midi.ord]) & 0x000000ff;
3776 writel(temp1, s->pBA0 + BA0_MIDWP);
3777 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
3778 s->midi.ocnt--;
3779 if (s->midi.ocnt < MIDIOUTBUF - 16)
3780 wake = 1;
3781 }
3782 if (wake)
3783 wake_up(&s->midi.owait);
3784 }
3785
3786
3787
3788 static void cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3789 {
3790 struct cs4281_state *s = (struct cs4281_state *) dev_id;
3791 unsigned int temp1;
3792
3793 // fastpath out, to ease interrupt sharing
3794 temp1 = readl(s->pBA0 + BA0_HISR); // Get Int Status reg.
3795
3796 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
3797 "cs4281: cs4281_interrupt() BA0_HISR=0x%.8x\n", temp1));
3798 /*
3799 * If not DMA or MIDI interrupt, then just return.
3800 */
3801 if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) {
3802 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
3803 CS_DBGOUT(CS_INTERRUPT, 9, printk(KERN_INFO
3804 "cs4281: cs4281_interrupt(): returning not cs4281 interrupt.\n"));
3805 return;
3806 }
3807
3808 if (temp1 & HISR_DMA0) // If play interrupt,
3809 readl(s->pBA0 + BA0_HDSR0); // clear the source.
3810
3811 if (temp1 & HISR_DMA1) // Same for play.
3812 readl(s->pBA0 + BA0_HDSR1);
3813 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Local EOI
3814
3815 spin_lock(&s->lock);
3816 cs4281_update_ptr(s,CS_TRUE);
3817 cs4281_handle_midi(s);
3818 spin_unlock(&s->lock);
3819 }
3820
3821 // **************************************************************************
3822
3823 static void cs4281_midi_timer(unsigned long data)
3824 {
3825 struct cs4281_state *s = (struct cs4281_state *) data;
3826 unsigned long flags;
3827
3828 spin_lock_irqsave(&s->lock, flags);
3829 cs4281_handle_midi(s);
3830 spin_unlock_irqrestore(&s->lock, flags);
3831 s->midi.timer.expires = jiffies + 1;
3832 add_timer(&s->midi.timer);
3833 }
3834
3835
3836 // ---------------------------------------------------------------------
3837
3838 static ssize_t cs4281_midi_read(struct file *file, char *buffer,
3839 size_t count, loff_t * ppos)
3840 {
3841 struct cs4281_state *s =
3842 (struct cs4281_state *) file->private_data;
3843 ssize_t ret;
3844 unsigned long flags;
3845 unsigned ptr;
3846 int cnt;
3847
3848 VALIDATE_STATE(s);
3849 if (ppos != &file->f_pos)
3850 return -ESPIPE;
3851 if (!access_ok(VERIFY_WRITE, buffer, count))
3852 return -EFAULT;
3853 ret = 0;
3854 while (count > 0) {
3855 spin_lock_irqsave(&s->lock, flags);
3856 ptr = s->midi.ird;
3857 cnt = MIDIINBUF - ptr;
3858 if (s->midi.icnt < cnt)
3859 cnt = s->midi.icnt;
3860 spin_unlock_irqrestore(&s->lock, flags);
3861 if (cnt > count)
3862 cnt = count;
3863 if (cnt <= 0) {
3864 if (file->f_flags & O_NONBLOCK)
3865 return ret ? ret : -EAGAIN;
3866 interruptible_sleep_on(&s->midi.iwait);
3867 if (signal_pending(current))
3868 return ret ? ret : -ERESTARTSYS;
3869 continue;
3870 }
3871 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt))
3872 return ret ? ret : -EFAULT;
3873 ptr = (ptr + cnt) % MIDIINBUF;
3874 spin_lock_irqsave(&s->lock, flags);
3875 s->midi.ird = ptr;
3876 s->midi.icnt -= cnt;
3877 spin_unlock_irqrestore(&s->lock, flags);
3878 count -= cnt;
3879 buffer += cnt;
3880 ret += cnt;
3881 }
3882 return ret;
3883 }
3884
3885
3886 static ssize_t cs4281_midi_write(struct file *file, const char *buffer,
3887 size_t count, loff_t * ppos)
3888 {
3889 struct cs4281_state *s =
3890 (struct cs4281_state *) file->private_data;
3891 ssize_t ret;
3892 unsigned long flags;
3893 unsigned ptr;
3894 int cnt;
3895
3896 VALIDATE_STATE(s);
3897 if (ppos != &file->f_pos)
3898 return -ESPIPE;
3899 if (!access_ok(VERIFY_READ, buffer, count))
3900 return -EFAULT;
3901 ret = 0;
3902 while (count > 0) {
3903 spin_lock_irqsave(&s->lock, flags);
3904 ptr = s->midi.owr;
3905 cnt = MIDIOUTBUF - ptr;
3906 if (s->midi.ocnt + cnt > MIDIOUTBUF)
3907 cnt = MIDIOUTBUF - s->midi.ocnt;
3908 if (cnt <= 0)
3909 cs4281_handle_midi(s);
3910 spin_unlock_irqrestore(&s->lock, flags);
3911 if (cnt > count)
3912 cnt = count;
3913 if (cnt <= 0) {
3914 if (file->f_flags & O_NONBLOCK)
3915 return ret ? ret : -EAGAIN;
3916 interruptible_sleep_on(&s->midi.owait);
3917 if (signal_pending(current))
3918 return ret ? ret : -ERESTARTSYS;
3919 continue;
3920 }
3921 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt))
3922 return ret ? ret : -EFAULT;
3923 ptr = (ptr + cnt) % MIDIOUTBUF;
3924 spin_lock_irqsave(&s->lock, flags);
3925 s->midi.owr = ptr;
3926 s->midi.ocnt += cnt;
3927 spin_unlock_irqrestore(&s->lock, flags);
3928 count -= cnt;
3929 buffer += cnt;
3930 ret += cnt;
3931 spin_lock_irqsave(&s->lock, flags);
3932 cs4281_handle_midi(s);
3933 spin_unlock_irqrestore(&s->lock, flags);
3934 }
3935 return ret;
3936 }
3937
3938
3939 static unsigned int cs4281_midi_poll(struct file *file,
3940 struct poll_table_struct *wait)
3941 {
3942 struct cs4281_state *s =
3943 (struct cs4281_state *) file->private_data;
3944 unsigned long flags;
3945 unsigned int mask = 0;
3946
3947 VALIDATE_STATE(s);
3948 if (file->f_flags & FMODE_WRITE)
3949 poll_wait(file, &s->midi.owait, wait);
3950 if (file->f_flags & FMODE_READ)
3951 poll_wait(file, &s->midi.iwait, wait);
3952 spin_lock_irqsave(&s->lock, flags);
3953 if (file->f_flags & FMODE_READ) {
3954 if (s->midi.icnt > 0)
3955 mask |= POLLIN | POLLRDNORM;
3956 }
3957 if (file->f_flags & FMODE_WRITE) {
3958 if (s->midi.ocnt < MIDIOUTBUF)
3959 mask |= POLLOUT | POLLWRNORM;
3960 }
3961 spin_unlock_irqrestore(&s->lock, flags);
3962 return mask;
3963 }
3964
3965
3966 static int cs4281_midi_open(struct inode *inode, struct file *file)
3967 {
3968 unsigned long flags, temp1;
3969 int minor = MINOR(inode->i_rdev);
3970 struct cs4281_state *s=NULL;
3971 struct list_head *entry;
3972 list_for_each(entry, &cs4281_devs)
3973 {
3974 s = list_entry(entry, struct cs4281_state, list);
3975
3976 if (s->dev_midi == minor)
3977 break;
3978 }
3979
3980 if (entry == &cs4281_devs)
3981 return -ENODEV;
3982 if (!s)
3983 {
3984 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3985 "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3986 return -ENODEV;
3987 }
3988 VALIDATE_STATE(s);
3989 file->private_data = s;
3990 // wait for device to become free
3991 down(&s->open_sem);
3992 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
3993 if (file->f_flags & O_NONBLOCK) {
3994 up(&s->open_sem);
3995 return -EBUSY;
3996 }
3997 up(&s->open_sem);
3998 interruptible_sleep_on(&s->open_wait);
3999 if (signal_pending(current))
4000 return -ERESTARTSYS;
4001 down(&s->open_sem);
4002 }
4003 spin_lock_irqsave(&s->lock, flags);
4004 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4005 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4006 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4007 writel(1, s->pBA0 + BA0_MIDCR); // Reset the interface.
4008 writel(0, s->pBA0 + BA0_MIDCR); // Return to normal mode.
4009 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4010 writel(0x0000000f, s->pBA0 + BA0_MIDCR); // Enable transmit, record, ints.
4011 temp1 = readl(s->pBA0 + BA0_HIMR);
4012 writel(temp1 & 0xffbfffff, s->pBA0 + BA0_HIMR); // Enable midi int. recognition.
4013 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts
4014 init_timer(&s->midi.timer);
4015 s->midi.timer.expires = jiffies + 1;
4016 s->midi.timer.data = (unsigned long) s;
4017 s->midi.timer.function = cs4281_midi_timer;
4018 add_timer(&s->midi.timer);
4019 }
4020 if (file->f_mode & FMODE_READ) {
4021 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4022 }
4023 if (file->f_mode & FMODE_WRITE) {
4024 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4025 }
4026 spin_unlock_irqrestore(&s->lock, flags);
4027 s->open_mode |=
4028 (file->
4029 f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ |
4030 FMODE_MIDI_WRITE);
4031 up(&s->open_sem);
4032 MOD_INC_USE_COUNT;
4033 return 0;
4034 }
4035
4036
4037 static int cs4281_midi_release(struct inode *inode, struct file *file)
4038 {
4039 struct cs4281_state *s =
4040 (struct cs4281_state *) file->private_data;
4041 DECLARE_WAITQUEUE(wait, current);
4042 unsigned long flags;
4043 unsigned count, tmo;
4044
4045 VALIDATE_STATE(s);
4046
4047 if (file->f_mode & FMODE_WRITE) {
4048 add_wait_queue(&s->midi.owait, &wait);
4049 for (;;) {
4050 set_current_state(TASK_INTERRUPTIBLE);
4051 spin_lock_irqsave(&s->lock, flags);
4052 count = s->midi.ocnt;
4053 spin_unlock_irqrestore(&s->lock, flags);
4054 if (count <= 0)
4055 break;
4056 if (signal_pending(current))
4057 break;
4058 if (file->f_flags & O_NONBLOCK) {
4059 remove_wait_queue(&s->midi.owait, &wait);
4060 current->state = TASK_RUNNING;
4061 return -EBUSY;
4062 }
4063 tmo = (count * HZ) / 3100;
4064 if (!schedule_timeout(tmo ? : 1) && tmo)
4065 printk(KERN_DEBUG
4066 "cs4281: midi timed out??\n");
4067 }
4068 remove_wait_queue(&s->midi.owait, &wait);
4069 current->state = TASK_RUNNING;
4070 }
4071 down(&s->open_sem);
4072 s->open_mode &=
4073 (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ |
4074 FMODE_MIDI_WRITE);
4075 spin_lock_irqsave(&s->lock, flags);
4076 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4077 writel(0, s->pBA0 + BA0_MIDCR); // Disable Midi interrupts.
4078 del_timer(&s->midi.timer);
4079 }
4080 spin_unlock_irqrestore(&s->lock, flags);
4081 up(&s->open_sem);
4082 wake_up(&s->open_wait);
4083 MOD_DEC_USE_COUNT;
4084 return 0;
4085 }
4086
4087 // ******************************************************************************************
4088 // Midi file operations struct.
4089 // ******************************************************************************************
4090 static /*const */ struct file_operations cs4281_midi_fops = {
4091 llseek:no_llseek,
4092 read:cs4281_midi_read,
4093 write:cs4281_midi_write,
4094 poll:cs4281_midi_poll,
4095 open:cs4281_midi_open,
4096 release:cs4281_midi_release,
4097 };
4098
4099
4100 // ---------------------------------------------------------------------
4101
4102 // maximum number of devices
4103 #define NR_DEVICE 8 // Only eight devices supported currently.
4104
4105 // ---------------------------------------------------------------------
4106
4107 static struct initvol {
4108 int mixch;
4109 int vol;
4110 } initvol[] __initdata = {
4111
4112 {
4113 SOUND_MIXER_WRITE_VOLUME, 0x4040}, {
4114 SOUND_MIXER_WRITE_PCM, 0x4040}, {
4115 SOUND_MIXER_WRITE_SYNTH, 0x4040}, {
4116 SOUND_MIXER_WRITE_CD, 0x4040}, {
4117 SOUND_MIXER_WRITE_LINE, 0x4040}, {
4118 SOUND_MIXER_WRITE_LINE1, 0x4040}, {
4119 SOUND_MIXER_WRITE_RECLEV, 0x0000}, {
4120 SOUND_MIXER_WRITE_SPEAKER, 0x4040}, {
4121 SOUND_MIXER_WRITE_MIC, 0x0000}
4122 };
4123
4124
4125 #ifndef NOT_CS4281_PM
4126 void __devinit cs4281_BuildFIFO(
4127 struct cs4281_pipeline *p,
4128 struct cs4281_state *s)
4129 {
4130 switch(p->number)
4131 {
4132 case 0: /* playback */
4133 {
4134 p->u32FCRnAddress = BA0_FCR0;
4135 p->u32FSICnAddress = BA0_FSIC0;
4136 p->u32FPDRnAddress = BA0_FPDR0;
4137 break;
4138 }
4139 case 1: /* capture */
4140 {
4141 p->u32FCRnAddress = BA0_FCR1;
4142 p->u32FSICnAddress = BA0_FSIC1;
4143 p->u32FPDRnAddress = BA0_FPDR1;
4144 break;
4145 }
4146
4147 case 2:
4148 {
4149 p->u32FCRnAddress = BA0_FCR2;
4150 p->u32FSICnAddress = BA0_FSIC2;
4151 p->u32FPDRnAddress = BA0_FPDR2;
4152 break;
4153 }
4154 case 3:
4155 {
4156 p->u32FCRnAddress = BA0_FCR3;
4157 p->u32FSICnAddress = BA0_FSIC3;
4158 p->u32FPDRnAddress = BA0_FPDR3;
4159 break;
4160 }
4161 default:
4162 break;
4163 }
4164 //
4165 // first read the hardware to initialize the member variables
4166 //
4167 p->u32FCRnValue = readl(s->pBA0 + p->u32FCRnAddress);
4168 p->u32FSICnValue = readl(s->pBA0 + p->u32FSICnAddress);
4169 p->u32FPDRnValue = readl(s->pBA0 + p->u32FPDRnAddress);
4170
4171 }
4172
4173 void __devinit cs4281_BuildDMAengine(
4174 struct cs4281_pipeline *p,
4175 struct cs4281_state *s)
4176 {
4177 /*
4178 * initialize all the addresses of this pipeline dma info.
4179 */
4180 switch(p->number)
4181 {
4182 case 0: /* playback */
4183 {
4184 p->u32DBAnAddress = BA0_DBA0;
4185 p->u32DCAnAddress = BA0_DCA0;
4186 p->u32DBCnAddress = BA0_DBC0;
4187 p->u32DCCnAddress = BA0_DCC0;
4188 p->u32DMRnAddress = BA0_DMR0;
4189 p->u32DCRnAddress = BA0_DCR0;
4190 p->u32HDSRnAddress = BA0_HDSR0;
4191 break;
4192 }
4193
4194 case 1: /* capture */
4195 {
4196 p->u32DBAnAddress = BA0_DBA1;
4197 p->u32DCAnAddress = BA0_DCA1;
4198 p->u32DBCnAddress = BA0_DBC1;
4199 p->u32DCCnAddress = BA0_DCC1;
4200 p->u32DMRnAddress = BA0_DMR1;
4201 p->u32DCRnAddress = BA0_DCR1;
4202 p->u32HDSRnAddress = BA0_HDSR1;
4203 break;
4204 }
4205
4206 case 2:
4207 {
4208 p->u32DBAnAddress = BA0_DBA2;
4209 p->u32DCAnAddress = BA0_DCA2;
4210 p->u32DBCnAddress = BA0_DBC2;
4211 p->u32DCCnAddress = BA0_DCC2;
4212 p->u32DMRnAddress = BA0_DMR2;
4213 p->u32DCRnAddress = BA0_DCR2;
4214 p->u32HDSRnAddress = BA0_HDSR2;
4215 break;
4216 }
4217
4218 case 3:
4219 {
4220 p->u32DBAnAddress = BA0_DBA3;
4221 p->u32DCAnAddress = BA0_DCA3;
4222 p->u32DBCnAddress = BA0_DBC3;
4223 p->u32DCCnAddress = BA0_DCC3;
4224 p->u32DMRnAddress = BA0_DMR3;
4225 p->u32DCRnAddress = BA0_DCR3;
4226 p->u32HDSRnAddress = BA0_HDSR3;
4227 break;
4228 }
4229 default:
4230 break;
4231 }
4232
4233 //
4234 // Initialize the dma values for this pipeline
4235 //
4236 p->u32DBAnValue = readl(s->pBA0 + p->u32DBAnAddress);
4237 p->u32DBCnValue = readl(s->pBA0 + p->u32DBCnAddress);
4238 p->u32DMRnValue = readl(s->pBA0 + p->u32DMRnAddress);
4239 p->u32DCRnValue = readl(s->pBA0 + p->u32DCRnAddress);
4240
4241 }
4242
4243 void __devinit cs4281_InitPM(struct cs4281_state *s)
4244 {
4245 int i;
4246 struct cs4281_pipeline *p;
4247
4248 for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
4249 {
4250 p = &s->pl[i];
4251 p->number = i;
4252 cs4281_BuildDMAengine(p,s);
4253 cs4281_BuildFIFO(p,s);
4254 /*
4255 * currently only 2 pipelines are used
4256 * so, only set the valid bit on the playback and capture.
4257 */
4258 if( (i == CS4281_PLAYBACK_PIPELINE_NUMBER) ||
4259 (i == CS4281_CAPTURE_PIPELINE_NUMBER))
4260 p->flags |= CS4281_PIPELINE_VALID;
4261 }
4262 s->pm.u32SSPM_BITS = 0x7e; /* rev c, use 0x7c for rev a or b */
4263 }
4264 #endif
4265
4266 static int __devinit cs4281_probe(struct pci_dev *pcidev,
4267 const struct pci_device_id *pciid)
4268 {
4269 #ifndef NOT_CS4281_PM
4270 struct pm_dev *pmdev;
4271 #endif
4272 struct cs4281_state *s;
4273 dma_addr_t dma_mask;
4274 mm_segment_t fs;
4275 int i, val;
4276 unsigned int temp1, temp2;
4277
4278 CS_DBGOUT(CS_FUNCTION | CS_INIT, 2,
4279 printk(KERN_INFO "cs4281: probe()+\n"));
4280
4281 if (pci_enable_device(pcidev)) {
4282 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4283 "cs4281: pci_enable_device() failed\n"));
4284 return -1;
4285 }
4286 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM) ||
4287 !(pci_resource_flags(pcidev, 1) & IORESOURCE_MEM)) {
4288 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4289 "cs4281: probe()- Memory region not assigned\n"));
4290 return -ENODEV;
4291 }
4292 if (pcidev->irq == 0) {
4293 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4294 "cs4281: probe() IRQ not assigned\n"));
4295 return -ENODEV;
4296 }
4297 dma_mask = 0xffffffff; /* this enables playback and recording */
4298 i = pci_set_dma_mask(pcidev, dma_mask);
4299 if (i) {
4300 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4301 "cs4281: probe() architecture does not support 32bit PCI busmaster DMA\n"));
4302 return i;
4303 }
4304 if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) {
4305 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4306 "cs4281: probe() no memory for state struct.\n"));
4307 return -1;
4308 }
4309 memset(s, 0, sizeof(struct cs4281_state));
4310 init_waitqueue_head(&s->dma_adc.wait);
4311 init_waitqueue_head(&s->dma_dac.wait);
4312 init_waitqueue_head(&s->open_wait);
4313 init_waitqueue_head(&s->open_wait_adc);
4314 init_waitqueue_head(&s->open_wait_dac);
4315 init_waitqueue_head(&s->midi.iwait);
4316 init_waitqueue_head(&s->midi.owait);
4317 init_MUTEX(&s->open_sem);
4318 init_MUTEX(&s->open_sem_adc);
4319 init_MUTEX(&s->open_sem_dac);
4320 spin_lock_init(&s->lock);
4321 s->pBA0phys = pci_resource_start(pcidev, 0);
4322 s->pBA1phys = pci_resource_start(pcidev, 1);
4323
4324 /* Convert phys to linear. */
4325 s->pBA0 = ioremap_nocache(s->pBA0phys, 4096);
4326 if (!s->pBA0) {
4327 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4328 "cs4281: BA0 I/O mapping failed. Skipping part.\n"));
4329 goto err_free;
4330 }
4331 s->pBA1 = ioremap_nocache(s->pBA1phys, 65536);
4332 if (!s->pBA1) {
4333 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4334 "cs4281: BA1 I/O mapping failed. Skipping part.\n"));
4335 goto err_unmap;
4336 }
4337
4338 temp1 = readl(s->pBA0 + BA0_PCICFG00);
4339 temp2 = readl(s->pBA0 + BA0_PCICFG04);
4340
4341 CS_DBGOUT(CS_INIT, 2,
4342 printk(KERN_INFO
4343 "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=0x%.8x pBA1=0x%.8x \n",
4344 (unsigned) temp1, (unsigned) temp2,
4345 (unsigned) s->pBA0, (unsigned) s->pBA1));
4346
4347 CS_DBGOUT(CS_INIT, 2,
4348 printk(KERN_INFO
4349 "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n",
4350 (unsigned) s->pBA0phys, (unsigned) s->pBA1phys));
4351
4352 #ifndef NOT_CS4281_PM
4353 s->pm.flags = CS4281_PM_IDLE;
4354 #endif
4355 temp1 = cs4281_hw_init(s);
4356 if (temp1) {
4357 CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4358 "cs4281: cs4281_hw_init() failed. Skipping part.\n"));
4359 goto err_irq;
4360 }
4361 s->magic = CS4281_MAGIC;
4362 s->pcidev = pcidev;
4363 s->irq = pcidev->irq;
4364 if (request_irq
4365 (s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)) {
4366 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
4367 printk(KERN_ERR "cs4281: irq %u in use\n", s->irq));
4368 goto err_irq;
4369 }
4370 if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) <
4371 0) {
4372 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4373 "cs4281: probe() register_sound_dsp() failed.\n"));
4374 goto err_dev1;
4375 }
4376 if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) <
4377 0) {
4378 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4379 "cs4281: probe() register_sound_mixer() failed.\n"));
4380 goto err_dev2;
4381 }
4382 if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0) {
4383 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4384 "cs4281: probe() register_sound_midi() failed.\n"));
4385 goto err_dev3;
4386 }
4387 #ifndef NOT_CS4281_PM
4388 cs4281_InitPM(s);
4389 pmdev = cs_pm_register(PM_PCI_DEV, PM_PCI_ID(pcidev), cs4281_pm_callback);
4390 if (pmdev)
4391 {
4392 CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO
4393 "cs4281: probe() pm_register() succeeded (0x%x).\n",
4394 (unsigned)pmdev));
4395 pmdev->data = s;
4396 }
4397 else
4398 {
4399 CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO
4400 "cs4281: probe() pm_register() failed (0x%x).\n",
4401 (unsigned)pmdev));
4402 s->pm.flags |= CS4281_PM_NOT_REGISTERED;
4403 }
4404 #endif
4405
4406 pci_set_master(pcidev); // enable bus mastering
4407
4408 fs = get_fs();
4409 set_fs(KERNEL_DS);
4410 val = SOUND_MASK_LINE;
4411 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
4412 for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
4413 val = initvol[i].vol;
4414 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
4415 }
4416 val = 1; // enable mic preamp
4417 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long) &val);
4418 set_fs(fs);
4419
4420 pci_set_drvdata(pcidev, s);
4421 list_add(&s->list, &cs4281_devs);
4422 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4423 "cs4281: probe()- device allocated successfully\n"));
4424 return 0;
4425
4426 err_dev3:
4427 unregister_sound_mixer(s->dev_mixer);
4428 err_dev2:
4429 unregister_sound_dsp(s->dev_audio);
4430 err_dev1:
4431 free_irq(s->irq, s);
4432 err_irq:
4433 iounmap(s->pBA1);
4434 err_unmap:
4435 iounmap(s->pBA0);
4436 err_free:
4437 kfree(s);
4438
4439 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
4440 "cs4281: probe()- no device allocated\n"));
4441 return -ENODEV;
4442 } // probe_cs4281
4443
4444
4445 // ---------------------------------------------------------------------
4446
4447 static void __devinit cs4281_remove(struct pci_dev *pci_dev)
4448 {
4449 struct cs4281_state *s = pci_get_drvdata(pci_dev);
4450 // stop DMA controller
4451 synchronize_irq();
4452 free_irq(s->irq, s);
4453 unregister_sound_dsp(s->dev_audio);
4454 unregister_sound_mixer(s->dev_mixer);
4455 unregister_sound_midi(s->dev_midi);
4456 iounmap(s->pBA1);
4457 iounmap(s->pBA0);
4458 pci_set_drvdata(pci_dev,NULL);
4459 list_del(&s->list);
4460 kfree(s);
4461 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4462 "cs4281: cs4281_remove()-: remove successful\n"));
4463 }
4464
4465 static struct pci_device_id cs4281_pci_tbl[] __devinitdata = {
4466 {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CRYSTAL_CS4281,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0},
4468 {0,}
4469 };
4470
4471 MODULE_DEVICE_TABLE(pci, cs4281_pci_tbl);
4472
4473 struct pci_driver cs4281_pci_driver = {
4474 name:"cs4281",
4475 id_table:cs4281_pci_tbl,
4476 probe:cs4281_probe,
4477 remove:cs4281_remove,
4478 suspend:CS4281_SUSPEND_TBL,
4479 resume:CS4281_RESUME_TBL,
4480 };
4481
4482 int __init cs4281_init_module(void)
4483 {
4484 int rtn = 0;
4485 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4486 "cs4281: cs4281_init_module()+ \n"));
4487 if (!pci_present()) { /* No PCI bus in this machine! */
4488 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4489 "cs4281: cs4281_init_module()- no pci bus found\n"));
4490 return -ENODEV;
4491 }
4492 printk(KERN_INFO "cs4281: version v%d.%02d.%d time " __TIME__ " "
4493 __DATE__ "\n", CS4281_MAJOR_VERSION, CS4281_MINOR_VERSION,
4494 CS4281_ARCH);
4495 rtn = pci_module_init(&cs4281_pci_driver);
4496
4497 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4498 printk(KERN_INFO "cs4281: cs4281_init_module()- (%d)\n",rtn));
4499 return rtn;
4500 }
4501
4502 void __exit cs4281_cleanup_module(void)
4503 {
4504 pci_unregister_driver(&cs4281_pci_driver);
4505 #ifndef NOT_CS4281_PM
4506 cs_pm_unregister_all(cs4281_pm_callback);
4507 #endif
4508 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4509 printk(KERN_INFO "cs4281: cleanup_cs4281() finished\n"));
4510 }
4511 // ---------------------------------------------------------------------
4512
4513 MODULE_AUTHOR("gw boynton, audio@crystal.cirrus.com");
4514 MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver");
4515
4516 // ---------------------------------------------------------------------
4517
4518 module_init(cs4281_init_module);
4519 module_exit(cs4281_cleanup_module);
4520
4521 #ifndef MODULE
4522 int __init init_cs4281(void)
4523 {
4524 return cs4281_init_module();
4525 }
4526 #endif
4527