File: /usr/src/linux/drivers/sound/es1371.c
1 /*****************************************************************************/
2
3 /*
4 * es1371.c -- Creative Ensoniq ES1371.
5 *
6 * Copyright (C) 1998-2001 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to Ensoniq
23 *
24 *
25 * Module command line parameters:
26 * joystick must be set to the base I/O-Port to be used for
27 * the gameport. Legal values are 0x200, 0x208, 0x210 and 0x218.
28 * The gameport is mirrored eight times.
29 *
30 * Supported devices:
31 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
32 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
33 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
34 * /dev/midi simple MIDI UART interface, no ioctl
35 *
36 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
37 * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
38 * there are several MIDI to PCM (WAV) packages, one of them is timidity.
39 *
40 * Revision history
41 * 04.06.1998 0.1 Initial release
42 * Mixer stuff should be overhauled; especially optional AC97 mixer bits
43 * should be detected. This results in strange behaviour of some mixer
44 * settings, like master volume and mic.
45 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
46 * 03.08.1998 0.3 Do not include modversions.h
47 * Now mixer behaviour can basically be selected between
48 * "OSS documented" and "OSS actual" behaviour
49 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
50 * 27.10.1998 0.5 Fix joystick support
51 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
52 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
53 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
54 * Don't wake up app until there are fragsize bytes to read/write
55 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
56 * hopefully killed the egcs section type conflict
57 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
58 * reported by Johan Maes <joma@telindus.be>
59 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
60 * read/write cannot be executed
61 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
62 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
63 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
64 * Another Alpha fix (wait_src_ready in init routine)
65 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
66 * Note: joystick address handling might still be wrong on archs
67 * other than i386
68 * 15.06.1999 0.12 Fix bad allocation bug.
69 * Thanks to Deti Fliegl <fliegl@in.tum.de>
70 * 28.06.1999 0.13 Add pci_set_master
71 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
72 * added kernel command line option "es1371=joystickaddr"
73 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
74 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
75 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
76 * module_init/__setup fixes
77 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
78 * Added detection for ES1371 revision ID so that we can
79 * detect the ES1373 and later parts.
80 * added AC97 #defines for readability
81 * added a /proc file system for dumping hardware state
82 * updated SRC and CODEC w/r functions to accomodate bugs
83 * in some versions of the ES137x chips.
84 * 31.08.1999 0.17 add spin_lock_init
85 * replaced current->state = x with set_current_state(x)
86 * 03.09.1999 0.18 change read semantics for MIDI to match
87 * OSS more closely; remove possible wakeup race
88 * 21.10.1999 0.19 Round sampling rates, requested by
89 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
90 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
91 * Codec ID printing changes
92 * 28.10.1999 0.21 More waitqueue races fixed
93 * Joe Cotellese <joec@ensoniq.com>
94 * Changed PCI detection routine so we can more easily
95 * detect ES137x chip and derivatives.
96 * 05.01.2000 0.22 Should now work with rev7 boards; patch by
97 * Eric Lemar, elemar@cs.washington.edu
98 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
99 * Tim Janik's BSE (Bedevilled Sound Engine) found this
100 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
101 * 07.02.2000 0.25 Use ac97_codec
102 * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
103 * Use pci_module_init
104 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
105 * 12.12.2000 0.28 More dma buffer initializations, patch from
106 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
107 * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
108 * the CT5880 revision.
109 * suggested by Stephan Müller <smueller@chronox.de>
110 * 31.01.2001 0.30 Register/Unregister gameport
111 * Fix SETTRIGGER non OSS API conformity
112 * 14.07.2001 0.31 Add list of laptops needing amplifier control
113 */
114
115 /*****************************************************************************/
116
117 #include <linux/version.h>
118 #include <linux/module.h>
119 #include <linux/string.h>
120 #include <linux/ioport.h>
121 #include <linux/sched.h>
122 #include <linux/delay.h>
123 #include <linux/sound.h>
124 #include <linux/slab.h>
125 #include <linux/soundcard.h>
126 #include <linux/pci.h>
127 #include <linux/init.h>
128 #include <linux/poll.h>
129 #include <linux/bitops.h>
130 #include <linux/proc_fs.h>
131 #include <linux/spinlock.h>
132 #include <linux/smp_lock.h>
133 #include <linux/ac97_codec.h>
134 #include <linux/wrapper.h>
135 #include <asm/io.h>
136 #include <asm/dma.h>
137 #include <asm/uaccess.h>
138 #include <asm/hardirq.h>
139 #include <linux/gameport.h>
140
141 /* --------------------------------------------------------------------- */
142
143 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
144 #define ES1371_DEBUG
145 #define DBG(x) {}
146 /*#define DBG(x) {x}*/
147
148 /* --------------------------------------------------------------------- */
149
150 #ifndef PCI_VENDOR_ID_ENSONIQ
151 #define PCI_VENDOR_ID_ENSONIQ 0x1274
152 #endif
153
154 #ifndef PCI_VENDOR_ID_ECTIVA
155 #define PCI_VENDOR_ID_ECTIVA 0x1102
156 #endif
157
158 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
159 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
160 #endif
161
162 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
163 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
164 #endif
165
166 #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
167 #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
168 #endif
169
170 /* ES1371 chip ID */
171 /* This is a little confusing because all ES1371 compatible chips have the
172 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
173 This is only significant if you want to enable features on the later parts.
174 Yes, I know it's stupid and why didn't we use the sub IDs?
175 */
176 #define ES1371REV_ES1373_A 0x04
177 #define ES1371REV_ES1373_B 0x06
178 #define ES1371REV_CT5880_A 0x07
179 #define CT5880REV_CT5880_C 0x02
180 #define CT5880REV_CT5880_D 0x03
181 #define ES1371REV_ES1371_B 0x09
182 #define EV1938REV_EV1938_A 0x00
183 #define ES1371REV_ES1373_8 0x08
184
185 #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
186
187 #define ES1371_EXTENT 0x40
188 #define JOY_EXTENT 8
189
190 #define ES1371_REG_CONTROL 0x00
191 #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
192 #define ES1371_REG_UART_DATA 0x08
193 #define ES1371_REG_UART_STATUS 0x09
194 #define ES1371_REG_UART_CONTROL 0x09
195 #define ES1371_REG_UART_TEST 0x0a
196 #define ES1371_REG_MEMPAGE 0x0c
197 #define ES1371_REG_SRCONV 0x10
198 #define ES1371_REG_CODEC 0x14
199 #define ES1371_REG_LEGACY 0x18
200 #define ES1371_REG_SERIAL_CONTROL 0x20
201 #define ES1371_REG_DAC1_SCOUNT 0x24
202 #define ES1371_REG_DAC2_SCOUNT 0x28
203 #define ES1371_REG_ADC_SCOUNT 0x2c
204
205 #define ES1371_REG_DAC1_FRAMEADR 0xc30
206 #define ES1371_REG_DAC1_FRAMECNT 0xc34
207 #define ES1371_REG_DAC2_FRAMEADR 0xc38
208 #define ES1371_REG_DAC2_FRAMECNT 0xc3c
209 #define ES1371_REG_ADC_FRAMEADR 0xd30
210 #define ES1371_REG_ADC_FRAMECNT 0xd34
211
212 #define ES1371_FMT_U8_MONO 0
213 #define ES1371_FMT_U8_STEREO 1
214 #define ES1371_FMT_S16_MONO 2
215 #define ES1371_FMT_S16_STEREO 3
216 #define ES1371_FMT_STEREO 1
217 #define ES1371_FMT_S16 2
218 #define ES1371_FMT_MASK 3
219
220 static const unsigned sample_size[] = { 1, 2, 2, 4 };
221 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
222
223 #define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
224 #define CTRL_SPDIFEN_B 0x04000000
225 #define CTRL_JOY_SHIFT 24
226 #define CTRL_JOY_MASK 3
227 #define CTRL_JOY_200 0x00000000 /* joystick base address */
228 #define CTRL_JOY_208 0x01000000
229 #define CTRL_JOY_210 0x02000000
230 #define CTRL_JOY_218 0x03000000
231 #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
232 #define CTRL_GPIO_IN1 0x00200000
233 #define CTRL_GPIO_IN2 0x00400000
234 #define CTRL_GPIO_IN3 0x00800000
235 #define CTRL_GPIO_OUT0 0x00010000
236 #define CTRL_GPIO_OUT1 0x00020000
237 #define CTRL_GPIO_OUT2 0x00040000
238 #define CTRL_GPIO_OUT3 0x00080000
239 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
240 #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
241 #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
242 #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
243 #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
244 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
245 #define CTRL_PDLEV0 0x00000000 /* power down level */
246 #define CTRL_PDLEV1 0x00000100
247 #define CTRL_PDLEV2 0x00000200
248 #define CTRL_PDLEV3 0x00000300
249 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
250 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
251 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
252 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
253 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
254 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
255 #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
256 #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
257
258
259 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
260 #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
261 #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
262 #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
263 #define STAT_TESTMODE 0x00010000 /* test ASIC */
264 #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
265 #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
266 #define STAT_SH_VC 6
267 #define STAT_MPWR 0x00000020 /* power level interrupt */
268 #define STAT_MCCB 0x00000010 /* CCB int pending */
269 #define STAT_UART 0x00000008 /* UART int pending */
270 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
271 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
272 #define STAT_ADC 0x00000001 /* ADC int pending */
273
274 #define USTAT_RXINT 0x80 /* UART rx int pending */
275 #define USTAT_TXINT 0x04 /* UART tx int pending */
276 #define USTAT_TXRDY 0x02 /* UART tx ready */
277 #define USTAT_RXRDY 0x01 /* UART rx ready */
278
279 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
280 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
281 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
282 #define UCTRL_CNTRL 0x03 /* control field */
283 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
284
285 /* sample rate converter */
286 #define SRC_OKSTATE 1
287
288 #define SRC_RAMADDR_MASK 0xfe000000
289 #define SRC_RAMADDR_SHIFT 25
290 #define SRC_DAC1FREEZE (1UL << 21)
291 #define SRC_DAC2FREEZE (1UL << 20)
292 #define SRC_ADCFREEZE (1UL << 19)
293
294
295 #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
296 #define SRC_BUSY 0x00800000 /* SRC busy */
297 #define SRC_DIS 0x00400000 /* 1 = disable SRC */
298 #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
299 #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
300 #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
301 #define SRC_CTLMASK 0x00780000
302 #define SRC_RAMDATA_MASK 0x0000ffff
303 #define SRC_RAMDATA_SHIFT 0
304
305 #define SRCREG_ADC 0x78
306 #define SRCREG_DAC1 0x70
307 #define SRCREG_DAC2 0x74
308 #define SRCREG_VOL_ADC 0x6c
309 #define SRCREG_VOL_DAC1 0x7c
310 #define SRCREG_VOL_DAC2 0x7e
311
312 #define SRCREG_TRUNC_N 0x00
313 #define SRCREG_INT_REGS 0x01
314 #define SRCREG_ACCUM_FRAC 0x02
315 #define SRCREG_VFREQ_FRAC 0x03
316
317 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
318 #define CODEC_PIADD_MASK 0x007f0000
319 #define CODEC_PIADD_SHIFT 16
320 #define CODEC_PIDAT_MASK 0x0000ffff
321 #define CODEC_PIDAT_SHIFT 0
322
323 #define CODEC_RDY 0x80000000 /* AC97 read data valid */
324 #define CODEC_WIP 0x40000000 /* AC97 write in progress */
325 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
326 #define CODEC_POADD_MASK 0x007f0000
327 #define CODEC_POADD_SHIFT 16
328 #define CODEC_PODAT_MASK 0x0000ffff
329 #define CODEC_PODAT_SHIFT 0
330
331
332 #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
333 #define LEGACY_FIRQ 0x01000000 /* force IRQ */
334
335 #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
336 #define SCTRL_P2ENDINC 0x00380000 /* */
337 #define SCTRL_SH_P2ENDINC 19
338 #define SCTRL_P2STINC 0x00070000 /* */
339 #define SCTRL_SH_P2STINC 16
340 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
341 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
342 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
343 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
344 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
345 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
346 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
347 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
348 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
349 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
350 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
351 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
352 #define SCTRL_R1FMT 0x00000030 /* format mask */
353 #define SCTRL_SH_R1FMT 4
354 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
355 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
356 #define SCTRL_P2FMT 0x0000000c /* format mask */
357 #define SCTRL_SH_P2FMT 2
358 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
359 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
360 #define SCTRL_P1FMT 0x00000003 /* format mask */
361 #define SCTRL_SH_P1FMT 0
362
363
364 /* misc stuff */
365 #define POLL_COUNT 0x1000
366 #define FMODE_DAC 4 /* slight misuse of mode_t */
367
368 /* MIDI buffer sizes */
369
370 #define MIDIINBUF 256
371 #define MIDIOUTBUF 256
372
373 #define FMODE_MIDI_SHIFT 3
374 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
375 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
376
377 #define ES1371_MODULE_NAME "es1371"
378 #define PFX ES1371_MODULE_NAME ": "
379
380 /* --------------------------------------------------------------------- */
381
382 struct es1371_state {
383 /* magic */
384 unsigned int magic;
385
386 /* list of es1371 devices */
387 struct list_head devs;
388
389 /* the corresponding pci_dev structure */
390 struct pci_dev *dev;
391
392 /* soundcore stuff */
393 int dev_audio;
394 int dev_dac;
395 int dev_midi;
396
397 /* hardware resources */
398 unsigned long io; /* long for SPARC */
399 unsigned int irq;
400
401 /* PCI ID's */
402 u16 vendor;
403 u16 device;
404 u8 rev; /* the chip revision */
405
406 /* options */
407 int spdif_volume; /* S/PDIF output is enabled if != -1 */
408
409 #ifdef ES1371_DEBUG
410 /* debug /proc entry */
411 struct proc_dir_entry *ps;
412 #endif /* ES1371_DEBUG */
413
414 struct ac97_codec codec;
415
416 /* wave stuff */
417 unsigned ctrl;
418 unsigned sctrl;
419 unsigned dac1rate, dac2rate, adcrate;
420
421 spinlock_t lock;
422 struct semaphore open_sem;
423 mode_t open_mode;
424 wait_queue_head_t open_wait;
425
426 struct dmabuf {
427 void *rawbuf;
428 dma_addr_t dmaaddr;
429 unsigned buforder;
430 unsigned numfrag;
431 unsigned fragshift;
432 unsigned hwptr, swptr;
433 unsigned total_bytes;
434 int count;
435 unsigned error; /* over/underrun */
436 wait_queue_head_t wait;
437 /* redundant, but makes calculations easier */
438 unsigned fragsize;
439 unsigned dmasize;
440 unsigned fragsamples;
441 /* OSS stuff */
442 unsigned mapped:1;
443 unsigned ready:1;
444 unsigned endcleared:1;
445 unsigned enabled:1;
446 unsigned ossfragshift;
447 int ossmaxfrags;
448 unsigned subdivision;
449 } dma_dac1, dma_dac2, dma_adc;
450
451 /* midi stuff */
452 struct {
453 unsigned ird, iwr, icnt;
454 unsigned ord, owr, ocnt;
455 wait_queue_head_t iwait;
456 wait_queue_head_t owait;
457 unsigned char ibuf[MIDIINBUF];
458 unsigned char obuf[MIDIOUTBUF];
459 } midi;
460
461 struct gameport gameport;
462 struct semaphore sem;
463 };
464
465 /* --------------------------------------------------------------------- */
466
467 static LIST_HEAD(devs);
468
469 /* --------------------------------------------------------------------- */
470
471 static inline unsigned ld2(unsigned int x)
472 {
473 unsigned r = 0;
474
475 if (x >= 0x10000) {
476 x >>= 16;
477 r += 16;
478 }
479 if (x >= 0x100) {
480 x >>= 8;
481 r += 8;
482 }
483 if (x >= 0x10) {
484 x >>= 4;
485 r += 4;
486 }
487 if (x >= 4) {
488 x >>= 2;
489 r += 2;
490 }
491 if (x >= 2)
492 r++;
493 return r;
494 }
495
496 /* --------------------------------------------------------------------- */
497
498 static unsigned wait_src_ready(struct es1371_state *s)
499 {
500 unsigned int t, r;
501
502 for (t = 0; t < POLL_COUNT; t++) {
503 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
504 return r;
505 udelay(1);
506 }
507 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
508 return r;
509 }
510
511 static unsigned src_read(struct es1371_state *s, unsigned reg)
512 {
513 unsigned int temp,i,orig;
514
515 /* wait for ready */
516 temp = wait_src_ready (s);
517
518 /* we can only access the SRC at certain times, make sure
519 we're allowed to before we read */
520
521 orig = temp;
522 /* expose the SRC state bits */
523 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
524 s->io + ES1371_REG_SRCONV);
525
526 /* now, wait for busy and the correct time to read */
527 temp = wait_src_ready (s);
528
529 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
530 /* wait for the right state */
531 for (i=0; i<POLL_COUNT; i++){
532 temp = inl (s->io + ES1371_REG_SRCONV);
533 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
534 break;
535 }
536 }
537
538 /* hide the state bits */
539 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
540 return temp;
541
542
543 }
544
545 static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
546 {
547
548 unsigned int r;
549
550 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
551 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
552 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
553 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
554
555 }
556
557 /* --------------------------------------------------------------------- */
558
559 /* most of the following here is black magic */
560 static void set_adc_rate(struct es1371_state *s, unsigned rate)
561 {
562 unsigned long flags;
563 unsigned int n, truncm, freq;
564
565 if (rate > 48000)
566 rate = 48000;
567 if (rate < 4000)
568 rate = 4000;
569 n = rate / 3000;
570 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
571 n--;
572 truncm = (21 * n - 1) | 1;
573 freq = ((48000UL << 15) / rate) * n;
574 s->adcrate = (48000UL << 15) / (freq / n);
575 spin_lock_irqsave(&s->lock, flags);
576 if (rate >= 24000) {
577 if (truncm > 239)
578 truncm = 239;
579 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
580 (((239 - truncm) >> 1) << 9) | (n << 4));
581 } else {
582 if (truncm > 119)
583 truncm = 119;
584 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
585 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
586 }
587 src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
588 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
589 ((freq >> 5) & 0xfc00));
590 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
591 src_write(s, SRCREG_VOL_ADC, n << 8);
592 src_write(s, SRCREG_VOL_ADC+1, n << 8);
593 spin_unlock_irqrestore(&s->lock, flags);
594 }
595
596
597 static void set_dac1_rate(struct es1371_state *s, unsigned rate)
598 {
599 unsigned long flags;
600 unsigned int freq, r;
601
602 if (rate > 48000)
603 rate = 48000;
604 if (rate < 4000)
605 rate = 4000;
606 freq = ((rate << 15) + 1500) / 3000;
607 s->dac1rate = (freq * 3000 + 16384) >> 15;
608 spin_lock_irqsave(&s->lock, flags);
609 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
610 outl(r, s->io + ES1371_REG_SRCONV);
611 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
612 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
613 ((freq >> 5) & 0xfc00));
614 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
615 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
616 outl(r, s->io + ES1371_REG_SRCONV);
617 spin_unlock_irqrestore(&s->lock, flags);
618 }
619
620 static void set_dac2_rate(struct es1371_state *s, unsigned rate)
621 {
622 unsigned long flags;
623 unsigned int freq, r;
624
625 if (rate > 48000)
626 rate = 48000;
627 if (rate < 4000)
628 rate = 4000;
629 freq = ((rate << 15) + 1500) / 3000;
630 s->dac2rate = (freq * 3000 + 16384) >> 15;
631 spin_lock_irqsave(&s->lock, flags);
632 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
633 outl(r, s->io + ES1371_REG_SRCONV);
634 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
635 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
636 ((freq >> 5) & 0xfc00));
637 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
638 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
639 outl(r, s->io + ES1371_REG_SRCONV);
640 spin_unlock_irqrestore(&s->lock, flags);
641 }
642
643 /* --------------------------------------------------------------------- */
644
645 static void __init src_init(struct es1371_state *s)
646 {
647 unsigned int i;
648
649 /* before we enable or disable the SRC we need
650 to wait for it to become ready */
651 wait_src_ready(s);
652
653 outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
654
655 for (i = 0; i < 0x80; i++)
656 src_write(s, i, 0);
657
658 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
659 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
660 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
661 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
662 src_write(s, SRCREG_VOL_ADC, 1 << 12);
663 src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
664 src_write(s, SRCREG_VOL_DAC1, 1 << 12);
665 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
666 src_write(s, SRCREG_VOL_DAC2, 1 << 12);
667 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
668 set_adc_rate(s, 22050);
669 set_dac1_rate(s, 22050);
670 set_dac2_rate(s, 22050);
671
672 /* WARNING:
673 * enabling the sample rate converter without properly programming
674 * its parameters causes the chip to lock up (the SRC busy bit will
675 * be stuck high, and I've found no way to rectify this other than
676 * power cycle)
677 */
678 wait_src_ready(s);
679 outl(0, s->io+ES1371_REG_SRCONV);
680 }
681
682 /* --------------------------------------------------------------------- */
683
684 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
685 {
686 struct es1371_state *s = (struct es1371_state *)codec->private_data;
687 unsigned long flags;
688 unsigned t, x;
689
690 for (t = 0; t < POLL_COUNT; t++)
691 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
692 break;
693 spin_lock_irqsave(&s->lock, flags);
694
695 /* save the current state for later */
696 x = wait_src_ready(s);
697
698 /* enable SRC state data in SRC mux */
699 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
700 s->io+ES1371_REG_SRCONV);
701
702 /* wait for not busy (state 0) first to avoid
703 transition states */
704 for (t=0; t<POLL_COUNT; t++){
705 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
706 break;
707 udelay(1);
708 }
709
710 /* wait for a SAFE time to write addr/data and then do it, dammit */
711 for (t=0; t<POLL_COUNT; t++){
712 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
713 break;
714 udelay(1);
715 }
716
717 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
718 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
719
720 /* restore SRC reg */
721 wait_src_ready(s);
722 outl(x, s->io+ES1371_REG_SRCONV);
723 spin_unlock_irqrestore(&s->lock, flags);
724 }
725
726 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
727 {
728 struct es1371_state *s = (struct es1371_state *)codec->private_data;
729 unsigned long flags;
730 unsigned t, x;
731
732 /* wait for WIP to go away */
733 for (t = 0; t < 0x1000; t++)
734 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
735 break;
736 spin_lock_irqsave(&s->lock, flags);
737
738 /* save the current state for later */
739 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
740
741 /* enable SRC state data in SRC mux */
742 outl( x | 0x00010000,
743 s->io+ES1371_REG_SRCONV);
744
745 /* wait for not busy (state 0) first to avoid
746 transition states */
747 for (t=0; t<POLL_COUNT; t++){
748 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
749 break;
750 udelay(1);
751 }
752
753 /* wait for a SAFE time to write addr/data and then do it, dammit */
754 for (t=0; t<POLL_COUNT; t++){
755 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
756 break;
757 udelay(1);
758 }
759
760 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
761 /* restore SRC reg */
762 wait_src_ready(s);
763 outl(x, s->io+ES1371_REG_SRCONV);
764 spin_unlock_irqrestore(&s->lock, flags);
765
766 /* wait for WIP again */
767 for (t = 0; t < 0x1000; t++)
768 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
769 break;
770
771 /* now wait for the stinkin' data (RDY) */
772 for (t = 0; t < POLL_COUNT; t++)
773 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
774 break;
775
776 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
777 }
778
779 /* --------------------------------------------------------------------- */
780
781 static inline void stop_adc(struct es1371_state *s)
782 {
783 unsigned long flags;
784
785 spin_lock_irqsave(&s->lock, flags);
786 s->ctrl &= ~CTRL_ADC_EN;
787 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
788 spin_unlock_irqrestore(&s->lock, flags);
789 }
790
791 static inline void stop_dac1(struct es1371_state *s)
792 {
793 unsigned long flags;
794
795 spin_lock_irqsave(&s->lock, flags);
796 s->ctrl &= ~CTRL_DAC1_EN;
797 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
798 spin_unlock_irqrestore(&s->lock, flags);
799 }
800
801 static inline void stop_dac2(struct es1371_state *s)
802 {
803 unsigned long flags;
804
805 spin_lock_irqsave(&s->lock, flags);
806 s->ctrl &= ~CTRL_DAC2_EN;
807 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
808 spin_unlock_irqrestore(&s->lock, flags);
809 }
810
811 static void start_dac1(struct es1371_state *s)
812 {
813 unsigned long flags;
814 unsigned fragremain, fshift;
815
816 spin_lock_irqsave(&s->lock, flags);
817 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
818 && s->dma_dac1.ready) {
819 s->ctrl |= CTRL_DAC1_EN;
820 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
821 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
822 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
823 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
824 if (fragremain < 2*fshift)
825 fragremain = s->dma_dac1.fragsize;
826 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
827 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
828 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
829 }
830 spin_unlock_irqrestore(&s->lock, flags);
831 }
832
833 static void start_dac2(struct es1371_state *s)
834 {
835 unsigned long flags;
836 unsigned fragremain, fshift;
837
838 spin_lock_irqsave(&s->lock, flags);
839 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
840 && s->dma_dac2.ready) {
841 s->ctrl |= CTRL_DAC2_EN;
842 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
843 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
844 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
845 (0 << SCTRL_SH_P2STINC);
846 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
847 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
848 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
849 if (fragremain < 2*fshift)
850 fragremain = s->dma_dac2.fragsize;
851 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
852 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
853 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
854 }
855 spin_unlock_irqrestore(&s->lock, flags);
856 }
857
858 static void start_adc(struct es1371_state *s)
859 {
860 unsigned long flags;
861 unsigned fragremain, fshift;
862
863 spin_lock_irqsave(&s->lock, flags);
864 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
865 && s->dma_adc.ready) {
866 s->ctrl |= CTRL_ADC_EN;
867 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
868 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
869 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
870 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
871 if (fragremain < 2*fshift)
872 fragremain = s->dma_adc.fragsize;
873 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
874 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
875 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
876 }
877 spin_unlock_irqrestore(&s->lock, flags);
878 }
879
880 /* --------------------------------------------------------------------- */
881
882 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
883 #define DMABUF_MINORDER 1
884
885
886 static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
887 {
888 struct page *page, *pend;
889
890 if (db->rawbuf) {
891 /* undo marking the pages as reserved */
892 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
893 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
894 mem_map_unreserve(page);
895 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
896 }
897 db->rawbuf = NULL;
898 db->mapped = db->ready = 0;
899 }
900
901 static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
902 {
903 int order;
904 unsigned bytepersec;
905 unsigned bufs;
906 struct page *page, *pend;
907
908 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
909 if (!db->rawbuf) {
910 db->ready = db->mapped = 0;
911 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
912 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
913 break;
914 if (!db->rawbuf)
915 return -ENOMEM;
916 db->buforder = order;
917 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
918 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
919 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
920 mem_map_reserve(page);
921 }
922 fmt &= ES1371_FMT_MASK;
923 bytepersec = rate << sample_shift[fmt];
924 bufs = PAGE_SIZE << db->buforder;
925 if (db->ossfragshift) {
926 if ((1000 << db->ossfragshift) < bytepersec)
927 db->fragshift = ld2(bytepersec/1000);
928 else
929 db->fragshift = db->ossfragshift;
930 } else {
931 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
932 if (db->fragshift < 3)
933 db->fragshift = 3;
934 }
935 db->numfrag = bufs >> db->fragshift;
936 while (db->numfrag < 4 && db->fragshift > 3) {
937 db->fragshift--;
938 db->numfrag = bufs >> db->fragshift;
939 }
940 db->fragsize = 1 << db->fragshift;
941 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
942 db->numfrag = db->ossmaxfrags;
943 db->fragsamples = db->fragsize >> sample_shift[fmt];
944 db->dmasize = db->numfrag << db->fragshift;
945 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
946 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
947 outl(db->dmaaddr, s->io+(reg & 0xff));
948 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
949 db->enabled = 1;
950 db->ready = 1;
951 return 0;
952 }
953
954 static inline int prog_dmabuf_adc(struct es1371_state *s)
955 {
956 stop_adc(s);
957 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
958 ES1371_REG_ADC_FRAMEADR);
959 }
960
961 static inline int prog_dmabuf_dac2(struct es1371_state *s)
962 {
963 stop_dac2(s);
964 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
965 ES1371_REG_DAC2_FRAMEADR);
966 }
967
968 static inline int prog_dmabuf_dac1(struct es1371_state *s)
969 {
970 stop_dac1(s);
971 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
972 ES1371_REG_DAC1_FRAMEADR);
973 }
974
975 static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
976 {
977 unsigned hwptr, diff;
978
979 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
980 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
981 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
982 db->hwptr = hwptr;
983 return diff;
984 }
985
986 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
987 {
988 if (bptr + len > bsize) {
989 unsigned x = bsize - bptr;
990 memset(((char *)buf) + bptr, c, x);
991 bptr = 0;
992 len -= x;
993 }
994 memset(((char *)buf) + bptr, c, len);
995 }
996
997 /* call with spinlock held! */
998 static void es1371_update_ptr(struct es1371_state *s)
999 {
1000 int diff;
1001
1002 /* update ADC pointer */
1003 if (s->ctrl & CTRL_ADC_EN) {
1004 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
1005 s->dma_adc.total_bytes += diff;
1006 s->dma_adc.count += diff;
1007 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1008 wake_up(&s->dma_adc.wait);
1009 if (!s->dma_adc.mapped) {
1010 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1011 s->ctrl &= ~CTRL_ADC_EN;
1012 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1013 s->dma_adc.error++;
1014 }
1015 }
1016 }
1017 /* update DAC1 pointer */
1018 if (s->ctrl & CTRL_DAC1_EN) {
1019 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1020 s->dma_dac1.total_bytes += diff;
1021 if (s->dma_dac1.mapped) {
1022 s->dma_dac1.count += diff;
1023 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1024 wake_up(&s->dma_dac1.wait);
1025 } else {
1026 s->dma_dac1.count -= diff;
1027 if (s->dma_dac1.count <= 0) {
1028 s->ctrl &= ~CTRL_DAC1_EN;
1029 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1030 s->dma_dac1.error++;
1031 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1032 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
1033 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1034 s->dma_dac1.endcleared = 1;
1035 }
1036 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1037 wake_up(&s->dma_dac1.wait);
1038 }
1039 }
1040 /* update DAC2 pointer */
1041 if (s->ctrl & CTRL_DAC2_EN) {
1042 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1043 s->dma_dac2.total_bytes += diff;
1044 if (s->dma_dac2.mapped) {
1045 s->dma_dac2.count += diff;
1046 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1047 wake_up(&s->dma_dac2.wait);
1048 } else {
1049 s->dma_dac2.count -= diff;
1050 if (s->dma_dac2.count <= 0) {
1051 s->ctrl &= ~CTRL_DAC2_EN;
1052 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1053 s->dma_dac2.error++;
1054 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1055 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
1056 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1057 s->dma_dac2.endcleared = 1;
1058 }
1059 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1060 wake_up(&s->dma_dac2.wait);
1061 }
1062 }
1063 }
1064
1065 /* hold spinlock for the following! */
1066 static void es1371_handle_midi(struct es1371_state *s)
1067 {
1068 unsigned char ch;
1069 int wake;
1070
1071 if (!(s->ctrl & CTRL_UART_EN))
1072 return;
1073 wake = 0;
1074 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1075 ch = inb(s->io+ES1371_REG_UART_DATA);
1076 if (s->midi.icnt < MIDIINBUF) {
1077 s->midi.ibuf[s->midi.iwr] = ch;
1078 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1079 s->midi.icnt++;
1080 }
1081 wake = 1;
1082 }
1083 if (wake)
1084 wake_up(&s->midi.iwait);
1085 wake = 0;
1086 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1087 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1088 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1089 s->midi.ocnt--;
1090 if (s->midi.ocnt < MIDIOUTBUF-16)
1091 wake = 1;
1092 }
1093 if (wake)
1094 wake_up(&s->midi.owait);
1095 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1096 }
1097
1098 static void es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1099 {
1100 struct es1371_state *s = (struct es1371_state *)dev_id;
1101 unsigned int intsrc, sctl;
1102
1103 /* fastpath out, to ease interrupt sharing */
1104 intsrc = inl(s->io+ES1371_REG_STATUS);
1105 if (!(intsrc & 0x80000000))
1106 return;
1107 spin_lock(&s->lock);
1108 /* clear audio interrupts first */
1109 sctl = s->sctrl;
1110 if (intsrc & STAT_ADC)
1111 sctl &= ~SCTRL_R1INTEN;
1112 if (intsrc & STAT_DAC1)
1113 sctl &= ~SCTRL_P1INTEN;
1114 if (intsrc & STAT_DAC2)
1115 sctl &= ~SCTRL_P2INTEN;
1116 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1117 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1118 es1371_update_ptr(s);
1119 es1371_handle_midi(s);
1120 spin_unlock(&s->lock);
1121 }
1122
1123 /* --------------------------------------------------------------------- */
1124
1125 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1126
1127 #define VALIDATE_STATE(s) \
1128 ({ \
1129 if (!(s) || (s)->magic != ES1371_MAGIC) { \
1130 printk(invalid_magic); \
1131 return -ENXIO; \
1132 } \
1133 })
1134
1135 /* --------------------------------------------------------------------- */
1136
1137 /* Conversion table for S/PDIF PCM volume emulation through the SRC */
1138 /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
1139 static const unsigned short DACVolTable[101] =
1140 {
1141 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
1142 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
1143 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
1144 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
1145 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
1146 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
1147 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
1148 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
1149 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
1150 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
1151 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
1152 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
1153 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
1154 };
1155
1156 /*
1157 * when we are in S/PDIF mode, we want to disable any analog output so
1158 * we filter the mixer ioctls
1159 */
1160 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
1161 {
1162 struct es1371_state *s = (struct es1371_state *)codec->private_data;
1163 int val;
1164 unsigned long flags;
1165 unsigned int left, right;
1166
1167 VALIDATE_STATE(s);
1168 /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
1169 if (s->spdif_volume == -1)
1170 return codec->mixer_ioctl(codec, cmd, arg);
1171 switch (cmd) {
1172 case SOUND_MIXER_WRITE_VOLUME:
1173 return 0;
1174
1175 case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
1176 if (get_user(val, (int *)arg))
1177 return -EFAULT;
1178 right = ((val >> 8) & 0xff);
1179 left = (val & 0xff);
1180 if (right > 100)
1181 right = 100;
1182 if (left > 100)
1183 left = 100;
1184 s->spdif_volume = (right << 8) | left;
1185 spin_lock_irqsave(&s->lock, flags);
1186 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
1187 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
1188 spin_unlock_irqrestore(&s->lock, flags);
1189 return 0;
1190
1191 case SOUND_MIXER_READ_PCM:
1192 return put_user(s->spdif_volume, (int *)arg);
1193 }
1194 return codec->mixer_ioctl(codec, cmd, arg);
1195 }
1196
1197 /* --------------------------------------------------------------------- */
1198
1199 /*
1200 * AC97 Mixer Register to Connections mapping of the Concert 97 board
1201 *
1202 * AC97_MASTER_VOL_STEREO Line Out
1203 * AC97_MASTER_VOL_MONO TAD Output
1204 * AC97_PCBEEP_VOL none
1205 * AC97_PHONE_VOL TAD Input (mono)
1206 * AC97_MIC_VOL MIC Input (mono)
1207 * AC97_LINEIN_VOL Line Input (stereo)
1208 * AC97_CD_VOL CD Input (stereo)
1209 * AC97_VIDEO_VOL none
1210 * AC97_AUX_VOL Aux Input (stereo)
1211 * AC97_PCMOUT_VOL Wave Output (stereo)
1212 */
1213
1214 static int es1371_open_mixdev(struct inode *inode, struct file *file)
1215 {
1216 int minor = MINOR(inode->i_rdev);
1217 struct list_head *list;
1218 struct es1371_state *s;
1219
1220 for (list = devs.next; ; list = list->next) {
1221 if (list == &devs)
1222 return -ENODEV;
1223 s = list_entry(list, struct es1371_state, devs);
1224 if (s->codec.dev_mixer == minor)
1225 break;
1226 }
1227 VALIDATE_STATE(s);
1228 file->private_data = s;
1229 return 0;
1230 }
1231
1232 static int es1371_release_mixdev(struct inode *inode, struct file *file)
1233 {
1234 struct es1371_state *s = (struct es1371_state *)file->private_data;
1235
1236 VALIDATE_STATE(s);
1237 return 0;
1238 }
1239
1240 static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1241 {
1242 struct es1371_state *s = (struct es1371_state *)file->private_data;
1243 struct ac97_codec *codec = &s->codec;
1244
1245 return mixdev_ioctl(codec, cmd, arg);
1246 }
1247
1248 static /*const*/ struct file_operations es1371_mixer_fops = {
1249 owner: THIS_MODULE,
1250 llseek: no_llseek,
1251 ioctl: es1371_ioctl_mixdev,
1252 open: es1371_open_mixdev,
1253 release: es1371_release_mixdev,
1254 };
1255
1256 /* --------------------------------------------------------------------- */
1257
1258 static int drain_dac1(struct es1371_state *s, int nonblock)
1259 {
1260 DECLARE_WAITQUEUE(wait, current);
1261 unsigned long flags;
1262 int count, tmo;
1263
1264 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1265 return 0;
1266 add_wait_queue(&s->dma_dac1.wait, &wait);
1267 for (;;) {
1268 __set_current_state(TASK_INTERRUPTIBLE);
1269 spin_lock_irqsave(&s->lock, flags);
1270 count = s->dma_dac1.count;
1271 spin_unlock_irqrestore(&s->lock, flags);
1272 if (count <= 0)
1273 break;
1274 if (signal_pending(current))
1275 break;
1276 if (nonblock) {
1277 remove_wait_queue(&s->dma_dac1.wait, &wait);
1278 set_current_state(TASK_RUNNING);
1279 return -EBUSY;
1280 }
1281 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1282 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1283 if (!schedule_timeout(tmo + 1))
1284 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1285 }
1286 remove_wait_queue(&s->dma_dac1.wait, &wait);
1287 set_current_state(TASK_RUNNING);
1288 if (signal_pending(current))
1289 return -ERESTARTSYS;
1290 return 0;
1291 }
1292
1293 static int drain_dac2(struct es1371_state *s, int nonblock)
1294 {
1295 DECLARE_WAITQUEUE(wait, current);
1296 unsigned long flags;
1297 int count, tmo;
1298
1299 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1300 return 0;
1301 add_wait_queue(&s->dma_dac2.wait, &wait);
1302 for (;;) {
1303 __set_current_state(TASK_UNINTERRUPTIBLE);
1304 spin_lock_irqsave(&s->lock, flags);
1305 count = s->dma_dac2.count;
1306 spin_unlock_irqrestore(&s->lock, flags);
1307 if (count <= 0)
1308 break;
1309 if (signal_pending(current))
1310 break;
1311 if (nonblock) {
1312 remove_wait_queue(&s->dma_dac2.wait, &wait);
1313 set_current_state(TASK_RUNNING);
1314 return -EBUSY;
1315 }
1316 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1317 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1318 if (!schedule_timeout(tmo + 1))
1319 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1320 }
1321 remove_wait_queue(&s->dma_dac2.wait, &wait);
1322 set_current_state(TASK_RUNNING);
1323 if (signal_pending(current))
1324 return -ERESTARTSYS;
1325 return 0;
1326 }
1327
1328 /* --------------------------------------------------------------------- */
1329
1330 static ssize_t es1371_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1331 {
1332 struct es1371_state *s = (struct es1371_state *)file->private_data;
1333 DECLARE_WAITQUEUE(wait, current);
1334 ssize_t ret = 0;
1335 unsigned long flags;
1336 unsigned swptr;
1337 int cnt;
1338
1339 VALIDATE_STATE(s);
1340 if (ppos != &file->f_pos)
1341 return -ESPIPE;
1342 if (s->dma_adc.mapped)
1343 return -ENXIO;
1344 if (!access_ok(VERIFY_WRITE, buffer, count))
1345 return -EFAULT;
1346 down(&s->sem);
1347 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1348 goto out2;
1349
1350 add_wait_queue(&s->dma_adc.wait, &wait);
1351 while (count > 0) {
1352 spin_lock_irqsave(&s->lock, flags);
1353 swptr = s->dma_adc.swptr;
1354 cnt = s->dma_adc.dmasize-swptr;
1355 if (s->dma_adc.count < cnt)
1356 cnt = s->dma_adc.count;
1357 if (cnt <= 0)
1358 __set_current_state(TASK_INTERRUPTIBLE);
1359 spin_unlock_irqrestore(&s->lock, flags);
1360 if (cnt > count)
1361 cnt = count;
1362 if (cnt <= 0) {
1363 if (s->dma_adc.enabled)
1364 start_adc(s);
1365 if (file->f_flags & O_NONBLOCK) {
1366 if (!ret)
1367 ret = -EAGAIN;
1368 goto out;
1369 }
1370 up(&s->sem);
1371 schedule();
1372 if (signal_pending(current)) {
1373 if (!ret)
1374 ret = -ERESTARTSYS;
1375 goto out2;
1376 }
1377 down(&s->sem);
1378 if (s->dma_adc.mapped)
1379 {
1380 ret = -ENXIO;
1381 goto out;
1382 }
1383 continue;
1384 }
1385 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1386 if (!ret)
1387 ret = -EFAULT;
1388 goto out;
1389 }
1390 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1391 spin_lock_irqsave(&s->lock, flags);
1392 s->dma_adc.swptr = swptr;
1393 s->dma_adc.count -= cnt;
1394 spin_unlock_irqrestore(&s->lock, flags);
1395 count -= cnt;
1396 buffer += cnt;
1397 ret += cnt;
1398 if (s->dma_adc.enabled)
1399 start_adc(s);
1400 }
1401 out:
1402 up(&s->sem);
1403 out2:
1404 remove_wait_queue(&s->dma_adc.wait, &wait);
1405 set_current_state(TASK_RUNNING);
1406 return ret;
1407 }
1408
1409 static ssize_t es1371_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1410 {
1411 struct es1371_state *s = (struct es1371_state *)file->private_data;
1412 DECLARE_WAITQUEUE(wait, current);
1413 ssize_t ret;
1414 unsigned long flags;
1415 unsigned swptr;
1416 int cnt;
1417
1418 VALIDATE_STATE(s);
1419 if (ppos != &file->f_pos)
1420 return -ESPIPE;
1421 if (s->dma_dac2.mapped)
1422 return -ENXIO;
1423 if (!access_ok(VERIFY_READ, buffer, count))
1424 return -EFAULT;
1425 down(&s->sem);
1426 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1427 goto out3;
1428 ret = 0;
1429 add_wait_queue(&s->dma_dac2.wait, &wait);
1430 while (count > 0) {
1431 spin_lock_irqsave(&s->lock, flags);
1432 if (s->dma_dac2.count < 0) {
1433 s->dma_dac2.count = 0;
1434 s->dma_dac2.swptr = s->dma_dac2.hwptr;
1435 }
1436 swptr = s->dma_dac2.swptr;
1437 cnt = s->dma_dac2.dmasize-swptr;
1438 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1439 cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1440 if (cnt <= 0)
1441 __set_current_state(TASK_INTERRUPTIBLE);
1442 spin_unlock_irqrestore(&s->lock, flags);
1443 if (cnt > count)
1444 cnt = count;
1445 if (cnt <= 0) {
1446 if (s->dma_dac2.enabled)
1447 start_dac2(s);
1448 if (file->f_flags & O_NONBLOCK) {
1449 if (!ret)
1450 ret = -EAGAIN;
1451 goto out;
1452 }
1453 up(&s->sem);
1454 schedule();
1455 if (signal_pending(current)) {
1456 if (!ret)
1457 ret = -ERESTARTSYS;
1458 goto out2;
1459 }
1460 down(&s->sem);
1461 if (s->dma_dac2.mapped)
1462 {
1463 ret = -ENXIO;
1464 goto out;
1465 }
1466 continue;
1467 }
1468 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1469 if (!ret)
1470 ret = -EFAULT;
1471 goto out;
1472 }
1473 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1474 spin_lock_irqsave(&s->lock, flags);
1475 s->dma_dac2.swptr = swptr;
1476 s->dma_dac2.count += cnt;
1477 s->dma_dac2.endcleared = 0;
1478 spin_unlock_irqrestore(&s->lock, flags);
1479 count -= cnt;
1480 buffer += cnt;
1481 ret += cnt;
1482 if (s->dma_dac2.enabled)
1483 start_dac2(s);
1484 }
1485 out:
1486 up(&s->sem);
1487 out2:
1488 remove_wait_queue(&s->dma_dac2.wait, &wait);
1489 out3:
1490 set_current_state(TASK_RUNNING);
1491 return ret;
1492 }
1493
1494 /* No kernel lock - we have our own spinlock */
1495 static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1496 {
1497 struct es1371_state *s = (struct es1371_state *)file->private_data;
1498 unsigned long flags;
1499 unsigned int mask = 0;
1500
1501 VALIDATE_STATE(s);
1502 if (file->f_mode & FMODE_WRITE) {
1503 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
1504 return 0;
1505 poll_wait(file, &s->dma_dac2.wait, wait);
1506 }
1507 if (file->f_mode & FMODE_READ) {
1508 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1509 return 0;
1510 poll_wait(file, &s->dma_adc.wait, wait);
1511 }
1512 spin_lock_irqsave(&s->lock, flags);
1513 es1371_update_ptr(s);
1514 if (file->f_mode & FMODE_READ) {
1515 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1516 mask |= POLLIN | POLLRDNORM;
1517 }
1518 if (file->f_mode & FMODE_WRITE) {
1519 if (s->dma_dac2.mapped) {
1520 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1521 mask |= POLLOUT | POLLWRNORM;
1522 } else {
1523 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1524 mask |= POLLOUT | POLLWRNORM;
1525 }
1526 }
1527 spin_unlock_irqrestore(&s->lock, flags);
1528 return mask;
1529 }
1530
1531 static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1532 {
1533 struct es1371_state *s = (struct es1371_state *)file->private_data;
1534 struct dmabuf *db;
1535 int ret = 0;
1536 unsigned long size;
1537
1538 VALIDATE_STATE(s);
1539 lock_kernel();
1540 down(&s->sem);
1541
1542 if (vma->vm_flags & VM_WRITE) {
1543 if ((ret = prog_dmabuf_dac2(s)) != 0) {
1544 goto out;
1545 }
1546 db = &s->dma_dac2;
1547 } else if (vma->vm_flags & VM_READ) {
1548 if ((ret = prog_dmabuf_adc(s)) != 0) {
1549 goto out;
1550 }
1551 db = &s->dma_adc;
1552 } else {
1553 ret = -EINVAL;
1554 goto out;
1555 }
1556 if (vma->vm_pgoff != 0) {
1557 ret = -EINVAL;
1558 goto out;
1559 }
1560 size = vma->vm_end - vma->vm_start;
1561 if (size > (PAGE_SIZE << db->buforder)) {
1562 ret = -EINVAL;
1563 goto out;
1564 }
1565 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot)) {
1566 ret = -EAGAIN;
1567 goto out;
1568 }
1569 db->mapped = 1;
1570 out:
1571 up(&s->sem);
1572 unlock_kernel();
1573 return ret;
1574 }
1575
1576 static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1577 {
1578 struct es1371_state *s = (struct es1371_state *)file->private_data;
1579 unsigned long flags;
1580 audio_buf_info abinfo;
1581 count_info cinfo;
1582 int count;
1583 int val, mapped, ret;
1584
1585 VALIDATE_STATE(s);
1586 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1587 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1588 switch (cmd) {
1589 case OSS_GETVERSION:
1590 return put_user(SOUND_VERSION, (int *)arg);
1591
1592 case SNDCTL_DSP_SYNC:
1593 if (file->f_mode & FMODE_WRITE)
1594 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1595 return 0;
1596
1597 case SNDCTL_DSP_SETDUPLEX:
1598 return 0;
1599
1600 case SNDCTL_DSP_GETCAPS:
1601 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1602
1603 case SNDCTL_DSP_RESET:
1604 if (file->f_mode & FMODE_WRITE) {
1605 stop_dac2(s);
1606 synchronize_irq();
1607 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1608 }
1609 if (file->f_mode & FMODE_READ) {
1610 stop_adc(s);
1611 synchronize_irq();
1612 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1613 }
1614 return 0;
1615
1616 case SNDCTL_DSP_SPEED:
1617 if (get_user(val, (int *)arg))
1618 return -EFAULT;
1619 if (val >= 0) {
1620 if (file->f_mode & FMODE_READ) {
1621 stop_adc(s);
1622 s->dma_adc.ready = 0;
1623 set_adc_rate(s, val);
1624 }
1625 if (file->f_mode & FMODE_WRITE) {
1626 stop_dac2(s);
1627 s->dma_dac2.ready = 0;
1628 set_dac2_rate(s, val);
1629 }
1630 }
1631 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1632
1633 case SNDCTL_DSP_STEREO:
1634 if (get_user(val, (int *)arg))
1635 return -EFAULT;
1636 if (file->f_mode & FMODE_READ) {
1637 stop_adc(s);
1638 s->dma_adc.ready = 0;
1639 spin_lock_irqsave(&s->lock, flags);
1640 if (val)
1641 s->sctrl |= SCTRL_R1SMB;
1642 else
1643 s->sctrl &= ~SCTRL_R1SMB;
1644 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1645 spin_unlock_irqrestore(&s->lock, flags);
1646 }
1647 if (file->f_mode & FMODE_WRITE) {
1648 stop_dac2(s);
1649 s->dma_dac2.ready = 0;
1650 spin_lock_irqsave(&s->lock, flags);
1651 if (val)
1652 s->sctrl |= SCTRL_P2SMB;
1653 else
1654 s->sctrl &= ~SCTRL_P2SMB;
1655 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1656 spin_unlock_irqrestore(&s->lock, flags);
1657 }
1658 return 0;
1659
1660 case SNDCTL_DSP_CHANNELS:
1661 if (get_user(val, (int *)arg))
1662 return -EFAULT;
1663 if (val != 0) {
1664 if (file->f_mode & FMODE_READ) {
1665 stop_adc(s);
1666 s->dma_adc.ready = 0;
1667 spin_lock_irqsave(&s->lock, flags);
1668 if (val >= 2)
1669 s->sctrl |= SCTRL_R1SMB;
1670 else
1671 s->sctrl &= ~SCTRL_R1SMB;
1672 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1673 spin_unlock_irqrestore(&s->lock, flags);
1674 }
1675 if (file->f_mode & FMODE_WRITE) {
1676 stop_dac2(s);
1677 s->dma_dac2.ready = 0;
1678 spin_lock_irqsave(&s->lock, flags);
1679 if (val >= 2)
1680 s->sctrl |= SCTRL_P2SMB;
1681 else
1682 s->sctrl &= ~SCTRL_P2SMB;
1683 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1684 spin_unlock_irqrestore(&s->lock, flags);
1685 }
1686 }
1687 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1688
1689 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1690 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
1691
1692 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1693 if (get_user(val, (int *)arg))
1694 return -EFAULT;
1695 if (val != AFMT_QUERY) {
1696 if (file->f_mode & FMODE_READ) {
1697 stop_adc(s);
1698 s->dma_adc.ready = 0;
1699 spin_lock_irqsave(&s->lock, flags);
1700 if (val == AFMT_S16_LE)
1701 s->sctrl |= SCTRL_R1SEB;
1702 else
1703 s->sctrl &= ~SCTRL_R1SEB;
1704 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1705 spin_unlock_irqrestore(&s->lock, flags);
1706 }
1707 if (file->f_mode & FMODE_WRITE) {
1708 stop_dac2(s);
1709 s->dma_dac2.ready = 0;
1710 spin_lock_irqsave(&s->lock, flags);
1711 if (val == AFMT_S16_LE)
1712 s->sctrl |= SCTRL_P2SEB;
1713 else
1714 s->sctrl &= ~SCTRL_P2SEB;
1715 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1716 spin_unlock_irqrestore(&s->lock, flags);
1717 }
1718 }
1719 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
1720 AFMT_S16_LE : AFMT_U8, (int *)arg);
1721
1722 case SNDCTL_DSP_POST:
1723 return 0;
1724
1725 case SNDCTL_DSP_GETTRIGGER:
1726 val = 0;
1727 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
1728 val |= PCM_ENABLE_INPUT;
1729 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
1730 val |= PCM_ENABLE_OUTPUT;
1731 return put_user(val, (int *)arg);
1732
1733 case SNDCTL_DSP_SETTRIGGER:
1734 if (get_user(val, (int *)arg))
1735 return -EFAULT;
1736 if (file->f_mode & FMODE_READ) {
1737 if (val & PCM_ENABLE_INPUT) {
1738 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1739 return ret;
1740 s->dma_adc.enabled = 1;
1741 start_adc(s);
1742 } else {
1743 s->dma_adc.enabled = 0;
1744 stop_adc(s);
1745 }
1746 }
1747 if (file->f_mode & FMODE_WRITE) {
1748 if (val & PCM_ENABLE_OUTPUT) {
1749 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1750 return ret;
1751 s->dma_dac2.enabled = 1;
1752 start_dac2(s);
1753 } else {
1754 s->dma_dac2.enabled = 0;
1755 stop_dac2(s);
1756 }
1757 }
1758 return 0;
1759
1760 case SNDCTL_DSP_GETOSPACE:
1761 if (!(file->f_mode & FMODE_WRITE))
1762 return -EINVAL;
1763 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1764 return val;
1765 spin_lock_irqsave(&s->lock, flags);
1766 es1371_update_ptr(s);
1767 abinfo.fragsize = s->dma_dac2.fragsize;
1768 count = s->dma_dac2.count;
1769 if (count < 0)
1770 count = 0;
1771 abinfo.bytes = s->dma_dac2.dmasize - count;
1772 abinfo.fragstotal = s->dma_dac2.numfrag;
1773 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
1774 spin_unlock_irqrestore(&s->lock, flags);
1775 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1776
1777 case SNDCTL_DSP_GETISPACE:
1778 if (!(file->f_mode & FMODE_READ))
1779 return -EINVAL;
1780 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1781 return val;
1782 spin_lock_irqsave(&s->lock, flags);
1783 es1371_update_ptr(s);
1784 abinfo.fragsize = s->dma_adc.fragsize;
1785 count = s->dma_adc.count;
1786 if (count < 0)
1787 count = 0;
1788 abinfo.bytes = count;
1789 abinfo.fragstotal = s->dma_adc.numfrag;
1790 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1791 spin_unlock_irqrestore(&s->lock, flags);
1792 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1793
1794 case SNDCTL_DSP_NONBLOCK:
1795 file->f_flags |= O_NONBLOCK;
1796 return 0;
1797
1798 case SNDCTL_DSP_GETODELAY:
1799 if (!(file->f_mode & FMODE_WRITE))
1800 return -EINVAL;
1801 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1802 return val;
1803 spin_lock_irqsave(&s->lock, flags);
1804 es1371_update_ptr(s);
1805 count = s->dma_dac2.count;
1806 spin_unlock_irqrestore(&s->lock, flags);
1807 if (count < 0)
1808 count = 0;
1809 return put_user(count, (int *)arg);
1810
1811 case SNDCTL_DSP_GETIPTR:
1812 if (!(file->f_mode & FMODE_READ))
1813 return -EINVAL;
1814 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1815 return val;
1816 spin_lock_irqsave(&s->lock, flags);
1817 es1371_update_ptr(s);
1818 cinfo.bytes = s->dma_adc.total_bytes;
1819 count = s->dma_adc.count;
1820 if (count < 0)
1821 count = 0;
1822 cinfo.blocks = count >> s->dma_adc.fragshift;
1823 cinfo.ptr = s->dma_adc.hwptr;
1824 if (s->dma_adc.mapped)
1825 s->dma_adc.count &= s->dma_adc.fragsize-1;
1826 spin_unlock_irqrestore(&s->lock, flags);
1827 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1828
1829 case SNDCTL_DSP_GETOPTR:
1830 if (!(file->f_mode & FMODE_WRITE))
1831 return -EINVAL;
1832 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1833 return val;
1834 spin_lock_irqsave(&s->lock, flags);
1835 es1371_update_ptr(s);
1836 cinfo.bytes = s->dma_dac2.total_bytes;
1837 count = s->dma_dac2.count;
1838 if (count < 0)
1839 count = 0;
1840 cinfo.blocks = count >> s->dma_dac2.fragshift;
1841 cinfo.ptr = s->dma_dac2.hwptr;
1842 if (s->dma_dac2.mapped)
1843 s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1844 spin_unlock_irqrestore(&s->lock, flags);
1845 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1846
1847 case SNDCTL_DSP_GETBLKSIZE:
1848 if (file->f_mode & FMODE_WRITE) {
1849 if ((val = prog_dmabuf_dac2(s)))
1850 return val;
1851 return put_user(s->dma_dac2.fragsize, (int *)arg);
1852 }
1853 if ((val = prog_dmabuf_adc(s)))
1854 return val;
1855 return put_user(s->dma_adc.fragsize, (int *)arg);
1856
1857 case SNDCTL_DSP_SETFRAGMENT:
1858 if (get_user(val, (int *)arg))
1859 return -EFAULT;
1860 if (file->f_mode & FMODE_READ) {
1861 s->dma_adc.ossfragshift = val & 0xffff;
1862 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1863 if (s->dma_adc.ossfragshift < 4)
1864 s->dma_adc.ossfragshift = 4;
1865 if (s->dma_adc.ossfragshift > 15)
1866 s->dma_adc.ossfragshift = 15;
1867 if (s->dma_adc.ossmaxfrags < 4)
1868 s->dma_adc.ossmaxfrags = 4;
1869 }
1870 if (file->f_mode & FMODE_WRITE) {
1871 s->dma_dac2.ossfragshift = val & 0xffff;
1872 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1873 if (s->dma_dac2.ossfragshift < 4)
1874 s->dma_dac2.ossfragshift = 4;
1875 if (s->dma_dac2.ossfragshift > 15)
1876 s->dma_dac2.ossfragshift = 15;
1877 if (s->dma_dac2.ossmaxfrags < 4)
1878 s->dma_dac2.ossmaxfrags = 4;
1879 }
1880 return 0;
1881
1882 case SNDCTL_DSP_SUBDIVIDE:
1883 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1884 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1885 return -EINVAL;
1886 if (get_user(val, (int *)arg))
1887 return -EFAULT;
1888 if (val != 1 && val != 2 && val != 4)
1889 return -EINVAL;
1890 if (file->f_mode & FMODE_READ)
1891 s->dma_adc.subdivision = val;
1892 if (file->f_mode & FMODE_WRITE)
1893 s->dma_dac2.subdivision = val;
1894 return 0;
1895
1896 case SOUND_PCM_READ_RATE:
1897 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1898
1899 case SOUND_PCM_READ_CHANNELS:
1900 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1901
1902 case SOUND_PCM_READ_BITS:
1903 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, (int *)arg);
1904
1905 case SOUND_PCM_WRITE_FILTER:
1906 case SNDCTL_DSP_SETSYNCRO:
1907 case SOUND_PCM_READ_FILTER:
1908 return -EINVAL;
1909
1910 }
1911 return mixdev_ioctl(&s->codec, cmd, arg);
1912 }
1913
1914 static int es1371_open(struct inode *inode, struct file *file)
1915 {
1916 int minor = MINOR(inode->i_rdev);
1917 DECLARE_WAITQUEUE(wait, current);
1918 unsigned long flags;
1919 struct list_head *list;
1920 struct es1371_state *s;
1921
1922 for (list = devs.next; ; list = list->next) {
1923 if (list == &devs)
1924 return -ENODEV;
1925 s = list_entry(list, struct es1371_state, devs);
1926 if (!((s->dev_audio ^ minor) & ~0xf))
1927 break;
1928 }
1929 VALIDATE_STATE(s);
1930 file->private_data = s;
1931 /* wait for device to become free */
1932 down(&s->open_sem);
1933 while (s->open_mode & file->f_mode) {
1934 if (file->f_flags & O_NONBLOCK) {
1935 up(&s->open_sem);
1936 return -EBUSY;
1937 }
1938 add_wait_queue(&s->open_wait, &wait);
1939 __set_current_state(TASK_INTERRUPTIBLE);
1940 up(&s->open_sem);
1941 schedule();
1942 remove_wait_queue(&s->open_wait, &wait);
1943 set_current_state(TASK_RUNNING);
1944 if (signal_pending(current))
1945 return -ERESTARTSYS;
1946 down(&s->open_sem);
1947 }
1948 if (file->f_mode & FMODE_READ) {
1949 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1950 s->dma_adc.enabled = 1;
1951 set_adc_rate(s, 8000);
1952 }
1953 if (file->f_mode & FMODE_WRITE) {
1954 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1955 s->dma_dac2.enabled = 1;
1956 set_dac2_rate(s, 8000);
1957 }
1958 spin_lock_irqsave(&s->lock, flags);
1959 if (file->f_mode & FMODE_READ) {
1960 s->sctrl &= ~SCTRL_R1FMT;
1961 if ((minor & 0xf) == SND_DEV_DSP16)
1962 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1963 else
1964 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1965 }
1966 if (file->f_mode & FMODE_WRITE) {
1967 s->sctrl &= ~SCTRL_P2FMT;
1968 if ((minor & 0xf) == SND_DEV_DSP16)
1969 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1970 else
1971 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1972 }
1973 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1974 spin_unlock_irqrestore(&s->lock, flags);
1975 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1976 up(&s->open_sem);
1977 init_MUTEX(&s->sem);
1978 return 0;
1979 }
1980
1981 static int es1371_release(struct inode *inode, struct file *file)
1982 {
1983 struct es1371_state *s = (struct es1371_state *)file->private_data;
1984
1985 VALIDATE_STATE(s);
1986 lock_kernel();
1987 if (file->f_mode & FMODE_WRITE)
1988 drain_dac2(s, file->f_flags & O_NONBLOCK);
1989 down(&s->open_sem);
1990 if (file->f_mode & FMODE_WRITE) {
1991 stop_dac2(s);
1992 dealloc_dmabuf(s, &s->dma_dac2);
1993 }
1994 if (file->f_mode & FMODE_READ) {
1995 stop_adc(s);
1996 dealloc_dmabuf(s, &s->dma_adc);
1997 }
1998 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
1999 up(&s->open_sem);
2000 wake_up(&s->open_wait);
2001 unlock_kernel();
2002 return 0;
2003 }
2004
2005 static /*const*/ struct file_operations es1371_audio_fops = {
2006 owner: THIS_MODULE,
2007 llseek: no_llseek,
2008 read: es1371_read,
2009 write: es1371_write,
2010 poll: es1371_poll,
2011 ioctl: es1371_ioctl,
2012 mmap: es1371_mmap,
2013 open: es1371_open,
2014 release: es1371_release,
2015 };
2016
2017 /* --------------------------------------------------------------------- */
2018
2019 static ssize_t es1371_write_dac(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2020 {
2021 struct es1371_state *s = (struct es1371_state *)file->private_data;
2022 DECLARE_WAITQUEUE(wait, current);
2023 ssize_t ret = 0;
2024 unsigned long flags;
2025 unsigned swptr;
2026 int cnt;
2027
2028 VALIDATE_STATE(s);
2029 if (ppos != &file->f_pos)
2030 return -ESPIPE;
2031 if (s->dma_dac1.mapped)
2032 return -ENXIO;
2033 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2034 return ret;
2035 if (!access_ok(VERIFY_READ, buffer, count))
2036 return -EFAULT;
2037 add_wait_queue(&s->dma_dac1.wait, &wait);
2038 while (count > 0) {
2039 spin_lock_irqsave(&s->lock, flags);
2040 if (s->dma_dac1.count < 0) {
2041 s->dma_dac1.count = 0;
2042 s->dma_dac1.swptr = s->dma_dac1.hwptr;
2043 }
2044 swptr = s->dma_dac1.swptr;
2045 cnt = s->dma_dac1.dmasize-swptr;
2046 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
2047 cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
2048 if (cnt <= 0)
2049 __set_current_state(TASK_INTERRUPTIBLE);
2050 spin_unlock_irqrestore(&s->lock, flags);
2051 if (cnt > count)
2052 cnt = count;
2053 if (cnt <= 0) {
2054 if (s->dma_dac1.enabled)
2055 start_dac1(s);
2056 if (file->f_flags & O_NONBLOCK) {
2057 if (!ret)
2058 ret = -EAGAIN;
2059 break;
2060 }
2061 schedule();
2062 if (signal_pending(current)) {
2063 if (!ret)
2064 ret = -ERESTARTSYS;
2065 break;
2066 }
2067 continue;
2068 }
2069 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
2070 if (!ret)
2071 ret = -EFAULT;
2072 break;
2073 }
2074 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
2075 spin_lock_irqsave(&s->lock, flags);
2076 s->dma_dac1.swptr = swptr;
2077 s->dma_dac1.count += cnt;
2078 s->dma_dac1.endcleared = 0;
2079 spin_unlock_irqrestore(&s->lock, flags);
2080 count -= cnt;
2081 buffer += cnt;
2082 ret += cnt;
2083 if (s->dma_dac1.enabled)
2084 start_dac1(s);
2085 }
2086 remove_wait_queue(&s->dma_dac1.wait, &wait);
2087 set_current_state(TASK_RUNNING);
2088 return ret;
2089 }
2090
2091 /* No kernel lock - we have our own spinlock */
2092 static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
2093 {
2094 struct es1371_state *s = (struct es1371_state *)file->private_data;
2095 unsigned long flags;
2096 unsigned int mask = 0;
2097
2098 VALIDATE_STATE(s);
2099 if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
2100 return 0;
2101 poll_wait(file, &s->dma_dac1.wait, wait);
2102 spin_lock_irqsave(&s->lock, flags);
2103 es1371_update_ptr(s);
2104 if (s->dma_dac1.mapped) {
2105 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
2106 mask |= POLLOUT | POLLWRNORM;
2107 } else {
2108 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
2109 mask |= POLLOUT | POLLWRNORM;
2110 }
2111 spin_unlock_irqrestore(&s->lock, flags);
2112 return mask;
2113 }
2114
2115 static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
2116 {
2117 struct es1371_state *s = (struct es1371_state *)file->private_data;
2118 int ret;
2119 unsigned long size;
2120
2121 VALIDATE_STATE(s);
2122 if (!(vma->vm_flags & VM_WRITE))
2123 return -EINVAL;
2124 lock_kernel();
2125 if ((ret = prog_dmabuf_dac1(s)) != 0)
2126 goto out;
2127 ret = -EINVAL;
2128 if (vma->vm_pgoff != 0)
2129 goto out;
2130 size = vma->vm_end - vma->vm_start;
2131 if (size > (PAGE_SIZE << s->dma_dac1.buforder))
2132 goto out;
2133 ret = -EAGAIN;
2134 if (remap_page_range(vma->vm_start, virt_to_phys(s->dma_dac1.rawbuf), size, vma->vm_page_prot))
2135 goto out;
2136 s->dma_dac1.mapped = 1;
2137 ret = 0;
2138 out:
2139 unlock_kernel();
2140 return ret;
2141 }
2142
2143 static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2144 {
2145 struct es1371_state *s = (struct es1371_state *)file->private_data;
2146 unsigned long flags;
2147 audio_buf_info abinfo;
2148 count_info cinfo;
2149 int count;
2150 int val, ret;
2151
2152 VALIDATE_STATE(s);
2153 switch (cmd) {
2154 case OSS_GETVERSION:
2155 return put_user(SOUND_VERSION, (int *)arg);
2156
2157 case SNDCTL_DSP_SYNC:
2158 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2159
2160 case SNDCTL_DSP_SETDUPLEX:
2161 return -EINVAL;
2162
2163 case SNDCTL_DSP_GETCAPS:
2164 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
2165
2166 case SNDCTL_DSP_RESET:
2167 stop_dac1(s);
2168 synchronize_irq();
2169 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2170 return 0;
2171
2172 case SNDCTL_DSP_SPEED:
2173 if (get_user(val, (int *)arg))
2174 return -EFAULT;
2175 if (val >= 0) {
2176 stop_dac1(s);
2177 s->dma_dac1.ready = 0;
2178 set_dac1_rate(s, val);
2179 }
2180 return put_user(s->dac1rate, (int *)arg);
2181
2182 case SNDCTL_DSP_STEREO:
2183 if (get_user(val, (int *)arg))
2184 return -EFAULT;
2185 stop_dac1(s);
2186 s->dma_dac1.ready = 0;
2187 spin_lock_irqsave(&s->lock, flags);
2188 if (val)
2189 s->sctrl |= SCTRL_P1SMB;
2190 else
2191 s->sctrl &= ~SCTRL_P1SMB;
2192 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2193 spin_unlock_irqrestore(&s->lock, flags);
2194 return 0;
2195
2196 case SNDCTL_DSP_CHANNELS:
2197 if (get_user(val, (int *)arg))
2198 return -EFAULT;
2199 if (val != 0) {
2200 stop_dac1(s);
2201 s->dma_dac1.ready = 0;
2202 spin_lock_irqsave(&s->lock, flags);
2203 if (val >= 2)
2204 s->sctrl |= SCTRL_P1SMB;
2205 else
2206 s->sctrl &= ~SCTRL_P1SMB;
2207 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2208 spin_unlock_irqrestore(&s->lock, flags);
2209 }
2210 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2211
2212 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2213 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
2214
2215 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2216 if (get_user(val, (int *)arg))
2217 return -EFAULT;
2218 if (val != AFMT_QUERY) {
2219 stop_dac1(s);
2220 s->dma_dac1.ready = 0;
2221 spin_lock_irqsave(&s->lock, flags);
2222 if (val == AFMT_S16_LE)
2223 s->sctrl |= SCTRL_P1SEB;
2224 else
2225 s->sctrl &= ~SCTRL_P1SEB;
2226 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2227 spin_unlock_irqrestore(&s->lock, flags);
2228 }
2229 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, (int *)arg);
2230
2231 case SNDCTL_DSP_POST:
2232 return 0;
2233
2234 case SNDCTL_DSP_GETTRIGGER:
2235 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, (int *)arg);
2236
2237 case SNDCTL_DSP_SETTRIGGER:
2238 if (get_user(val, (int *)arg))
2239 return -EFAULT;
2240 if (val & PCM_ENABLE_OUTPUT) {
2241 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2242 return ret;
2243 s->dma_dac1.enabled = 1;
2244 start_dac1(s);
2245 } else {
2246 s->dma_dac1.enabled = 0;
2247 stop_dac1(s);
2248 }
2249 return 0;
2250
2251 case SNDCTL_DSP_GETOSPACE:
2252 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2253 return val;
2254 spin_lock_irqsave(&s->lock, flags);
2255 es1371_update_ptr(s);
2256 abinfo.fragsize = s->dma_dac1.fragsize;
2257 count = s->dma_dac1.count;
2258 if (count < 0)
2259 count = 0;
2260 abinfo.bytes = s->dma_dac1.dmasize - count;
2261 abinfo.fragstotal = s->dma_dac1.numfrag;
2262 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
2263 spin_unlock_irqrestore(&s->lock, flags);
2264 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2265
2266 case SNDCTL_DSP_NONBLOCK:
2267 file->f_flags |= O_NONBLOCK;
2268 return 0;
2269
2270 case SNDCTL_DSP_GETODELAY:
2271 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2272 return val;
2273 spin_lock_irqsave(&s->lock, flags);
2274 es1371_update_ptr(s);
2275 count = s->dma_dac1.count;
2276 spin_unlock_irqrestore(&s->lock, flags);
2277 if (count < 0)
2278 count = 0;
2279 return put_user(count, (int *)arg);
2280
2281 case SNDCTL_DSP_GETOPTR:
2282 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2283 return val;
2284 spin_lock_irqsave(&s->lock, flags);
2285 es1371_update_ptr(s);
2286 cinfo.bytes = s->dma_dac1.total_bytes;
2287 count = s->dma_dac1.count;
2288 if (count < 0)
2289 count = 0;
2290 cinfo.blocks = count >> s->dma_dac1.fragshift;
2291 cinfo.ptr = s->dma_dac1.hwptr;
2292 if (s->dma_dac1.mapped)
2293 s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2294 spin_unlock_irqrestore(&s->lock, flags);
2295 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2296
2297 case SNDCTL_DSP_GETBLKSIZE:
2298 if ((val = prog_dmabuf_dac1(s)))
2299 return val;
2300 return put_user(s->dma_dac1.fragsize, (int *)arg);
2301
2302 case SNDCTL_DSP_SETFRAGMENT:
2303 if (get_user(val, (int *)arg))
2304 return -EFAULT;
2305 s->dma_dac1.ossfragshift = val & 0xffff;
2306 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2307 if (s->dma_dac1.ossfragshift < 4)
2308 s->dma_dac1.ossfragshift = 4;
2309 if (s->dma_dac1.ossfragshift > 15)
2310 s->dma_dac1.ossfragshift = 15;
2311 if (s->dma_dac1.ossmaxfrags < 4)
2312 s->dma_dac1.ossmaxfrags = 4;
2313 return 0;
2314
2315 case SNDCTL_DSP_SUBDIVIDE:
2316 if (s->dma_dac1.subdivision)
2317 return -EINVAL;
2318 if (get_user(val, (int *)arg))
2319 return -EFAULT;
2320 if (val != 1 && val != 2 && val != 4)
2321 return -EINVAL;
2322 s->dma_dac1.subdivision = val;
2323 return 0;
2324
2325 case SOUND_PCM_READ_RATE:
2326 return put_user(s->dac1rate, (int *)arg);
2327
2328 case SOUND_PCM_READ_CHANNELS:
2329 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2330
2331 case SOUND_PCM_READ_BITS:
2332 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, (int *)arg);
2333
2334 case SOUND_PCM_WRITE_FILTER:
2335 case SNDCTL_DSP_SETSYNCRO:
2336 case SOUND_PCM_READ_FILTER:
2337 return -EINVAL;
2338
2339 }
2340 return mixdev_ioctl(&s->codec, cmd, arg);
2341 }
2342
2343 static int es1371_open_dac(struct inode *inode, struct file *file)
2344 {
2345 int minor = MINOR(inode->i_rdev);
2346 DECLARE_WAITQUEUE(wait, current);
2347 unsigned long flags;
2348 struct list_head *list;
2349 struct es1371_state *s;
2350
2351 for (list = devs.next; ; list = list->next) {
2352 if (list == &devs)
2353 return -ENODEV;
2354 s = list_entry(list, struct es1371_state, devs);
2355 if (!((s->dev_dac ^ minor) & ~0xf))
2356 break;
2357 }
2358 VALIDATE_STATE(s);
2359 /* we allow opening with O_RDWR, most programs do it although they will only write */
2360 #if 0
2361 if (file->f_mode & FMODE_READ)
2362 return -EPERM;
2363 #endif
2364 if (!(file->f_mode & FMODE_WRITE))
2365 return -EINVAL;
2366 file->private_data = s;
2367 /* wait for device to become free */
2368 down(&s->open_sem);
2369 while (s->open_mode & FMODE_DAC) {
2370 if (file->f_flags & O_NONBLOCK) {
2371 up(&s->open_sem);
2372 return -EBUSY;
2373 }
2374 add_wait_queue(&s->open_wait, &wait);
2375 __set_current_state(TASK_INTERRUPTIBLE);
2376 up(&s->open_sem);
2377 schedule();
2378 remove_wait_queue(&s->open_wait, &wait);
2379 set_current_state(TASK_RUNNING);
2380 if (signal_pending(current))
2381 return -ERESTARTSYS;
2382 down(&s->open_sem);
2383 }
2384 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2385 s->dma_dac1.enabled = 1;
2386 set_dac1_rate(s, 8000);
2387 spin_lock_irqsave(&s->lock, flags);
2388 s->sctrl &= ~SCTRL_P1FMT;
2389 if ((minor & 0xf) == SND_DEV_DSP16)
2390 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2391 else
2392 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2393 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2394 spin_unlock_irqrestore(&s->lock, flags);
2395 s->open_mode |= FMODE_DAC;
2396 up(&s->open_sem);
2397 return 0;
2398 }
2399
2400 static int es1371_release_dac(struct inode *inode, struct file *file)
2401 {
2402 struct es1371_state *s = (struct es1371_state *)file->private_data;
2403
2404 VALIDATE_STATE(s);
2405 lock_kernel();
2406 drain_dac1(s, file->f_flags & O_NONBLOCK);
2407 down(&s->open_sem);
2408 stop_dac1(s);
2409 dealloc_dmabuf(s, &s->dma_dac1);
2410 s->open_mode &= ~FMODE_DAC;
2411 up(&s->open_sem);
2412 wake_up(&s->open_wait);
2413 unlock_kernel();
2414 return 0;
2415 }
2416
2417 static /*const*/ struct file_operations es1371_dac_fops = {
2418 owner: THIS_MODULE,
2419 llseek: no_llseek,
2420 write: es1371_write_dac,
2421 poll: es1371_poll_dac,
2422 ioctl: es1371_ioctl_dac,
2423 mmap: es1371_mmap_dac,
2424 open: es1371_open_dac,
2425 release: es1371_release_dac,
2426 };
2427
2428 /* --------------------------------------------------------------------- */
2429
2430 static ssize_t es1371_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
2431 {
2432 struct es1371_state *s = (struct es1371_state *)file->private_data;
2433 DECLARE_WAITQUEUE(wait, current);
2434 ssize_t ret;
2435 unsigned long flags;
2436 unsigned ptr;
2437 int cnt;
2438
2439 VALIDATE_STATE(s);
2440 if (ppos != &file->f_pos)
2441 return -ESPIPE;
2442 if (!access_ok(VERIFY_WRITE, buffer, count))
2443 return -EFAULT;
2444 if (count == 0)
2445 return 0;
2446 ret = 0;
2447 add_wait_queue(&s->midi.iwait, &wait);
2448 while (count > 0) {
2449 spin_lock_irqsave(&s->lock, flags);
2450 ptr = s->midi.ird;
2451 cnt = MIDIINBUF - ptr;
2452 if (s->midi.icnt < cnt)
2453 cnt = s->midi.icnt;
2454 if (cnt <= 0)
2455 __set_current_state(TASK_INTERRUPTIBLE);
2456 spin_unlock_irqrestore(&s->lock, flags);
2457 if (cnt > count)
2458 cnt = count;
2459 if (cnt <= 0) {
2460 if (file->f_flags & O_NONBLOCK) {
2461 if (!ret)
2462 ret = -EAGAIN;
2463 break;
2464 }
2465 schedule();
2466 if (signal_pending(current)) {
2467 if (!ret)
2468 ret = -ERESTARTSYS;
2469 break;
2470 }
2471 continue;
2472 }
2473 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2474 if (!ret)
2475 ret = -EFAULT;
2476 break;
2477 }
2478 ptr = (ptr + cnt) % MIDIINBUF;
2479 spin_lock_irqsave(&s->lock, flags);
2480 s->midi.ird = ptr;
2481 s->midi.icnt -= cnt;
2482 spin_unlock_irqrestore(&s->lock, flags);
2483 count -= cnt;
2484 buffer += cnt;
2485 ret += cnt;
2486 break;
2487 }
2488 __set_current_state(TASK_RUNNING);
2489 remove_wait_queue(&s->midi.iwait, &wait);
2490 return ret;
2491 }
2492
2493 static ssize_t es1371_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2494 {
2495 struct es1371_state *s = (struct es1371_state *)file->private_data;
2496 DECLARE_WAITQUEUE(wait, current);
2497 ssize_t ret;
2498 unsigned long flags;
2499 unsigned ptr;
2500 int cnt;
2501
2502 VALIDATE_STATE(s);
2503 if (ppos != &file->f_pos)
2504 return -ESPIPE;
2505 if (!access_ok(VERIFY_READ, buffer, count))
2506 return -EFAULT;
2507 if (count == 0)
2508 return 0;
2509 ret = 0;
2510 add_wait_queue(&s->midi.owait, &wait);
2511 while (count > 0) {
2512 spin_lock_irqsave(&s->lock, flags);
2513 ptr = s->midi.owr;
2514 cnt = MIDIOUTBUF - ptr;
2515 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2516 cnt = MIDIOUTBUF - s->midi.ocnt;
2517 if (cnt <= 0) {
2518 __set_current_state(TASK_INTERRUPTIBLE);
2519 es1371_handle_midi(s);
2520 }
2521 spin_unlock_irqrestore(&s->lock, flags);
2522 if (cnt > count)
2523 cnt = count;
2524 if (cnt <= 0) {
2525 if (file->f_flags & O_NONBLOCK) {
2526 if (!ret)
2527 ret = -EAGAIN;
2528 break;
2529 }
2530 schedule();
2531 if (signal_pending(current)) {
2532 if (!ret)
2533 ret = -ERESTARTSYS;
2534 break;
2535 }
2536 continue;
2537 }
2538 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2539 if (!ret)
2540 ret = -EFAULT;
2541 break;
2542 }
2543 ptr = (ptr + cnt) % MIDIOUTBUF;
2544 spin_lock_irqsave(&s->lock, flags);
2545 s->midi.owr = ptr;
2546 s->midi.ocnt += cnt;
2547 spin_unlock_irqrestore(&s->lock, flags);
2548 count -= cnt;
2549 buffer += cnt;
2550 ret += cnt;
2551 spin_lock_irqsave(&s->lock, flags);
2552 es1371_handle_midi(s);
2553 spin_unlock_irqrestore(&s->lock, flags);
2554 }
2555 __set_current_state(TASK_RUNNING);
2556 remove_wait_queue(&s->midi.owait, &wait);
2557 return ret;
2558 }
2559
2560 /* No kernel lock - we have our own spinlock */
2561 static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2562 {
2563 struct es1371_state *s = (struct es1371_state *)file->private_data;
2564 unsigned long flags;
2565 unsigned int mask = 0;
2566
2567 VALIDATE_STATE(s);
2568 if (file->f_mode & FMODE_WRITE)
2569 poll_wait(file, &s->midi.owait, wait);
2570 if (file->f_mode & FMODE_READ)
2571 poll_wait(file, &s->midi.iwait, wait);
2572 spin_lock_irqsave(&s->lock, flags);
2573 if (file->f_mode & FMODE_READ) {
2574 if (s->midi.icnt > 0)
2575 mask |= POLLIN | POLLRDNORM;
2576 }
2577 if (file->f_mode & FMODE_WRITE) {
2578 if (s->midi.ocnt < MIDIOUTBUF)
2579 mask |= POLLOUT | POLLWRNORM;
2580 }
2581 spin_unlock_irqrestore(&s->lock, flags);
2582 return mask;
2583 }
2584
2585 static int es1371_midi_open(struct inode *inode, struct file *file)
2586 {
2587 int minor = MINOR(inode->i_rdev);
2588 DECLARE_WAITQUEUE(wait, current);
2589 unsigned long flags;
2590 struct list_head *list;
2591 struct es1371_state *s;
2592
2593 for (list = devs.next; ; list = list->next) {
2594 if (list == &devs)
2595 return -ENODEV;
2596 s = list_entry(list, struct es1371_state, devs);
2597 if (s->dev_midi == minor)
2598 break;
2599 }
2600 VALIDATE_STATE(s);
2601 file->private_data = s;
2602 /* wait for device to become free */
2603 down(&s->open_sem);
2604 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2605 if (file->f_flags & O_NONBLOCK) {
2606 up(&s->open_sem);
2607 return -EBUSY;
2608 }
2609 add_wait_queue(&s->open_wait, &wait);
2610 __set_current_state(TASK_INTERRUPTIBLE);
2611 up(&s->open_sem);
2612 schedule();
2613 remove_wait_queue(&s->open_wait, &wait);
2614 set_current_state(TASK_RUNNING);
2615 if (signal_pending(current))
2616 return -ERESTARTSYS;
2617 down(&s->open_sem);
2618 }
2619 spin_lock_irqsave(&s->lock, flags);
2620 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2621 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2622 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2623 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2624 outb(0, s->io+ES1371_REG_UART_CONTROL);
2625 outb(0, s->io+ES1371_REG_UART_TEST);
2626 }
2627 if (file->f_mode & FMODE_READ) {
2628 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2629 }
2630 if (file->f_mode & FMODE_WRITE) {
2631 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2632 }
2633 s->ctrl |= CTRL_UART_EN;
2634 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2635 es1371_handle_midi(s);
2636 spin_unlock_irqrestore(&s->lock, flags);
2637 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2638 up(&s->open_sem);
2639 return 0;
2640 }
2641
2642 static int es1371_midi_release(struct inode *inode, struct file *file)
2643 {
2644 struct es1371_state *s = (struct es1371_state *)file->private_data;
2645 DECLARE_WAITQUEUE(wait, current);
2646 unsigned long flags;
2647 unsigned count, tmo;
2648
2649 VALIDATE_STATE(s);
2650 lock_kernel();
2651 if (file->f_mode & FMODE_WRITE) {
2652 add_wait_queue(&s->midi.owait, &wait);
2653 for (;;) {
2654 __set_current_state(TASK_INTERRUPTIBLE);
2655 spin_lock_irqsave(&s->lock, flags);
2656 count = s->midi.ocnt;
2657 spin_unlock_irqrestore(&s->lock, flags);
2658 if (count <= 0)
2659 break;
2660 if (signal_pending(current))
2661 break;
2662 if (file->f_flags & O_NONBLOCK) {
2663 remove_wait_queue(&s->midi.owait, &wait);
2664 set_current_state(TASK_RUNNING);
2665 unlock_kernel();
2666 return -EBUSY;
2667 }
2668 tmo = (count * HZ) / 3100;
2669 if (!schedule_timeout(tmo ? : 1) && tmo)
2670 printk(KERN_DEBUG PFX "midi timed out??\n");
2671 }
2672 remove_wait_queue(&s->midi.owait, &wait);
2673 set_current_state(TASK_RUNNING);
2674 }
2675 down(&s->open_sem);
2676 s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
2677 spin_lock_irqsave(&s->lock, flags);
2678 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2679 s->ctrl &= ~CTRL_UART_EN;
2680 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2681 }
2682 spin_unlock_irqrestore(&s->lock, flags);
2683 up(&s->open_sem);
2684 wake_up(&s->open_wait);
2685 unlock_kernel();
2686 return 0;
2687 }
2688
2689 static /*const*/ struct file_operations es1371_midi_fops = {
2690 owner: THIS_MODULE,
2691 llseek: no_llseek,
2692 read: es1371_midi_read,
2693 write: es1371_midi_write,
2694 poll: es1371_midi_poll,
2695 open: es1371_midi_open,
2696 release: es1371_midi_release,
2697 };
2698
2699 /* --------------------------------------------------------------------- */
2700
2701 /*
2702 * for debugging purposes, we'll create a proc device that dumps the
2703 * CODEC chipstate
2704 */
2705
2706 #ifdef ES1371_DEBUG
2707 static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
2708 {
2709 struct es1371_state *s;
2710 int cnt, len = 0;
2711
2712 if (list_empty(&devs))
2713 return 0;
2714 s = list_entry(devs.next, struct es1371_state, devs);
2715 /* print out header */
2716 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
2717
2718 /* print out CODEC state */
2719 len += sprintf (buf + len, "AC97 CODEC state\n");
2720 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
2721 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(&s->codec, cnt));
2722
2723 if (fpos >=len){
2724 *start = buf;
2725 *eof =1;
2726 return 0;
2727 }
2728 *start = buf + fpos;
2729 if ((len -= fpos) > length)
2730 return length;
2731 *eof =1;
2732 return len;
2733
2734 }
2735 #endif /* ES1371_DEBUG */
2736
2737 /* --------------------------------------------------------------------- */
2738
2739 /* maximum number of devices; only used for command line params */
2740 #define NR_DEVICE 5
2741
2742 static int joystick[NR_DEVICE] = { 0, };
2743 static int spdif[NR_DEVICE] = { 0, };
2744 static int nomix[NR_DEVICE] = { 0, };
2745
2746 static unsigned int devindex = 0;
2747 static int amplifier = 0;
2748
2749 MODULE_PARM(joystick, "1-" __MODULE_STRING(NR_DEVICE) "i");
2750 MODULE_PARM_DESC(joystick, "sets address and enables joystick interface (still need separate driver)");
2751 MODULE_PARM(spdif, "1-" __MODULE_STRING(NR_DEVICE) "i");
2752 MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
2753 MODULE_PARM(nomix, "1-" __MODULE_STRING(NR_DEVICE) "i");
2754 MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
2755 MODULE_PARM(amplifier, "i");
2756 MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)");
2757
2758 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2759 MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
2760
2761 /* --------------------------------------------------------------------- */
2762
2763 static struct initvol {
2764 int mixch;
2765 int vol;
2766 } initvol[] __initdata = {
2767 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2768 { SOUND_MIXER_WRITE_CD, 0x4040 },
2769 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
2770 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2771 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2772 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2773 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
2774 { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
2775 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
2776 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2777 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2778 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2779 { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
2780 };
2781
2782 static struct
2783 {
2784 short svid, sdid;
2785 } amplifier_needed[] =
2786 {
2787 { 0x107B, 0x2150 }, /* Gateway Solo 2150 */
2788 { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */
2789 { 0x1102, 0x5938 }, /* Targa Xtender 300 */
2790 { 0x1102, 0x8938 }, /* IPC notebook */
2791 { PCI_ANY_ID, PCI_ANY_ID }
2792 };
2793
2794
2795 static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2796 {
2797 struct es1371_state *s;
2798 mm_segment_t fs;
2799 int i, val, res = -1;
2800 int idx;
2801 unsigned long tmo;
2802 signed long tmo2;
2803 unsigned int cssr;
2804
2805 if ((res=pci_enable_device(pcidev)))
2806 return res;
2807
2808 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
2809 return -ENODEV;
2810 if (pcidev->irq == 0)
2811 return -ENODEV;
2812 i = pci_set_dma_mask(pcidev, 0xffffffff);
2813 if (i) {
2814 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
2815 return i;
2816 }
2817 if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
2818 printk(KERN_WARNING PFX "out of memory\n");
2819 return -ENOMEM;
2820 }
2821 memset(s, 0, sizeof(struct es1371_state));
2822 init_waitqueue_head(&s->dma_adc.wait);
2823 init_waitqueue_head(&s->dma_dac1.wait);
2824 init_waitqueue_head(&s->dma_dac2.wait);
2825 init_waitqueue_head(&s->open_wait);
2826 init_waitqueue_head(&s->midi.iwait);
2827 init_waitqueue_head(&s->midi.owait);
2828 init_MUTEX(&s->open_sem);
2829 spin_lock_init(&s->lock);
2830 s->magic = ES1371_MAGIC;
2831 s->dev = pcidev;
2832 s->io = pci_resource_start(pcidev, 0);
2833 s->irq = pcidev->irq;
2834 s->vendor = pcidev->vendor;
2835 s->device = pcidev->device;
2836 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2837 s->codec.private_data = s;
2838 s->codec.id = 0;
2839 s->codec.codec_read = rdcodec;
2840 s->codec.codec_write = wrcodec;
2841 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
2842 s->vendor, s->device, s->rev);
2843 if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
2844 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
2845 res = -EBUSY;
2846 goto err_region;
2847 }
2848 if ((res=request_irq(s->irq, es1371_interrupt, SA_SHIRQ, "es1371",s))) {
2849 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
2850 goto err_irq;
2851 }
2852 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n"
2853 KERN_INFO PFX "features: joystick 0x%x\n", s->rev, s->io, s->irq, joystick[devindex]);
2854 /* register devices */
2855 if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1))<0))
2856 goto err_dev1;
2857 if ((res=(s->codec.dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1)) < 0))
2858 goto err_dev2;
2859 if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1)) < 0))
2860 goto err_dev3;
2861 if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1))<0 ))
2862 goto err_dev4;
2863 #ifdef ES1371_DEBUG
2864 /* intialize the debug proc device */
2865 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
2866 #endif /* ES1371_DEBUG */
2867
2868 /* initialize codec registers */
2869 s->ctrl = 0;
2870
2871 /* Check amplifier requirements */
2872
2873 if(amplifier)
2874 s->ctrl |= CTRL_GPIO_OUT0;
2875 else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++)
2876 {
2877 if(pcidev->subsystem_vendor == amplifier_needed[idx].svid &&
2878 pcidev->subsystem_device == amplifier_needed[idx].sdid)
2879 {
2880 s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */
2881 printk(KERN_INFO PFX "Enabling internal amplifier.\n");
2882 }
2883 }
2884 s->gameport.io = 0;
2885 if ((joystick[devindex] & ~0x18) == 0x200) {
2886 if (!request_region(joystick[devindex], JOY_EXTENT, "es1371"))
2887 printk(KERN_ERR PFX "joystick address 0x%x already in use\n", joystick[devindex]);
2888 else {
2889 s->ctrl |= CTRL_JYSTK_EN | (((joystick[devindex] >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2890 s->gameport.io = joystick[devindex];
2891 }
2892 } else if (joystick[devindex] == 1) {
2893 for (i = 0x218; i >= 0x200; i -= 0x08) {
2894 if (request_region(i, JOY_EXTENT, "es1371")) {
2895 s->ctrl |= CTRL_JYSTK_EN | (((i >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2896 s->gameport.io = i;
2897 break;
2898 }
2899 }
2900 if (!s->gameport.io)
2901 printk(KERN_ERR PFX "no free joystick address found\n");
2902 }
2903 s->sctrl = 0;
2904 cssr = 0;
2905 s->spdif_volume = -1;
2906 /* check to see if s/pdif mode is being requested */
2907 if (spdif[devindex]) {
2908 if (s->rev >= 4) {
2909 printk(KERN_INFO PFX "enabling S/PDIF output\n");
2910 s->spdif_volume = 0;
2911 cssr |= STAT_EN_SPDIF;
2912 s->ctrl |= CTRL_SPDIFEN_B;
2913 if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
2914 s->ctrl |= CTRL_RECEN_B;
2915 } else {
2916 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
2917 }
2918 }
2919 /* initialize the chips */
2920 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2921 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2922 outl(0, s->io+ES1371_REG_LEGACY);
2923 pci_set_master(pcidev); /* enable bus mastering */
2924 /* if we are a 5880 turn on the AC97 */
2925 if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
2926 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) ||
2927 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
2928 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
2929 cssr |= CSTAT_5880_AC97_RST;
2930 outl(cssr, s->io+ES1371_REG_STATUS);
2931 /* need to delay around 20ms(bleech) to give
2932 some CODECs enough time to wakeup */
2933 tmo = jiffies + (HZ / 50) + 1;
2934 for (;;) {
2935 tmo2 = tmo - jiffies;
2936 if (tmo2 <= 0)
2937 break;
2938 schedule_timeout(tmo2);
2939 }
2940 }
2941 /* AC97 warm reset to start the bitclk */
2942 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
2943 udelay(2);
2944 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2945 /* init the sample rate converter */
2946 src_init(s);
2947 /* codec init */
2948 if (!ac97_probe_codec(&s->codec)) {
2949 res = -ENODEV;
2950 goto err_gp;
2951 }
2952 /* set default values */
2953
2954 fs = get_fs();
2955 set_fs(KERNEL_DS);
2956 val = SOUND_MASK_LINE;
2957 mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2958 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2959 val = initvol[i].vol;
2960 mixdev_ioctl(&s->codec, initvol[i].mixch, (unsigned long)&val);
2961 }
2962 /* mute master and PCM when in S/PDIF mode */
2963 if (s->spdif_volume != -1) {
2964 val = 0x0000;
2965 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
2966 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
2967 }
2968 set_fs(fs);
2969 /* turn on S/PDIF output driver if requested */
2970 outl(cssr, s->io+ES1371_REG_STATUS);
2971 /* register gameport */
2972 gameport_register_port(&s->gameport);
2973 /* store it in the driver field */
2974 pci_set_drvdata(pcidev, s);
2975 /* put it into driver list */
2976 list_add_tail(&s->devs, &devs);
2977 /* increment devindex */
2978 if (devindex < NR_DEVICE-1)
2979 devindex++;
2980 return 0;
2981
2982 err_gp:
2983 if (s->gameport.io)
2984 release_region(s->gameport.io, JOY_EXTENT);
2985 err_dev4:
2986 unregister_sound_dsp(s->dev_dac);
2987 err_dev3:
2988 unregister_sound_mixer(s->codec.dev_mixer);
2989 err_dev2:
2990 unregister_sound_dsp(s->dev_audio);
2991 err_dev1:
2992 printk(KERN_ERR PFX "cannot register misc device\n");
2993 free_irq(s->irq, s);
2994 err_irq:
2995 release_region(s->io, ES1371_EXTENT);
2996 err_region:
2997 kfree(s);
2998 return res;
2999 }
3000
3001 static void __devinit es1371_remove(struct pci_dev *dev)
3002 {
3003 struct es1371_state *s = pci_get_drvdata(dev);
3004
3005 if (!s)
3006 return;
3007 list_del(&s->devs);
3008 #ifdef ES1371_DEBUG
3009 if (s->ps)
3010 remove_proc_entry("es1371", NULL);
3011 #endif /* ES1371_DEBUG */
3012 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
3013 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
3014 synchronize_irq();
3015 free_irq(s->irq, s);
3016 if (s->gameport.io) {
3017 gameport_unregister_port(&s->gameport);
3018 release_region(s->gameport.io, JOY_EXTENT);
3019 }
3020 release_region(s->io, ES1371_EXTENT);
3021 unregister_sound_dsp(s->dev_audio);
3022 unregister_sound_mixer(s->codec.dev_mixer);
3023 unregister_sound_dsp(s->dev_dac);
3024 unregister_sound_midi(s->dev_midi);
3025 kfree(s);
3026 pci_set_drvdata(dev, NULL);
3027 }
3028
3029 static struct pci_device_id id_table[] __devinitdata = {
3030 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3031 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3032 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3033 { 0, }
3034 };
3035
3036 MODULE_DEVICE_TABLE(pci, id_table);
3037
3038 static struct pci_driver es1371_driver = {
3039 name: "es1371",
3040 id_table: id_table,
3041 probe: es1371_probe,
3042 remove: es1371_remove
3043 };
3044
3045 static int __init init_es1371(void)
3046 {
3047 if (!pci_present()) /* No PCI bus in this machine! */
3048 return -ENODEV;
3049 printk(KERN_INFO PFX "version v0.30 time " __TIME__ " " __DATE__ "\n");
3050 return pci_module_init(&es1371_driver);
3051 }
3052
3053 static void __exit cleanup_es1371(void)
3054 {
3055 printk(KERN_INFO PFX "unloading\n");
3056 pci_unregister_driver(&es1371_driver);
3057 }
3058
3059 module_init(init_es1371);
3060 module_exit(cleanup_es1371);
3061
3062 /* --------------------------------------------------------------------- */
3063
3064 #ifndef MODULE
3065
3066 /* format is: es1371=[joystick] */
3067
3068 static int __init es1371_setup(char *str)
3069 {
3070 static unsigned __initdata nr_dev = 0;
3071
3072 if (nr_dev >= NR_DEVICE)
3073 return 0;
3074 if (get_option(&str, &joystick[nr_dev]) == 2)
3075 (void)get_option(&str, &spdif[nr_dev]);
3076 nr_dev++;
3077 return 1;
3078 }
3079
3080 __setup("es1371=", es1371_setup);
3081
3082 #endif /* MODULE */
3083