File: /usr/src/linux/drivers/sound/esssolo1.c
1 /****************************************************************************/
2
3 /*
4 * esssolo1.c -- ESS Technology Solo1 (ES1946) audio driver.
5 *
6 * Copyright (C) 1998-2001 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Module command line parameters:
23 * none so far
24 *
25 * Supported devices:
26 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
27 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * Revision history
31 * 10.11.1998 0.1 Initial release (without any hardware)
32 * 22.03.1999 0.2 cinfo.blocks should be reset after GETxPTR ioctl.
33 * reported by Johan Maes <joma@telindus.be>
34 * return EAGAIN instead of EBUSY when O_NONBLOCK
35 * read/write cannot be executed
36 * 07.04.1999 0.3 implemented the following ioctl's: SOUND_PCM_READ_RATE,
37 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
38 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
39 * 15.06.1999 0.4 Fix bad allocation bug.
40 * Thanks to Deti Fliegl <fliegl@in.tum.de>
41 * 28.06.1999 0.5 Add pci_set_master
42 * 12.08.1999 0.6 Fix MIDI UART crashing the driver
43 * Changed mixer semantics from OSS documented
44 * behaviour to OSS "code behaviour".
45 * Recording might actually work now.
46 * The real DDMA controller address register is at PCI config
47 * 0x60, while the register at 0x18 is used as a placeholder
48 * register for BIOS address allocation. This register
49 * is supposed to be copied into 0x60, according
50 * to the Solo1 datasheet. When I do that, I can access
51 * the DDMA registers except the mask bit, which
52 * is stuck at 1. When I copy the contents of 0x18 +0x10
53 * to the DDMA base register, everything seems to work.
54 * The fun part is that the Windows Solo1 driver doesn't
55 * seem to do these tricks.
56 * Bugs remaining: plops and clicks when starting/stopping playback
57 * 31.08.1999 0.7 add spin_lock_init
58 * replaced current->state = x with set_current_state(x)
59 * 03.09.1999 0.8 change read semantics for MIDI to match
60 * OSS more closely; remove possible wakeup race
61 * 07.10.1999 0.9 Fix initialization; complain if sequencer writes time out
62 * Revised resource grabbing for the FM synthesizer
63 * 28.10.1999 0.10 More waitqueue races fixed
64 * 09.12.1999 0.11 Work around stupid Alpha port issue (virt_to_bus(kmalloc(GFP_DMA)) > 16M)
65 * Disabling recording on Alpha
66 * 12.01.2000 0.12 Prevent some ioctl's from returning bad count values on underrun/overrun;
67 * Tim Janik's BSE (Bedevilled Sound Engine) found this
68 * Integrated (aka redid 8-)) APM support patch by Zach Brown
69 * 07.02.2000 0.13 Use pci_alloc_consistent and pci_register_driver
70 * 19.02.2000 0.14 Use pci_dma_supported to determine if recording should be disabled
71 * 13.03.2000 0.15 Reintroduce initialization of a couple of PCI config space registers
72 * 21.11.2000 0.16 Initialize dma buffers in poll, otherwise poll may return a bogus mask
73 * 12.12.2000 0.17 More dma buffer initializations, patch from
74 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
75 * 31.01.2001 0.18 Register/Unregister gameport, original patch from
76 * Nathaniel Daw <daw@cs.cmu.edu>
77 * Fix SETTRIGGER non OSS API conformity
78 * 10.03.2001 provide abs function, prevent picking up a bogus kernel macro
79 * for abs. Bug report by Andrew Morton <andrewm@uow.edu.au>
80 * 15.05.2001 pci_enable_device moved, return values in probe cleaned
81 * up. Marcus Meissner <mm@caldera.de>
82 * 22.05.2001 0.19 more cleanups, changed PM to PCI 2.4 style, got rid
83 * of global list of devices, using pci device data.
84 * Marcus Meissner <mm@caldera.de>
85 */
86
87 /*****************************************************************************/
88
89 #include <linux/version.h>
90 #include <linux/module.h>
91 #include <linux/string.h>
92 #include <linux/ioport.h>
93 #include <linux/sched.h>
94 #include <linux/delay.h>
95 #include <linux/sound.h>
96 #include <linux/slab.h>
97 #include <linux/soundcard.h>
98 #include <linux/pci.h>
99 #include <linux/bitops.h>
100 #include <asm/io.h>
101 #include <asm/dma.h>
102 #include <linux/init.h>
103 #include <linux/poll.h>
104 #include <linux/spinlock.h>
105 #include <linux/smp_lock.h>
106 #include <linux/wrapper.h>
107 #include <asm/uaccess.h>
108 #include <asm/hardirq.h>
109 #include <linux/gameport.h>
110
111 #include "dm.h"
112
113 /* --------------------------------------------------------------------- */
114
115 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
116
117 /* --------------------------------------------------------------------- */
118
119 #ifndef PCI_VENDOR_ID_ESS
120 #define PCI_VENDOR_ID_ESS 0x125d
121 #endif
122 #ifndef PCI_DEVICE_ID_ESS_SOLO1
123 #define PCI_DEVICE_ID_ESS_SOLO1 0x1969
124 #endif
125
126 #define SOLO1_MAGIC ((PCI_VENDOR_ID_ESS<<16)|PCI_DEVICE_ID_ESS_SOLO1)
127
128 #define DDMABASE_OFFSET 0 /* chip bug workaround kludge */
129 #define DDMABASE_EXTENT 16
130
131 #define IOBASE_EXTENT 16
132 #define SBBASE_EXTENT 16
133 #define VCBASE_EXTENT (DDMABASE_EXTENT+DDMABASE_OFFSET)
134 #define MPUBASE_EXTENT 4
135 #define GPBASE_EXTENT 4
136 #define GAMEPORT_EXTENT 4
137
138 #define FMSYNTH_EXTENT 4
139
140 /* MIDI buffer sizes */
141
142 #define MIDIINBUF 256
143 #define MIDIOUTBUF 256
144
145 #define FMODE_MIDI_SHIFT 3
146 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
147 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
148
149 #define FMODE_DMFM 0x10
150
151 static struct pci_driver solo1_driver;
152
153 /* --------------------------------------------------------------------- */
154
155 struct solo1_state {
156 /* magic */
157 unsigned int magic;
158
159 /* the corresponding pci_dev structure */
160 struct pci_dev *dev;
161
162 /* soundcore stuff */
163 int dev_audio;
164 int dev_mixer;
165 int dev_midi;
166 int dev_dmfm;
167
168 /* hardware resources */
169 unsigned long iobase, sbbase, vcbase, ddmabase, mpubase; /* long for SPARC */
170 unsigned int irq;
171
172 /* mixer registers */
173 struct {
174 unsigned short vol[10];
175 unsigned int recsrc;
176 unsigned int modcnt;
177 unsigned short micpreamp;
178 } mix;
179
180 /* wave stuff */
181 unsigned fmt;
182 unsigned channels;
183 unsigned rate;
184 unsigned char clkdiv;
185 unsigned ena;
186
187 spinlock_t lock;
188 struct semaphore open_sem;
189 mode_t open_mode;
190 wait_queue_head_t open_wait;
191
192 struct dmabuf {
193 void *rawbuf;
194 dma_addr_t dmaaddr;
195 unsigned buforder;
196 unsigned numfrag;
197 unsigned fragshift;
198 unsigned hwptr, swptr;
199 unsigned total_bytes;
200 int count;
201 unsigned error; /* over/underrun */
202 wait_queue_head_t wait;
203 /* redundant, but makes calculations easier */
204 unsigned fragsize;
205 unsigned dmasize;
206 unsigned fragsamples;
207 /* OSS stuff */
208 unsigned mapped:1;
209 unsigned ready:1;
210 unsigned endcleared:1;
211 unsigned enabled:1;
212 unsigned ossfragshift;
213 int ossmaxfrags;
214 unsigned subdivision;
215 } dma_dac, dma_adc;
216
217 /* midi stuff */
218 struct {
219 unsigned ird, iwr, icnt;
220 unsigned ord, owr, ocnt;
221 wait_queue_head_t iwait;
222 wait_queue_head_t owait;
223 struct timer_list timer;
224 unsigned char ibuf[MIDIINBUF];
225 unsigned char obuf[MIDIOUTBUF];
226 } midi;
227
228 struct gameport gameport;
229 };
230
231 /* --------------------------------------------------------------------- */
232
233 static inline void write_seq(struct solo1_state *s, unsigned char data)
234 {
235 int i;
236 unsigned long flags;
237
238 /* the __cli stunt is to send the data within the command window */
239 for (i = 0; i < 0xffff; i++) {
240 __save_flags(flags);
241 __cli();
242 if (!(inb(s->sbbase+0xc) & 0x80)) {
243 outb(data, s->sbbase+0xc);
244 __restore_flags(flags);
245 return;
246 }
247 __restore_flags(flags);
248 }
249 printk(KERN_ERR "esssolo1: write_seq timeout\n");
250 outb(data, s->sbbase+0xc);
251 }
252
253 static inline int read_seq(struct solo1_state *s, unsigned char *data)
254 {
255 int i;
256
257 if (!data)
258 return 0;
259 for (i = 0; i < 0xffff; i++)
260 if (inb(s->sbbase+0xe) & 0x80) {
261 *data = inb(s->sbbase+0xa);
262 return 1;
263 }
264 printk(KERN_ERR "esssolo1: read_seq timeout\n");
265 return 0;
266 }
267
268 static int inline reset_ctrl(struct solo1_state *s)
269 {
270 int i;
271
272 outb(3, s->sbbase+6); /* clear sequencer and FIFO */
273 udelay(10);
274 outb(0, s->sbbase+6);
275 for (i = 0; i < 0xffff; i++)
276 if (inb(s->sbbase+0xe) & 0x80)
277 if (inb(s->sbbase+0xa) == 0xaa) {
278 write_seq(s, 0xc6); /* enter enhanced mode */
279 return 1;
280 }
281 return 0;
282 }
283
284 static void write_ctrl(struct solo1_state *s, unsigned char reg, unsigned char data)
285 {
286 write_seq(s, reg);
287 write_seq(s, data);
288 }
289
290 #if 0 /* unused */
291 static unsigned char read_ctrl(struct solo1_state *s, unsigned char reg)
292 {
293 unsigned char r;
294
295 write_seq(s, 0xc0);
296 write_seq(s, reg);
297 read_seq(s, &r);
298 return r;
299 }
300 #endif /* unused */
301
302 static void write_mixer(struct solo1_state *s, unsigned char reg, unsigned char data)
303 {
304 outb(reg, s->sbbase+4);
305 outb(data, s->sbbase+5);
306 }
307
308 static unsigned char read_mixer(struct solo1_state *s, unsigned char reg)
309 {
310 outb(reg, s->sbbase+4);
311 return inb(s->sbbase+5);
312 }
313
314 /* --------------------------------------------------------------------- */
315
316 static inline unsigned ld2(unsigned int x)
317 {
318 unsigned r = 0;
319
320 if (x >= 0x10000) {
321 x >>= 16;
322 r += 16;
323 }
324 if (x >= 0x100) {
325 x >>= 8;
326 r += 8;
327 }
328 if (x >= 0x10) {
329 x >>= 4;
330 r += 4;
331 }
332 if (x >= 4) {
333 x >>= 2;
334 r += 2;
335 }
336 if (x >= 2)
337 r++;
338 return r;
339 }
340
341 /* --------------------------------------------------------------------- */
342
343 static inline void stop_dac(struct solo1_state *s)
344 {
345 unsigned long flags;
346
347 spin_lock_irqsave(&s->lock, flags);
348 s->ena &= ~FMODE_WRITE;
349 write_mixer(s, 0x78, 0x10);
350 spin_unlock_irqrestore(&s->lock, flags);
351 }
352
353 static void start_dac(struct solo1_state *s)
354 {
355 unsigned long flags;
356
357 spin_lock_irqsave(&s->lock, flags);
358 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
359 s->ena |= FMODE_WRITE;
360 write_mixer(s, 0x78, 0x12);
361 udelay(10);
362 write_mixer(s, 0x78, 0x13);
363 }
364 spin_unlock_irqrestore(&s->lock, flags);
365 }
366
367 static inline void stop_adc(struct solo1_state *s)
368 {
369 unsigned long flags;
370
371 spin_lock_irqsave(&s->lock, flags);
372 s->ena &= ~FMODE_READ;
373 write_ctrl(s, 0xb8, 0xe);
374 spin_unlock_irqrestore(&s->lock, flags);
375 }
376
377 static void start_adc(struct solo1_state *s)
378 {
379 unsigned long flags;
380
381 spin_lock_irqsave(&s->lock, flags);
382 if (!(s->ena & FMODE_READ) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
383 && s->dma_adc.ready) {
384 s->ena |= FMODE_READ;
385 write_ctrl(s, 0xb8, 0xf);
386 #if 0
387 printk(KERN_DEBUG "solo1: DMAbuffer: 0x%08lx\n", (long)s->dma_adc.rawbuf);
388 printk(KERN_DEBUG "solo1: DMA: mask: 0x%02x cnt: 0x%04x addr: 0x%08x stat: 0x%02x\n",
389 inb(s->ddmabase+0xf), inw(s->ddmabase+4), inl(s->ddmabase), inb(s->ddmabase+8));
390 #endif
391 outb(0, s->ddmabase+0xd); /* master reset */
392 outb(1, s->ddmabase+0xf); /* mask */
393 outb(0x54/*0x14*/, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
394 outl(virt_to_bus(s->dma_adc.rawbuf), s->ddmabase);
395 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
396 outb(0, s->ddmabase+0xf);
397 }
398 spin_unlock_irqrestore(&s->lock, flags);
399 #if 0
400 printk(KERN_DEBUG "solo1: start DMA: reg B8: 0x%02x SBstat: 0x%02x\n"
401 KERN_DEBUG "solo1: DMA: stat: 0x%02x cnt: 0x%04x mask: 0x%02x\n",
402 read_ctrl(s, 0xb8), inb(s->sbbase+0xc),
403 inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->ddmabase+0xf));
404 printk(KERN_DEBUG "solo1: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
405 KERN_DEBUG "solo1: B1: 0x%02x B2: 0x%02x B4: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n",
406 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
407 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb4), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8),
408 read_ctrl(s, 0xb9));
409 #endif
410 }
411
412 /* --------------------------------------------------------------------- */
413
414 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
415 #define DMABUF_MINORDER 1
416
417 static inline void dealloc_dmabuf(struct solo1_state *s, struct dmabuf *db)
418 {
419 struct page *page, *pend;
420
421 if (db->rawbuf) {
422 /* undo marking the pages as reserved */
423 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
424 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
425 mem_map_unreserve(page);
426 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
427 }
428 db->rawbuf = NULL;
429 db->mapped = db->ready = 0;
430 }
431
432 static int prog_dmabuf(struct solo1_state *s, struct dmabuf *db)
433 {
434 int order;
435 unsigned bytespersec;
436 unsigned bufs, sample_shift = 0;
437 struct page *page, *pend;
438
439 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
440 if (!db->rawbuf) {
441 db->ready = db->mapped = 0;
442 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
443 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
444 break;
445 if (!db->rawbuf)
446 return -ENOMEM;
447 db->buforder = order;
448 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
449 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
450 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
451 mem_map_reserve(page);
452 }
453 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
454 sample_shift++;
455 if (s->channels > 1)
456 sample_shift++;
457 bytespersec = s->rate << sample_shift;
458 bufs = PAGE_SIZE << db->buforder;
459 if (db->ossfragshift) {
460 if ((1000 << db->ossfragshift) < bytespersec)
461 db->fragshift = ld2(bytespersec/1000);
462 else
463 db->fragshift = db->ossfragshift;
464 } else {
465 db->fragshift = ld2(bytespersec/100/(db->subdivision ? db->subdivision : 1));
466 if (db->fragshift < 3)
467 db->fragshift = 3;
468 }
469 db->numfrag = bufs >> db->fragshift;
470 while (db->numfrag < 4 && db->fragshift > 3) {
471 db->fragshift--;
472 db->numfrag = bufs >> db->fragshift;
473 }
474 db->fragsize = 1 << db->fragshift;
475 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
476 db->numfrag = db->ossmaxfrags;
477 db->fragsamples = db->fragsize >> sample_shift;
478 db->dmasize = db->numfrag << db->fragshift;
479 db->enabled = 1;
480 return 0;
481 }
482
483 static inline int prog_dmabuf_adc(struct solo1_state *s)
484 {
485 unsigned long va;
486 int c;
487
488 stop_adc(s);
489 /* check if PCI implementation supports 24bit busmaster DMA */
490 if (s->dev->dma_mask > 0xffffff)
491 return -EIO;
492 if ((c = prog_dmabuf(s, &s->dma_adc)))
493 return c;
494 va = s->dma_adc.dmaaddr;
495 if ((va & ~((1<<24)-1)))
496 panic("solo1: buffer above 16M boundary");
497 outb(0, s->ddmabase+0xd); /* clear */
498 outb(1, s->ddmabase+0xf); /* mask */
499 /*outb(0, s->ddmabase+8);*/ /* enable (enable is active low!) */
500 outb(0x54, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
501 outl(va, s->ddmabase);
502 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
503 c = - s->dma_adc.fragsamples;
504 write_ctrl(s, 0xa4, c);
505 write_ctrl(s, 0xa5, c >> 8);
506 outb(0, s->ddmabase+0xf);
507 s->dma_adc.ready = 1;
508 return 0;
509 }
510
511 static inline int prog_dmabuf_dac(struct solo1_state *s)
512 {
513 unsigned long va;
514 int c;
515
516 stop_dac(s);
517 if ((c = prog_dmabuf(s, &s->dma_dac)))
518 return c;
519 memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80, s->dma_dac.dmasize); /* almost correct for U16 */
520 va = s->dma_dac.dmaaddr;
521 if ((va ^ (va + s->dma_dac.dmasize - 1)) & ~((1<<20)-1))
522 panic("solo1: buffer crosses 1M boundary");
523 outl(va, s->iobase);
524 /* warning: s->dma_dac.dmasize & 0xffff must not be zero! i.e. this limits us to a 32k buffer */
525 outw(s->dma_dac.dmasize, s->iobase+4);
526 c = - s->dma_dac.fragsamples;
527 write_mixer(s, 0x74, c);
528 write_mixer(s, 0x76, c >> 8);
529 outb(0xa, s->iobase+6);
530 s->dma_dac.ready = 1;
531 return 0;
532 }
533
534 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
535 {
536 if (bptr + len > bsize) {
537 unsigned x = bsize - bptr;
538 memset(((char *)buf) + bptr, c, x);
539 bptr = 0;
540 len -= x;
541 }
542 memset(((char *)buf) + bptr, c, len);
543 }
544
545 /* call with spinlock held! */
546
547 static void solo1_update_ptr(struct solo1_state *s)
548 {
549 int diff;
550 unsigned hwptr;
551
552 /* update ADC pointer */
553 if (s->ena & FMODE_READ) {
554 hwptr = (s->dma_adc.dmasize - 1 - inw(s->ddmabase+4)) % s->dma_adc.dmasize;
555 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
556 s->dma_adc.hwptr = hwptr;
557 s->dma_adc.total_bytes += diff;
558 s->dma_adc.count += diff;
559 #if 0
560 printk(KERN_DEBUG "solo1: rd: hwptr %u swptr %u dmasize %u count %u\n",
561 s->dma_adc.hwptr, s->dma_adc.swptr, s->dma_adc.dmasize, s->dma_adc.count);
562 #endif
563 if (s->dma_adc.mapped) {
564 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
565 wake_up(&s->dma_adc.wait);
566 } else {
567 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
568 s->ena &= ~FMODE_READ;
569 write_ctrl(s, 0xb8, 0xe);
570 s->dma_adc.error++;
571 }
572 if (s->dma_adc.count > 0)
573 wake_up(&s->dma_adc.wait);
574 }
575 }
576 /* update DAC pointer */
577 if (s->ena & FMODE_WRITE) {
578 hwptr = (s->dma_dac.dmasize - inw(s->iobase+4)) % s->dma_dac.dmasize;
579 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
580 s->dma_dac.hwptr = hwptr;
581 s->dma_dac.total_bytes += diff;
582 #if 0
583 printk(KERN_DEBUG "solo1: wr: hwptr %u swptr %u dmasize %u count %u\n",
584 s->dma_dac.hwptr, s->dma_dac.swptr, s->dma_dac.dmasize, s->dma_dac.count);
585 #endif
586 if (s->dma_dac.mapped) {
587 s->dma_dac.count += diff;
588 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
589 wake_up(&s->dma_dac.wait);
590 } else {
591 s->dma_dac.count -= diff;
592 if (s->dma_dac.count <= 0) {
593 s->ena &= ~FMODE_WRITE;
594 write_mixer(s, 0x78, 0x12);
595 s->dma_dac.error++;
596 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
597 clear_advance(s->dma_dac.rawbuf, s->dma_dac.dmasize, s->dma_dac.swptr,
598 s->dma_dac.fragsize, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80);
599 s->dma_dac.endcleared = 1;
600 }
601 if (s->dma_dac.count < (signed)s->dma_dac.dmasize)
602 wake_up(&s->dma_dac.wait);
603 }
604 }
605 }
606
607 /* --------------------------------------------------------------------- */
608
609 static void prog_codec(struct solo1_state *s)
610 {
611 unsigned long flags;
612 int fdiv, filter;
613 unsigned char c;
614
615 reset_ctrl(s);
616 write_seq(s, 0xd3);
617 /* program sampling rates */
618 filter = s->rate * 9 / 20; /* Set filter roll-off to 90% of rate/2 */
619 fdiv = 256 - 7160000 / (filter * 82);
620 spin_lock_irqsave(&s->lock, flags);
621 write_ctrl(s, 0xa1, s->clkdiv);
622 write_ctrl(s, 0xa2, fdiv);
623 write_mixer(s, 0x70, s->clkdiv);
624 write_mixer(s, 0x72, fdiv);
625 /* program ADC parameters */
626 write_ctrl(s, 0xb8, 0xe);
627 write_ctrl(s, 0xb9, /*0x1*/0);
628 write_ctrl(s, 0xa8, (s->channels > 1) ? 0x11 : 0x12);
629 c = 0xd0;
630 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
631 c |= 0x04;
632 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
633 c |= 0x20;
634 if (s->channels > 1)
635 c ^= 0x48;
636 write_ctrl(s, 0xb7, (c & 0x70) | 1);
637 write_ctrl(s, 0xb7, c);
638 write_ctrl(s, 0xb1, 0x50);
639 write_ctrl(s, 0xb2, 0x50);
640 /* program DAC parameters */
641 c = 0x40;
642 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
643 c |= 1;
644 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
645 c |= 4;
646 if (s->channels > 1)
647 c |= 2;
648 write_mixer(s, 0x7a, c);
649 write_mixer(s, 0x78, 0x10);
650 s->ena = 0;
651 spin_unlock_irqrestore(&s->lock, flags);
652 }
653
654 /* --------------------------------------------------------------------- */
655
656 static const char invalid_magic[] = KERN_CRIT "solo1: invalid magic value\n";
657
658 #define VALIDATE_STATE(s) \
659 ({ \
660 if (!(s) || (s)->magic != SOLO1_MAGIC) { \
661 printk(invalid_magic); \
662 return -ENXIO; \
663 } \
664 })
665
666 /* --------------------------------------------------------------------- */
667
668 static int mixer_ioctl(struct solo1_state *s, unsigned int cmd, unsigned long arg)
669 {
670 static const unsigned int mixer_src[8] = {
671 SOUND_MASK_MIC, SOUND_MASK_MIC, SOUND_MASK_CD, SOUND_MASK_VOLUME,
672 SOUND_MASK_MIC, 0, SOUND_MASK_LINE, 0
673 };
674 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
675 [SOUND_MIXER_PCM] = 1, /* voice */
676 [SOUND_MIXER_SYNTH] = 2, /* FM */
677 [SOUND_MIXER_CD] = 3, /* CD */
678 [SOUND_MIXER_LINE] = 4, /* Line */
679 [SOUND_MIXER_LINE1] = 5, /* AUX */
680 [SOUND_MIXER_MIC] = 6, /* Mic */
681 [SOUND_MIXER_LINE2] = 7, /* Mono in */
682 [SOUND_MIXER_SPEAKER] = 8, /* Speaker */
683 [SOUND_MIXER_RECLEV] = 9, /* Recording level */
684 [SOUND_MIXER_VOLUME] = 10 /* Master Volume */
685 };
686 static const unsigned char mixreg[] = {
687 0x7c, /* voice */
688 0x36, /* FM */
689 0x38, /* CD */
690 0x3e, /* Line */
691 0x3a, /* AUX */
692 0x1a, /* Mic */
693 0x6d /* Mono in */
694 };
695 unsigned char l, r, rl, rr, vidx;
696 int i, val;
697
698 VALIDATE_STATE(s);
699
700 if (cmd == SOUND_MIXER_PRIVATE1) {
701 /* enable/disable/query mixer preamp */
702 if (get_user(val, (int *)arg))
703 return -EFAULT;
704 if (val != -1) {
705 val = val ? 0xff : 0xf7;
706 write_mixer(s, 0x7d, (read_mixer(s, 0x7d) | 0x08) & val);
707 }
708 val = (read_mixer(s, 0x7d) & 0x08) ? 1 : 0;
709 return put_user(val, (int *)arg);
710 }
711 if (cmd == SOUND_MIXER_PRIVATE2) {
712 /* enable/disable/query spatializer */
713 if (get_user(val, (int *)arg))
714 return -EFAULT;
715 if (val != -1) {
716 val &= 0x3f;
717 write_mixer(s, 0x52, val);
718 write_mixer(s, 0x50, val ? 0x08 : 0);
719 }
720 return put_user(read_mixer(s, 0x52), (int *)arg);
721 }
722 if (cmd == SOUND_MIXER_INFO) {
723 mixer_info info;
724 strncpy(info.id, "Solo1", sizeof(info.id));
725 strncpy(info.name, "ESS Solo1", sizeof(info.name));
726 info.modify_counter = s->mix.modcnt;
727 if (copy_to_user((void *)arg, &info, sizeof(info)))
728 return -EFAULT;
729 return 0;
730 }
731 if (cmd == SOUND_OLD_MIXER_INFO) {
732 _old_mixer_info info;
733 strncpy(info.id, "Solo1", sizeof(info.id));
734 strncpy(info.name, "ESS Solo1", sizeof(info.name));
735 if (copy_to_user((void *)arg, &info, sizeof(info)))
736 return -EFAULT;
737 return 0;
738 }
739 if (cmd == OSS_GETVERSION)
740 return put_user(SOUND_VERSION, (int *)arg);
741 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
742 return -EINVAL;
743 if (_SIOC_DIR(cmd) == _SIOC_READ) {
744 switch (_IOC_NR(cmd)) {
745 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
746 return put_user(mixer_src[read_mixer(s, 0x1c) & 7], (int *)arg);
747
748 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
749 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
750 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
751 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV |
752 SOUND_MASK_SPEAKER, (int *)arg);
753
754 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
755 return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_VOLUME, (int *)arg);
756
757 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
758 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
759 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
760 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV, (int *)arg);
761
762 case SOUND_MIXER_CAPS:
763 return put_user(SOUND_CAP_EXCL_INPUT, (int *)arg);
764
765 default:
766 i = _IOC_NR(cmd);
767 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
768 return -EINVAL;
769 return put_user(s->mix.vol[vidx-1], (int *)arg);
770 }
771 }
772 if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
773 return -EINVAL;
774 s->mix.modcnt++;
775 switch (_IOC_NR(cmd)) {
776 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
777 #if 0
778 {
779 static const unsigned char regs[] = {
780 0x1c, 0x1a, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 0x60, 0x62, 0x6d, 0x7c
781 };
782 int i;
783
784 for (i = 0; i < sizeof(regs); i++)
785 printk(KERN_DEBUG "solo1: mixer reg 0x%02x: 0x%02x\n",
786 regs[i], read_mixer(s, regs[i]));
787 printk(KERN_DEBUG "solo1: ctrl reg 0x%02x: 0x%02x\n",
788 0xb4, read_ctrl(s, 0xb4));
789 }
790 #endif
791 if (get_user(val, (int *)arg))
792 return -EFAULT;
793 i = hweight32(val);
794 if (i == 0)
795 return 0;
796 else if (i > 1)
797 val &= ~mixer_src[read_mixer(s, 0x1c) & 7];
798 for (i = 0; i < 8; i++) {
799 if (mixer_src[i] & val)
800 break;
801 }
802 if (i > 7)
803 return 0;
804 write_mixer(s, 0x1c, i);
805 return 0;
806
807 case SOUND_MIXER_VOLUME:
808 if (get_user(val, (int *)arg))
809 return -EFAULT;
810 l = val & 0xff;
811 if (l > 100)
812 l = 100;
813 r = (val >> 8) & 0xff;
814 if (r > 100)
815 r = 100;
816 if (l < 6) {
817 rl = 0x40;
818 l = 0;
819 } else {
820 rl = (l * 2 - 11) / 3;
821 l = (rl * 3 + 11) / 2;
822 }
823 if (r < 6) {
824 rr = 0x40;
825 r = 0;
826 } else {
827 rr = (r * 2 - 11) / 3;
828 r = (rr * 3 + 11) / 2;
829 }
830 write_mixer(s, 0x60, rl);
831 write_mixer(s, 0x62, rr);
832 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
833 s->mix.vol[9] = ((unsigned int)r << 8) | l;
834 #else
835 s->mix.vol[9] = val;
836 #endif
837 return put_user(s->mix.vol[9], (int *)arg);
838
839 case SOUND_MIXER_SPEAKER:
840 if (get_user(val, (int *)arg))
841 return -EFAULT;
842 l = val & 0xff;
843 if (l > 100)
844 l = 100;
845 else if (l < 2)
846 l = 2;
847 rl = (l - 2) / 14;
848 l = rl * 14 + 2;
849 write_mixer(s, 0x3c, rl);
850 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
851 s->mix.vol[7] = l * 0x101;
852 #else
853 s->mix.vol[7] = val;
854 #endif
855 return put_user(s->mix.vol[7], (int *)arg);
856
857 case SOUND_MIXER_RECLEV:
858 if (get_user(val, (int *)arg))
859 return -EFAULT;
860 l = (val << 1) & 0x1fe;
861 if (l > 200)
862 l = 200;
863 else if (l < 5)
864 l = 5;
865 r = (val >> 7) & 0x1fe;
866 if (r > 200)
867 r = 200;
868 else if (r < 5)
869 r = 5;
870 rl = (l - 5) / 13;
871 rr = (r - 5) / 13;
872 r = (rl * 13 + 5) / 2;
873 l = (rr * 13 + 5) / 2;
874 write_ctrl(s, 0xb4, (rl << 4) | rr);
875 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
876 s->mix.vol[8] = ((unsigned int)r << 8) | l;
877 #else
878 s->mix.vol[8] = val;
879 #endif
880 return put_user(s->mix.vol[8], (int *)arg);
881
882 default:
883 i = _IOC_NR(cmd);
884 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
885 return -EINVAL;
886 if (get_user(val, (int *)arg))
887 return -EFAULT;
888 l = (val << 1) & 0x1fe;
889 if (l > 200)
890 l = 200;
891 else if (l < 5)
892 l = 5;
893 r = (val >> 7) & 0x1fe;
894 if (r > 200)
895 r = 200;
896 else if (r < 5)
897 r = 5;
898 rl = (l - 5) / 13;
899 rr = (r - 5) / 13;
900 r = (rl * 13 + 5) / 2;
901 l = (rr * 13 + 5) / 2;
902 write_mixer(s, mixreg[vidx-1], (rl << 4) | rr);
903 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
904 s->mix.vol[vidx-1] = ((unsigned int)r << 8) | l;
905 #else
906 s->mix.vol[vidx-1] = val;
907 #endif
908 return put_user(s->mix.vol[vidx-1], (int *)arg);
909 }
910 }
911
912 /* --------------------------------------------------------------------- */
913
914 static int solo1_open_mixdev(struct inode *inode, struct file *file)
915 {
916 int minor = MINOR(inode->i_rdev);
917 struct solo1_state *s = NULL;
918 struct pci_dev *pci_dev;
919
920 pci_for_each_dev(pci_dev) {
921 struct pci_driver *drvr;
922 drvr = pci_dev_driver (pci_dev);
923 if (drvr != &solo1_driver)
924 continue;
925 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
926 if (!s)
927 continue;
928 if (s->dev_mixer == minor)
929 break;
930 }
931 if (!s)
932 return -ENODEV;
933 VALIDATE_STATE(s);
934 file->private_data = s;
935 return 0;
936 }
937
938 static int solo1_release_mixdev(struct inode *inode, struct file *file)
939 {
940 struct solo1_state *s = (struct solo1_state *)file->private_data;
941
942 VALIDATE_STATE(s);
943 return 0;
944 }
945
946 static int solo1_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
947 {
948 return mixer_ioctl((struct solo1_state *)file->private_data, cmd, arg);
949 }
950
951 static /*const*/ struct file_operations solo1_mixer_fops = {
952 owner: THIS_MODULE,
953 llseek: no_llseek,
954 ioctl: solo1_ioctl_mixdev,
955 open: solo1_open_mixdev,
956 release: solo1_release_mixdev,
957 };
958
959 /* --------------------------------------------------------------------- */
960
961 static int drain_dac(struct solo1_state *s, int nonblock)
962 {
963 DECLARE_WAITQUEUE(wait, current);
964 unsigned long flags;
965 int count;
966 unsigned tmo;
967
968 if (s->dma_dac.mapped)
969 return 0;
970 add_wait_queue(&s->dma_dac.wait, &wait);
971 for (;;) {
972 set_current_state(TASK_INTERRUPTIBLE);
973 spin_lock_irqsave(&s->lock, flags);
974 count = s->dma_dac.count;
975 spin_unlock_irqrestore(&s->lock, flags);
976 if (count <= 0)
977 break;
978 if (signal_pending(current))
979 break;
980 if (nonblock) {
981 remove_wait_queue(&s->dma_dac.wait, &wait);
982 set_current_state(TASK_RUNNING);
983 return -EBUSY;
984 }
985 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->rate;
986 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
987 tmo >>= 1;
988 if (s->channels > 1)
989 tmo >>= 1;
990 if (!schedule_timeout(tmo + 1))
991 printk(KERN_DEBUG "solo1: dma timed out??\n");
992 }
993 remove_wait_queue(&s->dma_dac.wait, &wait);
994 set_current_state(TASK_RUNNING);
995 if (signal_pending(current))
996 return -ERESTARTSYS;
997 return 0;
998 }
999
1000 /* --------------------------------------------------------------------- */
1001
1002 static ssize_t solo1_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1003 {
1004 struct solo1_state *s = (struct solo1_state *)file->private_data;
1005 DECLARE_WAITQUEUE(wait, current);
1006 ssize_t ret;
1007 unsigned long flags;
1008 unsigned swptr;
1009 int cnt;
1010
1011 VALIDATE_STATE(s);
1012 if (ppos != &file->f_pos)
1013 return -ESPIPE;
1014 if (s->dma_adc.mapped)
1015 return -ENXIO;
1016 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1017 return ret;
1018 if (!access_ok(VERIFY_WRITE, buffer, count))
1019 return -EFAULT;
1020 ret = 0;
1021 add_wait_queue(&s->dma_adc.wait, &wait);
1022 while (count > 0) {
1023 spin_lock_irqsave(&s->lock, flags);
1024 swptr = s->dma_adc.swptr;
1025 cnt = s->dma_adc.dmasize-swptr;
1026 if (s->dma_adc.count < cnt)
1027 cnt = s->dma_adc.count;
1028 if (cnt <= 0)
1029 __set_current_state(TASK_INTERRUPTIBLE);
1030 spin_unlock_irqrestore(&s->lock, flags);
1031 if (cnt > count)
1032 cnt = count;
1033 #ifdef DEBUGREC
1034 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x cnt: %u\n",
1035 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc), cnt);
1036 #endif
1037 if (cnt <= 0) {
1038 if (s->dma_adc.enabled)
1039 start_adc(s);
1040 #ifdef DEBUGREC
1041 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1042 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1043 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1044 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1045 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1046 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1047 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1048 #endif
1049 if (inb(s->ddmabase+15) & 1)
1050 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1051 if (file->f_flags & O_NONBLOCK) {
1052 if (!ret)
1053 ret = -EAGAIN;
1054 break;
1055 }
1056 schedule();
1057 #ifdef DEBUGREC
1058 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1059 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1060 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1061 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1062 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1063 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1064 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1065 #endif
1066 if (signal_pending(current)) {
1067 if (!ret)
1068 ret = -ERESTARTSYS;
1069 break;
1070 }
1071 continue;
1072 }
1073 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1074 if (!ret)
1075 ret = -EFAULT;
1076 break;
1077 }
1078 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1079 spin_lock_irqsave(&s->lock, flags);
1080 s->dma_adc.swptr = swptr;
1081 s->dma_adc.count -= cnt;
1082 spin_unlock_irqrestore(&s->lock, flags);
1083 count -= cnt;
1084 buffer += cnt;
1085 ret += cnt;
1086 if (s->dma_adc.enabled)
1087 start_adc(s);
1088 #ifdef DEBUGREC
1089 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x\n",
1090 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc));
1091 #endif
1092 }
1093 remove_wait_queue(&s->dma_adc.wait, &wait);
1094 set_current_state(TASK_RUNNING);
1095 return ret;
1096 }
1097
1098 static ssize_t solo1_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1099 {
1100 struct solo1_state *s = (struct solo1_state *)file->private_data;
1101 DECLARE_WAITQUEUE(wait, current);
1102 ssize_t ret;
1103 unsigned long flags;
1104 unsigned swptr;
1105 int cnt;
1106
1107 VALIDATE_STATE(s);
1108 if (ppos != &file->f_pos)
1109 return -ESPIPE;
1110 if (s->dma_dac.mapped)
1111 return -ENXIO;
1112 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1113 return ret;
1114 if (!access_ok(VERIFY_READ, buffer, count))
1115 return -EFAULT;
1116 #if 0
1117 printk(KERN_DEBUG "solo1_write: reg 70: 0x%02x 71: 0x%02x 72: 0x%02x 74: 0x%02x 76: 0x%02x 78: 0x%02x 7A: 0x%02x\n"
1118 KERN_DEBUG "solo1_write: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x SBstat: 0x%02x\n",
1119 read_mixer(s, 0x70), read_mixer(s, 0x71), read_mixer(s, 0x72), read_mixer(s, 0x74), read_mixer(s, 0x76),
1120 read_mixer(s, 0x78), read_mixer(s, 0x7a), inl(s->iobase), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1121 printk(KERN_DEBUG "solo1_write: reg 78: 0x%02x reg 7A: 0x%02x DMAcnt: 0x%04x DMAstat: 0x%02x SBstat: 0x%02x\n",
1122 read_mixer(s, 0x78), read_mixer(s, 0x7a), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1123 #endif
1124 ret = 0;
1125 add_wait_queue(&s->dma_dac.wait, &wait);
1126 while (count > 0) {
1127 spin_lock_irqsave(&s->lock, flags);
1128 if (s->dma_dac.count < 0) {
1129 s->dma_dac.count = 0;
1130 s->dma_dac.swptr = s->dma_dac.hwptr;
1131 }
1132 swptr = s->dma_dac.swptr;
1133 cnt = s->dma_dac.dmasize-swptr;
1134 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1135 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1136 if (cnt <= 0)
1137 __set_current_state(TASK_INTERRUPTIBLE);
1138 spin_unlock_irqrestore(&s->lock, flags);
1139 if (cnt > count)
1140 cnt = count;
1141 if (cnt <= 0) {
1142 if (s->dma_dac.enabled)
1143 start_dac(s);
1144 if (file->f_flags & O_NONBLOCK) {
1145 if (!ret)
1146 ret = -EAGAIN;
1147 break;
1148 }
1149 schedule();
1150 if (signal_pending(current)) {
1151 if (!ret)
1152 ret = -ERESTARTSYS;
1153 break;
1154 }
1155 continue;
1156 }
1157 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1158 if (!ret)
1159 ret = -EFAULT;
1160 break;
1161 }
1162 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1163 spin_lock_irqsave(&s->lock, flags);
1164 s->dma_dac.swptr = swptr;
1165 s->dma_dac.count += cnt;
1166 s->dma_dac.endcleared = 0;
1167 spin_unlock_irqrestore(&s->lock, flags);
1168 count -= cnt;
1169 buffer += cnt;
1170 ret += cnt;
1171 if (s->dma_dac.enabled)
1172 start_dac(s);
1173 }
1174 remove_wait_queue(&s->dma_dac.wait, &wait);
1175 set_current_state(TASK_RUNNING);
1176 return ret;
1177 }
1178
1179 /* No kernel lock - we have our own spinlock */
1180 static unsigned int solo1_poll(struct file *file, struct poll_table_struct *wait)
1181 {
1182 struct solo1_state *s = (struct solo1_state *)file->private_data;
1183 unsigned long flags;
1184 unsigned int mask = 0;
1185
1186 VALIDATE_STATE(s);
1187 if (file->f_mode & FMODE_WRITE) {
1188 if (!s->dma_dac.ready && prog_dmabuf_dac(s))
1189 return 0;
1190 poll_wait(file, &s->dma_dac.wait, wait);
1191 }
1192 if (file->f_mode & FMODE_READ) {
1193 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1194 return 0;
1195 poll_wait(file, &s->dma_adc.wait, wait);
1196 }
1197 spin_lock_irqsave(&s->lock, flags);
1198 solo1_update_ptr(s);
1199 if (file->f_mode & FMODE_READ) {
1200 if (s->dma_adc.mapped) {
1201 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1202 mask |= POLLIN | POLLRDNORM;
1203 } else {
1204 if (s->dma_adc.count > 0)
1205 mask |= POLLIN | POLLRDNORM;
1206 }
1207 }
1208 if (file->f_mode & FMODE_WRITE) {
1209 if (s->dma_dac.mapped) {
1210 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1211 mask |= POLLOUT | POLLWRNORM;
1212 } else {
1213 if ((signed)s->dma_dac.dmasize > s->dma_dac.count)
1214 mask |= POLLOUT | POLLWRNORM;
1215 }
1216 }
1217 spin_unlock_irqrestore(&s->lock, flags);
1218 return mask;
1219 }
1220
1221
1222 static int solo1_mmap(struct file *file, struct vm_area_struct *vma)
1223 {
1224 struct solo1_state *s = (struct solo1_state *)file->private_data;
1225 struct dmabuf *db;
1226 int ret = -EINVAL;
1227 unsigned long size;
1228
1229 VALIDATE_STATE(s);
1230 lock_kernel();
1231 if (vma->vm_flags & VM_WRITE) {
1232 if ((ret = prog_dmabuf_dac(s)) != 0)
1233 goto out;
1234 db = &s->dma_dac;
1235 } else if (vma->vm_flags & VM_READ) {
1236 if ((ret = prog_dmabuf_adc(s)) != 0)
1237 goto out;
1238 db = &s->dma_adc;
1239 } else
1240 goto out;
1241 ret = -EINVAL;
1242 if (vma->vm_pgoff != 0)
1243 goto out;
1244 size = vma->vm_end - vma->vm_start;
1245 if (size > (PAGE_SIZE << db->buforder))
1246 goto out;
1247 ret = -EAGAIN;
1248 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
1249 goto out;
1250 db->mapped = 1;
1251 ret = 0;
1252 out:
1253 unlock_kernel();
1254 return ret;
1255 }
1256
1257 static int solo1_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1258 {
1259 struct solo1_state *s = (struct solo1_state *)file->private_data;
1260 unsigned long flags;
1261 audio_buf_info abinfo;
1262 count_info cinfo;
1263 int val, mapped, ret, count;
1264 int div1, div2;
1265 unsigned rate1, rate2;
1266
1267 VALIDATE_STATE(s);
1268 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1269 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1270 switch (cmd) {
1271 case OSS_GETVERSION:
1272 return put_user(SOUND_VERSION, (int *)arg);
1273
1274 case SNDCTL_DSP_SYNC:
1275 if (file->f_mode & FMODE_WRITE)
1276 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
1277 return 0;
1278
1279 case SNDCTL_DSP_SETDUPLEX:
1280 return 0;
1281
1282 case SNDCTL_DSP_GETCAPS:
1283 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1284
1285 case SNDCTL_DSP_RESET:
1286 if (file->f_mode & FMODE_WRITE) {
1287 stop_dac(s);
1288 synchronize_irq();
1289 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1290 }
1291 if (file->f_mode & FMODE_READ) {
1292 stop_adc(s);
1293 synchronize_irq();
1294 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1295 }
1296 prog_codec(s);
1297 return 0;
1298
1299 case SNDCTL_DSP_SPEED:
1300 if (get_user(val, (int *)arg))
1301 return -EFAULT;
1302 if (val >= 0) {
1303 stop_adc(s);
1304 stop_dac(s);
1305 s->dma_adc.ready = s->dma_dac.ready = 0;
1306 /* program sampling rates */
1307 if (val > 48000)
1308 val = 48000;
1309 if (val < 6300)
1310 val = 6300;
1311 div1 = (768000 + val / 2) / val;
1312 rate1 = (768000 + div1 / 2) / div1;
1313 div1 = -div1;
1314 div2 = (793800 + val / 2) / val;
1315 rate2 = (793800 + div2 / 2) / div2;
1316 div2 = (-div2) & 0x7f;
1317 if (abs(val - rate2) < abs(val - rate1)) {
1318 rate1 = rate2;
1319 div1 = div2;
1320 }
1321 s->rate = rate1;
1322 s->clkdiv = div1;
1323 prog_codec(s);
1324 }
1325 return put_user(s->rate, (int *)arg);
1326
1327 case SNDCTL_DSP_STEREO:
1328 if (get_user(val, (int *)arg))
1329 return -EFAULT;
1330 stop_adc(s);
1331 stop_dac(s);
1332 s->dma_adc.ready = s->dma_dac.ready = 0;
1333 /* program channels */
1334 s->channels = val ? 2 : 1;
1335 prog_codec(s);
1336 return 0;
1337
1338 case SNDCTL_DSP_CHANNELS:
1339 if (get_user(val, (int *)arg))
1340 return -EFAULT;
1341 if (val != 0) {
1342 stop_adc(s);
1343 stop_dac(s);
1344 s->dma_adc.ready = s->dma_dac.ready = 0;
1345 /* program channels */
1346 s->channels = (val >= 2) ? 2 : 1;
1347 prog_codec(s);
1348 }
1349 return put_user(s->channels, (int *)arg);
1350
1351 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1352 return put_user(AFMT_S16_LE|AFMT_U16_LE|AFMT_S8|AFMT_U8, (int *)arg);
1353
1354 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1355 if (get_user(val, (int *)arg))
1356 return -EFAULT;
1357 if (val != AFMT_QUERY) {
1358 stop_adc(s);
1359 stop_dac(s);
1360 s->dma_adc.ready = s->dma_dac.ready = 0;
1361 /* program format */
1362 if (val != AFMT_S16_LE && val != AFMT_U16_LE &&
1363 val != AFMT_S8 && val != AFMT_U8)
1364 val = AFMT_U8;
1365 s->fmt = val;
1366 prog_codec(s);
1367 }
1368 return put_user(s->fmt, (int *)arg);
1369
1370 case SNDCTL_DSP_POST:
1371 return 0;
1372
1373 case SNDCTL_DSP_GETTRIGGER:
1374 val = 0;
1375 if (file->f_mode & s->ena & FMODE_READ)
1376 val |= PCM_ENABLE_INPUT;
1377 if (file->f_mode & s->ena & FMODE_WRITE)
1378 val |= PCM_ENABLE_OUTPUT;
1379 return put_user(val, (int *)arg);
1380
1381 case SNDCTL_DSP_SETTRIGGER:
1382 if (get_user(val, (int *)arg))
1383 return -EFAULT;
1384 if (file->f_mode & FMODE_READ) {
1385 if (val & PCM_ENABLE_INPUT) {
1386 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1387 return ret;
1388 s->dma_dac.enabled = 1;
1389 start_adc(s);
1390 if (inb(s->ddmabase+15) & 1)
1391 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1392 } else {
1393 s->dma_dac.enabled = 0;
1394 stop_adc(s);
1395 }
1396 }
1397 if (file->f_mode & FMODE_WRITE) {
1398 if (val & PCM_ENABLE_OUTPUT) {
1399 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1400 return ret;
1401 s->dma_dac.enabled = 1;
1402 start_dac(s);
1403 } else {
1404 s->dma_dac.enabled = 0;
1405 stop_dac(s);
1406 }
1407 }
1408 return 0;
1409
1410 case SNDCTL_DSP_GETOSPACE:
1411 if (!(file->f_mode & FMODE_WRITE))
1412 return -EINVAL;
1413 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1414 return val;
1415 spin_lock_irqsave(&s->lock, flags);
1416 solo1_update_ptr(s);
1417 abinfo.fragsize = s->dma_dac.fragsize;
1418 count = s->dma_dac.count;
1419 if (count < 0)
1420 count = 0;
1421 abinfo.bytes = s->dma_dac.dmasize - count;
1422 abinfo.fragstotal = s->dma_dac.numfrag;
1423 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1424 spin_unlock_irqrestore(&s->lock, flags);
1425 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1426
1427 case SNDCTL_DSP_GETISPACE:
1428 if (!(file->f_mode & FMODE_READ))
1429 return -EINVAL;
1430 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1431 return val;
1432 spin_lock_irqsave(&s->lock, flags);
1433 solo1_update_ptr(s);
1434 abinfo.fragsize = s->dma_adc.fragsize;
1435 abinfo.bytes = s->dma_adc.count;
1436 abinfo.fragstotal = s->dma_adc.numfrag;
1437 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1438 spin_unlock_irqrestore(&s->lock, flags);
1439 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1440
1441 case SNDCTL_DSP_NONBLOCK:
1442 file->f_flags |= O_NONBLOCK;
1443 return 0;
1444
1445 case SNDCTL_DSP_GETODELAY:
1446 if (!(file->f_mode & FMODE_WRITE))
1447 return -EINVAL;
1448 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1449 return val;
1450 spin_lock_irqsave(&s->lock, flags);
1451 solo1_update_ptr(s);
1452 count = s->dma_dac.count;
1453 spin_unlock_irqrestore(&s->lock, flags);
1454 if (count < 0)
1455 count = 0;
1456 return put_user(count, (int *)arg);
1457
1458 case SNDCTL_DSP_GETIPTR:
1459 if (!(file->f_mode & FMODE_READ))
1460 return -EINVAL;
1461 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1462 return val;
1463 spin_lock_irqsave(&s->lock, flags);
1464 solo1_update_ptr(s);
1465 cinfo.bytes = s->dma_adc.total_bytes;
1466 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1467 cinfo.ptr = s->dma_adc.hwptr;
1468 if (s->dma_adc.mapped)
1469 s->dma_adc.count &= s->dma_adc.fragsize-1;
1470 spin_unlock_irqrestore(&s->lock, flags);
1471 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1472
1473 case SNDCTL_DSP_GETOPTR:
1474 if (!(file->f_mode & FMODE_WRITE))
1475 return -EINVAL;
1476 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1477 return val;
1478 spin_lock_irqsave(&s->lock, flags);
1479 solo1_update_ptr(s);
1480 cinfo.bytes = s->dma_dac.total_bytes;
1481 count = s->dma_dac.count;
1482 if (count < 0)
1483 count = 0;
1484 cinfo.blocks = count >> s->dma_dac.fragshift;
1485 cinfo.ptr = s->dma_dac.hwptr;
1486 if (s->dma_dac.mapped)
1487 s->dma_dac.count &= s->dma_dac.fragsize-1;
1488 spin_unlock_irqrestore(&s->lock, flags);
1489 #if 0
1490 printk(KERN_DEBUG "esssolo1: GETOPTR: bytes %u blocks %u ptr %u, buforder %u numfrag %u fragshift %u\n"
1491 KERN_DEBUG "esssolo1: swptr %u count %u fragsize %u dmasize %u fragsamples %u\n",
1492 cinfo.bytes, cinfo.blocks, cinfo.ptr, s->dma_dac.buforder, s->dma_dac.numfrag, s->dma_dac.fragshift,
1493 s->dma_dac.swptr, s->dma_dac.count, s->dma_dac.fragsize, s->dma_dac.dmasize, s->dma_dac.fragsamples);
1494 #endif
1495 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1496
1497 case SNDCTL_DSP_GETBLKSIZE:
1498 if (file->f_mode & FMODE_WRITE) {
1499 if ((val = prog_dmabuf_dac(s)))
1500 return val;
1501 return put_user(s->dma_dac.fragsize, (int *)arg);
1502 }
1503 if ((val = prog_dmabuf_adc(s)))
1504 return val;
1505 return put_user(s->dma_adc.fragsize, (int *)arg);
1506
1507 case SNDCTL_DSP_SETFRAGMENT:
1508 if (get_user(val, (int *)arg))
1509 return -EFAULT;
1510 if (file->f_mode & FMODE_READ) {
1511 s->dma_adc.ossfragshift = val & 0xffff;
1512 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1513 if (s->dma_adc.ossfragshift < 4)
1514 s->dma_adc.ossfragshift = 4;
1515 if (s->dma_adc.ossfragshift > 15)
1516 s->dma_adc.ossfragshift = 15;
1517 if (s->dma_adc.ossmaxfrags < 4)
1518 s->dma_adc.ossmaxfrags = 4;
1519 }
1520 if (file->f_mode & FMODE_WRITE) {
1521 s->dma_dac.ossfragshift = val & 0xffff;
1522 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1523 if (s->dma_dac.ossfragshift < 4)
1524 s->dma_dac.ossfragshift = 4;
1525 if (s->dma_dac.ossfragshift > 15)
1526 s->dma_dac.ossfragshift = 15;
1527 if (s->dma_dac.ossmaxfrags < 4)
1528 s->dma_dac.ossmaxfrags = 4;
1529 }
1530 return 0;
1531
1532 case SNDCTL_DSP_SUBDIVIDE:
1533 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1534 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1535 return -EINVAL;
1536 if (get_user(val, (int *)arg))
1537 return -EFAULT;
1538 if (val != 1 && val != 2 && val != 4)
1539 return -EINVAL;
1540 if (file->f_mode & FMODE_READ)
1541 s->dma_adc.subdivision = val;
1542 if (file->f_mode & FMODE_WRITE)
1543 s->dma_dac.subdivision = val;
1544 return 0;
1545
1546 case SOUND_PCM_READ_RATE:
1547 return put_user(s->rate, (int *)arg);
1548
1549 case SOUND_PCM_READ_CHANNELS:
1550 return put_user(s->channels, (int *)arg);
1551
1552 case SOUND_PCM_READ_BITS:
1553 return put_user((s->fmt & (AFMT_S8|AFMT_U8)) ? 8 : 16, (int *)arg);
1554
1555 case SOUND_PCM_WRITE_FILTER:
1556 case SNDCTL_DSP_SETSYNCRO:
1557 case SOUND_PCM_READ_FILTER:
1558 return -EINVAL;
1559
1560 }
1561 return mixer_ioctl(s, cmd, arg);
1562 }
1563
1564 static int solo1_release(struct inode *inode, struct file *file)
1565 {
1566 struct solo1_state *s = (struct solo1_state *)file->private_data;
1567
1568 VALIDATE_STATE(s);
1569 lock_kernel();
1570 if (file->f_mode & FMODE_WRITE)
1571 drain_dac(s, file->f_flags & O_NONBLOCK);
1572 down(&s->open_sem);
1573 if (file->f_mode & FMODE_WRITE) {
1574 stop_dac(s);
1575 outb(0, s->iobase+6); /* disable DMA */
1576 dealloc_dmabuf(s, &s->dma_dac);
1577 }
1578 if (file->f_mode & FMODE_READ) {
1579 stop_adc(s);
1580 outb(1, s->ddmabase+0xf); /* mask DMA channel */
1581 outb(0, s->ddmabase+0xd); /* DMA master clear */
1582 dealloc_dmabuf(s, &s->dma_adc);
1583 }
1584 s->open_mode &= ~(FMODE_READ | FMODE_WRITE);
1585 wake_up(&s->open_wait);
1586 up(&s->open_sem);
1587 unlock_kernel();
1588 return 0;
1589 }
1590
1591 static int solo1_open(struct inode *inode, struct file *file)
1592 {
1593 int minor = MINOR(inode->i_rdev);
1594 DECLARE_WAITQUEUE(wait, current);
1595 struct solo1_state *s = NULL;
1596 struct pci_dev *pci_dev;
1597
1598 pci_for_each_dev(pci_dev) {
1599 struct pci_driver *drvr;
1600
1601 drvr = pci_dev_driver(pci_dev);
1602 if (drvr != &solo1_driver)
1603 continue;
1604 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1605 if (!s)
1606 continue;
1607 if (!((s->dev_audio ^ minor) & ~0xf))
1608 break;
1609 }
1610 if (!s)
1611 return -ENODEV;
1612 VALIDATE_STATE(s);
1613 file->private_data = s;
1614 /* wait for device to become free */
1615 down(&s->open_sem);
1616 while (s->open_mode & (FMODE_READ | FMODE_WRITE)) {
1617 if (file->f_flags & O_NONBLOCK) {
1618 up(&s->open_sem);
1619 return -EBUSY;
1620 }
1621 add_wait_queue(&s->open_wait, &wait);
1622 __set_current_state(TASK_INTERRUPTIBLE);
1623 up(&s->open_sem);
1624 schedule();
1625 remove_wait_queue(&s->open_wait, &wait);
1626 set_current_state(TASK_RUNNING);
1627 if (signal_pending(current))
1628 return -ERESTARTSYS;
1629 down(&s->open_sem);
1630 }
1631 s->fmt = AFMT_U8;
1632 s->channels = 1;
1633 s->rate = 8000;
1634 s->clkdiv = 96 | 0x80;
1635 s->ena = 0;
1636 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1637 s->dma_adc.enabled = 1;
1638 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
1639 s->dma_dac.enabled = 1;
1640 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1641 up(&s->open_sem);
1642 prog_codec(s);
1643 return 0;
1644 }
1645
1646 static /*const*/ struct file_operations solo1_audio_fops = {
1647 owner: THIS_MODULE,
1648 llseek: no_llseek,
1649 read: solo1_read,
1650 write: solo1_write,
1651 poll: solo1_poll,
1652 ioctl: solo1_ioctl,
1653 mmap: solo1_mmap,
1654 open: solo1_open,
1655 release: solo1_release,
1656 };
1657
1658 /* --------------------------------------------------------------------- */
1659
1660 /* hold spinlock for the following! */
1661 static void solo1_handle_midi(struct solo1_state *s)
1662 {
1663 unsigned char ch;
1664 int wake;
1665
1666 if (!(s->mpubase))
1667 return;
1668 wake = 0;
1669 while (!(inb(s->mpubase+1) & 0x80)) {
1670 ch = inb(s->mpubase);
1671 if (s->midi.icnt < MIDIINBUF) {
1672 s->midi.ibuf[s->midi.iwr] = ch;
1673 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1674 s->midi.icnt++;
1675 }
1676 wake = 1;
1677 }
1678 if (wake)
1679 wake_up(&s->midi.iwait);
1680 wake = 0;
1681 while (!(inb(s->mpubase+1) & 0x40) && s->midi.ocnt > 0) {
1682 outb(s->midi.obuf[s->midi.ord], s->mpubase);
1683 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1684 s->midi.ocnt--;
1685 if (s->midi.ocnt < MIDIOUTBUF-16)
1686 wake = 1;
1687 }
1688 if (wake)
1689 wake_up(&s->midi.owait);
1690 }
1691
1692 static void solo1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1693 {
1694 struct solo1_state *s = (struct solo1_state *)dev_id;
1695 unsigned int intsrc;
1696
1697 /* fastpath out, to ease interrupt sharing */
1698 intsrc = inb(s->iobase+7); /* get interrupt source(s) */
1699 if (!intsrc)
1700 return;
1701 (void)inb(s->sbbase+0xe); /* clear interrupt */
1702 spin_lock(&s->lock);
1703 /* clear audio interrupts first */
1704 if (intsrc & 0x20)
1705 write_mixer(s, 0x7a, read_mixer(s, 0x7a) & 0x7f);
1706 solo1_update_ptr(s);
1707 solo1_handle_midi(s);
1708 spin_unlock(&s->lock);
1709 }
1710
1711 static void solo1_midi_timer(unsigned long data)
1712 {
1713 struct solo1_state *s = (struct solo1_state *)data;
1714 unsigned long flags;
1715
1716 spin_lock_irqsave(&s->lock, flags);
1717 solo1_handle_midi(s);
1718 spin_unlock_irqrestore(&s->lock, flags);
1719 s->midi.timer.expires = jiffies+1;
1720 add_timer(&s->midi.timer);
1721 }
1722
1723 /* --------------------------------------------------------------------- */
1724
1725 static ssize_t solo1_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1726 {
1727 struct solo1_state *s = (struct solo1_state *)file->private_data;
1728 DECLARE_WAITQUEUE(wait, current);
1729 ssize_t ret;
1730 unsigned long flags;
1731 unsigned ptr;
1732 int cnt;
1733
1734 VALIDATE_STATE(s);
1735 if (ppos != &file->f_pos)
1736 return -ESPIPE;
1737 if (!access_ok(VERIFY_WRITE, buffer, count))
1738 return -EFAULT;
1739 if (count == 0)
1740 return 0;
1741 ret = 0;
1742 add_wait_queue(&s->midi.iwait, &wait);
1743 while (count > 0) {
1744 spin_lock_irqsave(&s->lock, flags);
1745 ptr = s->midi.ird;
1746 cnt = MIDIINBUF - ptr;
1747 if (s->midi.icnt < cnt)
1748 cnt = s->midi.icnt;
1749 if (cnt <= 0)
1750 __set_current_state(TASK_INTERRUPTIBLE);
1751 spin_unlock_irqrestore(&s->lock, flags);
1752 if (cnt > count)
1753 cnt = count;
1754 if (cnt <= 0) {
1755 if (file->f_flags & O_NONBLOCK) {
1756 if (!ret)
1757 ret = -EAGAIN;
1758 break;
1759 }
1760 schedule();
1761 if (signal_pending(current)) {
1762 if (!ret)
1763 ret = -ERESTARTSYS;
1764 break;
1765 }
1766 continue;
1767 }
1768 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
1769 if (!ret)
1770 ret = -EFAULT;
1771 break;
1772 }
1773 ptr = (ptr + cnt) % MIDIINBUF;
1774 spin_lock_irqsave(&s->lock, flags);
1775 s->midi.ird = ptr;
1776 s->midi.icnt -= cnt;
1777 spin_unlock_irqrestore(&s->lock, flags);
1778 count -= cnt;
1779 buffer += cnt;
1780 ret += cnt;
1781 break;
1782 }
1783 __set_current_state(TASK_RUNNING);
1784 remove_wait_queue(&s->midi.iwait, &wait);
1785 return ret;
1786 }
1787
1788 static ssize_t solo1_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1789 {
1790 struct solo1_state *s = (struct solo1_state *)file->private_data;
1791 DECLARE_WAITQUEUE(wait, current);
1792 ssize_t ret;
1793 unsigned long flags;
1794 unsigned ptr;
1795 int cnt;
1796
1797 VALIDATE_STATE(s);
1798 if (ppos != &file->f_pos)
1799 return -ESPIPE;
1800 if (!access_ok(VERIFY_READ, buffer, count))
1801 return -EFAULT;
1802 if (count == 0)
1803 return 0;
1804 ret = 0;
1805 add_wait_queue(&s->midi.owait, &wait);
1806 while (count > 0) {
1807 spin_lock_irqsave(&s->lock, flags);
1808 ptr = s->midi.owr;
1809 cnt = MIDIOUTBUF - ptr;
1810 if (s->midi.ocnt + cnt > MIDIOUTBUF)
1811 cnt = MIDIOUTBUF - s->midi.ocnt;
1812 if (cnt <= 0) {
1813 __set_current_state(TASK_INTERRUPTIBLE);
1814 solo1_handle_midi(s);
1815 }
1816 spin_unlock_irqrestore(&s->lock, flags);
1817 if (cnt > count)
1818 cnt = count;
1819 if (cnt <= 0) {
1820 if (file->f_flags & O_NONBLOCK) {
1821 if (!ret)
1822 ret = -EAGAIN;
1823 break;
1824 }
1825 schedule();
1826 if (signal_pending(current)) {
1827 if (!ret)
1828 ret = -ERESTARTSYS;
1829 break;
1830 }
1831 continue;
1832 }
1833 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
1834 if (!ret)
1835 ret = -EFAULT;
1836 break;
1837 }
1838 ptr = (ptr + cnt) % MIDIOUTBUF;
1839 spin_lock_irqsave(&s->lock, flags);
1840 s->midi.owr = ptr;
1841 s->midi.ocnt += cnt;
1842 spin_unlock_irqrestore(&s->lock, flags);
1843 count -= cnt;
1844 buffer += cnt;
1845 ret += cnt;
1846 spin_lock_irqsave(&s->lock, flags);
1847 solo1_handle_midi(s);
1848 spin_unlock_irqrestore(&s->lock, flags);
1849 }
1850 __set_current_state(TASK_RUNNING);
1851 remove_wait_queue(&s->midi.owait, &wait);
1852 return ret;
1853 }
1854
1855 /* No kernel lock - we have our own spinlock */
1856 static unsigned int solo1_midi_poll(struct file *file, struct poll_table_struct *wait)
1857 {
1858 struct solo1_state *s = (struct solo1_state *)file->private_data;
1859 unsigned long flags;
1860 unsigned int mask = 0;
1861
1862 VALIDATE_STATE(s);
1863 if (file->f_flags & FMODE_WRITE)
1864 poll_wait(file, &s->midi.owait, wait);
1865 if (file->f_flags & FMODE_READ)
1866 poll_wait(file, &s->midi.iwait, wait);
1867 spin_lock_irqsave(&s->lock, flags);
1868 if (file->f_flags & FMODE_READ) {
1869 if (s->midi.icnt > 0)
1870 mask |= POLLIN | POLLRDNORM;
1871 }
1872 if (file->f_flags & FMODE_WRITE) {
1873 if (s->midi.ocnt < MIDIOUTBUF)
1874 mask |= POLLOUT | POLLWRNORM;
1875 }
1876 spin_unlock_irqrestore(&s->lock, flags);
1877 return mask;
1878 }
1879
1880 static int solo1_midi_open(struct inode *inode, struct file *file)
1881 {
1882 int minor = MINOR(inode->i_rdev);
1883 DECLARE_WAITQUEUE(wait, current);
1884 unsigned long flags;
1885 struct solo1_state *s = NULL;
1886 struct pci_dev *pci_dev;
1887
1888 pci_for_each_dev(pci_dev) {
1889 struct pci_driver *drvr;
1890
1891 drvr = pci_dev_driver(pci_dev);
1892 if (drvr != &solo1_driver)
1893 continue;
1894 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1895 if (!s)
1896 continue;
1897 if (s->dev_midi == minor)
1898 break;
1899 }
1900 if (!s)
1901 return -ENODEV;
1902 VALIDATE_STATE(s);
1903 file->private_data = s;
1904 /* wait for device to become free */
1905 down(&s->open_sem);
1906 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
1907 if (file->f_flags & O_NONBLOCK) {
1908 up(&s->open_sem);
1909 return -EBUSY;
1910 }
1911 add_wait_queue(&s->open_wait, &wait);
1912 __set_current_state(TASK_INTERRUPTIBLE);
1913 up(&s->open_sem);
1914 schedule();
1915 remove_wait_queue(&s->open_wait, &wait);
1916 set_current_state(TASK_RUNNING);
1917 if (signal_pending(current))
1918 return -ERESTARTSYS;
1919 down(&s->open_sem);
1920 }
1921 spin_lock_irqsave(&s->lock, flags);
1922 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1923 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1924 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1925 outb(0xff, s->mpubase+1); /* reset command */
1926 outb(0x3f, s->mpubase+1); /* uart command */
1927 if (!(inb(s->mpubase+1) & 0x80))
1928 inb(s->mpubase);
1929 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1930 outb(0xb0, s->iobase + 7); /* enable A1, A2, MPU irq's */
1931 init_timer(&s->midi.timer);
1932 s->midi.timer.expires = jiffies+1;
1933 s->midi.timer.data = (unsigned long)s;
1934 s->midi.timer.function = solo1_midi_timer;
1935 add_timer(&s->midi.timer);
1936 }
1937 if (file->f_mode & FMODE_READ) {
1938 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1939 }
1940 if (file->f_mode & FMODE_WRITE) {
1941 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1942 }
1943 spin_unlock_irqrestore(&s->lock, flags);
1944 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
1945 up(&s->open_sem);
1946 return 0;
1947 }
1948
1949 static int solo1_midi_release(struct inode *inode, struct file *file)
1950 {
1951 struct solo1_state *s = (struct solo1_state *)file->private_data;
1952 DECLARE_WAITQUEUE(wait, current);
1953 unsigned long flags;
1954 unsigned count, tmo;
1955
1956 VALIDATE_STATE(s);
1957
1958 lock_kernel();
1959 if (file->f_mode & FMODE_WRITE) {
1960 add_wait_queue(&s->midi.owait, &wait);
1961 for (;;) {
1962 __set_current_state(TASK_INTERRUPTIBLE);
1963 spin_lock_irqsave(&s->lock, flags);
1964 count = s->midi.ocnt;
1965 spin_unlock_irqrestore(&s->lock, flags);
1966 if (count <= 0)
1967 break;
1968 if (signal_pending(current))
1969 break;
1970 if (file->f_flags & O_NONBLOCK) {
1971 remove_wait_queue(&s->midi.owait, &wait);
1972 set_current_state(TASK_RUNNING);
1973 unlock_kernel();
1974 return -EBUSY;
1975 }
1976 tmo = (count * HZ) / 3100;
1977 if (!schedule_timeout(tmo ? : 1) && tmo)
1978 printk(KERN_DEBUG "solo1: midi timed out??\n");
1979 }
1980 remove_wait_queue(&s->midi.owait, &wait);
1981 set_current_state(TASK_RUNNING);
1982 }
1983 down(&s->open_sem);
1984 s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
1985 spin_lock_irqsave(&s->lock, flags);
1986 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1987 outb(0x30, s->iobase + 7); /* enable A1, A2 irq's */
1988 del_timer(&s->midi.timer);
1989 }
1990 spin_unlock_irqrestore(&s->lock, flags);
1991 wake_up(&s->open_wait);
1992 up(&s->open_sem);
1993 unlock_kernel();
1994 return 0;
1995 }
1996
1997 static /*const*/ struct file_operations solo1_midi_fops = {
1998 owner: THIS_MODULE,
1999 llseek: no_llseek,
2000 read: solo1_midi_read,
2001 write: solo1_midi_write,
2002 poll: solo1_midi_poll,
2003 open: solo1_midi_open,
2004 release: solo1_midi_release,
2005 };
2006
2007 /* --------------------------------------------------------------------- */
2008
2009 static int solo1_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2010 {
2011 static const unsigned char op_offset[18] = {
2012 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
2013 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
2014 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
2015 };
2016 struct solo1_state *s = (struct solo1_state *)file->private_data;
2017 struct dm_fm_voice v;
2018 struct dm_fm_note n;
2019 struct dm_fm_params p;
2020 unsigned int io;
2021 unsigned int regb;
2022
2023 switch (cmd) {
2024 case FM_IOCTL_RESET:
2025 for (regb = 0xb0; regb < 0xb9; regb++) {
2026 outb(regb, s->sbbase);
2027 outb(0, s->sbbase+1);
2028 outb(regb, s->sbbase+2);
2029 outb(0, s->sbbase+3);
2030 }
2031 return 0;
2032
2033 case FM_IOCTL_PLAY_NOTE:
2034 if (copy_from_user(&n, (void *)arg, sizeof(n)))
2035 return -EFAULT;
2036 if (n.voice >= 18)
2037 return -EINVAL;
2038 if (n.voice >= 9) {
2039 regb = n.voice - 9;
2040 io = s->sbbase+2;
2041 } else {
2042 regb = n.voice;
2043 io = s->sbbase;
2044 }
2045 outb(0xa0 + regb, io);
2046 outb(n.fnum & 0xff, io+1);
2047 outb(0xb0 + regb, io);
2048 outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
2049 return 0;
2050
2051 case FM_IOCTL_SET_VOICE:
2052 if (copy_from_user(&v, (void *)arg, sizeof(v)))
2053 return -EFAULT;
2054 if (v.voice >= 18)
2055 return -EINVAL;
2056 regb = op_offset[v.voice];
2057 io = s->sbbase + ((v.op & 1) << 1);
2058 outb(0x20 + regb, io);
2059 outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
2060 ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
2061 outb(0x40 + regb, io);
2062 outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
2063 outb(0x60 + regb, io);
2064 outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
2065 outb(0x80 + regb, io);
2066 outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
2067 outb(0xe0 + regb, io);
2068 outb(v.waveform & 0x7, io+1);
2069 if (n.voice >= 9) {
2070 regb = n.voice - 9;
2071 io = s->sbbase+2;
2072 } else {
2073 regb = n.voice;
2074 io = s->sbbase;
2075 }
2076 outb(0xc0 + regb, io);
2077 outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
2078 (v.connection & 1), io+1);
2079 return 0;
2080
2081 case FM_IOCTL_SET_PARAMS:
2082 if (copy_from_user(&p, (void *)arg, sizeof(p)))
2083 return -EFAULT;
2084 outb(0x08, s->sbbase);
2085 outb((p.kbd_split & 1) << 6, s->sbbase+1);
2086 outb(0xbd, s->sbbase);
2087 outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
2088 ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->sbbase+1);
2089 return 0;
2090
2091 case FM_IOCTL_SET_OPL:
2092 outb(4, s->sbbase+2);
2093 outb(arg, s->sbbase+3);
2094 return 0;
2095
2096 case FM_IOCTL_SET_MODE:
2097 outb(5, s->sbbase+2);
2098 outb(arg & 1, s->sbbase+3);
2099 return 0;
2100
2101 default:
2102 return -EINVAL;
2103 }
2104 }
2105
2106 static int solo1_dmfm_open(struct inode *inode, struct file *file)
2107 {
2108 int minor = MINOR(inode->i_rdev);
2109 DECLARE_WAITQUEUE(wait, current);
2110 struct solo1_state *s = NULL;
2111 struct pci_dev *pci_dev;
2112
2113 pci_for_each_dev(pci_dev) {
2114 struct pci_driver *drvr;
2115
2116 drvr = pci_dev_driver(pci_dev);
2117 if (drvr != &solo1_driver)
2118 continue;
2119 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2120 if (!s)
2121 continue;
2122 if (s->dev_dmfm == minor)
2123 break;
2124 }
2125 if (!s)
2126 return -ENODEV;
2127 VALIDATE_STATE(s);
2128 file->private_data = s;
2129 /* wait for device to become free */
2130 down(&s->open_sem);
2131 while (s->open_mode & FMODE_DMFM) {
2132 if (file->f_flags & O_NONBLOCK) {
2133 up(&s->open_sem);
2134 return -EBUSY;
2135 }
2136 add_wait_queue(&s->open_wait, &wait);
2137 __set_current_state(TASK_INTERRUPTIBLE);
2138 up(&s->open_sem);
2139 schedule();
2140 remove_wait_queue(&s->open_wait, &wait);
2141 set_current_state(TASK_RUNNING);
2142 if (signal_pending(current))
2143 return -ERESTARTSYS;
2144 down(&s->open_sem);
2145 }
2146 if (!request_region(s->sbbase, FMSYNTH_EXTENT, "ESS Solo1")) {
2147 up(&s->open_sem);
2148 printk(KERN_ERR "solo1: FM synth io ports in use, opl3 loaded?\n");
2149 return -EBUSY;
2150 }
2151 /* init the stuff */
2152 outb(1, s->sbbase);
2153 outb(0x20, s->sbbase+1); /* enable waveforms */
2154 outb(4, s->sbbase+2);
2155 outb(0, s->sbbase+3); /* no 4op enabled */
2156 outb(5, s->sbbase+2);
2157 outb(1, s->sbbase+3); /* enable OPL3 */
2158 s->open_mode |= FMODE_DMFM;
2159 up(&s->open_sem);
2160 return 0;
2161 }
2162
2163 static int solo1_dmfm_release(struct inode *inode, struct file *file)
2164 {
2165 struct solo1_state *s = (struct solo1_state *)file->private_data;
2166 unsigned int regb;
2167
2168 VALIDATE_STATE(s);
2169 lock_kernel();
2170 down(&s->open_sem);
2171 s->open_mode &= ~FMODE_DMFM;
2172 for (regb = 0xb0; regb < 0xb9; regb++) {
2173 outb(regb, s->sbbase);
2174 outb(0, s->sbbase+1);
2175 outb(regb, s->sbbase+2);
2176 outb(0, s->sbbase+3);
2177 }
2178 release_region(s->sbbase, FMSYNTH_EXTENT);
2179 wake_up(&s->open_wait);
2180 up(&s->open_sem);
2181 unlock_kernel();
2182 return 0;
2183 }
2184
2185 static /*const*/ struct file_operations solo1_dmfm_fops = {
2186 owner: THIS_MODULE,
2187 llseek: no_llseek,
2188 ioctl: solo1_dmfm_ioctl,
2189 open: solo1_dmfm_open,
2190 release: solo1_dmfm_release,
2191 };
2192
2193 /* --------------------------------------------------------------------- */
2194
2195 static struct initvol {
2196 int mixch;
2197 int vol;
2198 } initvol[] __initdata = {
2199 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2200 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2201 { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
2202 { SOUND_MIXER_WRITE_CD, 0x4040 },
2203 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2204 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2205 { SOUND_MIXER_WRITE_LINE2, 0x4040 },
2206 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2207 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2208 { SOUND_MIXER_WRITE_MIC, 0x4040 }
2209 };
2210
2211 static int setup_solo1(struct solo1_state *s)
2212 {
2213 struct pci_dev *pcidev = s->dev;
2214 mm_segment_t fs;
2215 int i, val;
2216
2217 /* initialize DDMA base address */
2218 printk(KERN_DEBUG "solo1: ddma base address: 0x%lx\n", s->ddmabase);
2219 pci_write_config_word(pcidev, 0x60, (s->ddmabase & (~0xf)) | 1);
2220 /* set DMA policy to DDMA, IRQ emulation off (CLKRUN disabled for now) */
2221 pci_write_config_dword(pcidev, 0x50, 0);
2222 /* disable legacy audio address decode */
2223 pci_write_config_word(pcidev, 0x40, 0x907f);
2224
2225 /* initialize the chips */
2226 if (!reset_ctrl(s)) {
2227 printk(KERN_ERR "esssolo1: cannot reset controller\n");
2228 return -1;
2229 }
2230 outb(0xb0, s->iobase+7); /* enable A1, A2, MPU irq's */
2231
2232 /* initialize mixer regs */
2233 write_mixer(s, 0x7f, 0); /* disable music digital recording */
2234 write_mixer(s, 0x7d, 0x0c); /* enable mic preamp, MONO_OUT is 2nd DAC right channel */
2235 write_mixer(s, 0x64, 0x45); /* volume control */
2236 write_mixer(s, 0x48, 0x10); /* enable music DAC/ES6xx interface */
2237 write_mixer(s, 0x50, 0); /* disable spatializer */
2238 write_mixer(s, 0x52, 0);
2239 write_mixer(s, 0x14, 0); /* DAC1 minimum volume */
2240 write_mixer(s, 0x71, 0x20); /* enable new 0xA1 reg format */
2241 outb(0, s->ddmabase+0xd); /* DMA master clear */
2242 outb(1, s->ddmabase+0xf); /* mask channel */
2243 /*outb(0, s->ddmabase+0x8);*/ /* enable controller (enable is low active!!) */
2244
2245 pci_set_master(pcidev); /* enable bus mastering */
2246
2247 fs = get_fs();
2248 set_fs(KERNEL_DS);
2249 val = SOUND_MASK_LINE;
2250 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2251 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2252 val = initvol[i].vol;
2253 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2254 }
2255 val = 1; /* enable mic preamp */
2256 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long)&val);
2257 set_fs(fs);
2258 return 0;
2259 }
2260
2261 static int
2262 solo1_suspend(struct pci_dev *pci_dev, u32 state) {
2263 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2264 if (!s)
2265 return 1;
2266 outb(0, s->iobase+6);
2267 /* DMA master clear */
2268 outb(0, s->ddmabase+0xd);
2269 /* reset sequencer and FIFO */
2270 outb(3, s->sbbase+6);
2271 /* turn off DDMA controller address space */
2272 pci_write_config_word(s->dev, 0x60, 0);
2273 return 0;
2274 }
2275
2276 static int
2277 solo1_resume(struct pci_dev *pci_dev) {
2278 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2279 if (!s)
2280 return 1;
2281 setup_solo1(s);
2282 return 0;
2283 }
2284
2285 static int __devinit solo1_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2286 {
2287 struct solo1_state *s;
2288 int ret;
2289
2290 if ((ret=pci_enable_device(pcidev)))
2291 return ret;
2292 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO) ||
2293 !(pci_resource_flags(pcidev, 1) & IORESOURCE_IO) ||
2294 !(pci_resource_flags(pcidev, 2) & IORESOURCE_IO) ||
2295 !(pci_resource_flags(pcidev, 3) & IORESOURCE_IO))
2296 return -ENODEV;
2297 if (pcidev->irq == 0)
2298 return -ENODEV;
2299
2300 /* Recording requires 24-bit DMA, so attempt to set dma mask
2301 * to 24 bits first, then 32 bits (playback only) if that fails.
2302 */
2303 if (pci_set_dma_mask(pcidev, 0x00ffffff) &&
2304 pci_set_dma_mask(pcidev, 0xffffffff)) {
2305 printk(KERN_WARNING "solo1: architecture does not support 24bit or 32bit PCI busmaster DMA\n");
2306 return -ENODEV;
2307 }
2308
2309 if (!(s = kmalloc(sizeof(struct solo1_state), GFP_KERNEL))) {
2310 printk(KERN_WARNING "solo1: out of memory\n");
2311 return -ENOMEM;
2312 }
2313 memset(s, 0, sizeof(struct solo1_state));
2314 init_waitqueue_head(&s->dma_adc.wait);
2315 init_waitqueue_head(&s->dma_dac.wait);
2316 init_waitqueue_head(&s->open_wait);
2317 init_waitqueue_head(&s->midi.iwait);
2318 init_waitqueue_head(&s->midi.owait);
2319 init_MUTEX(&s->open_sem);
2320 spin_lock_init(&s->lock);
2321 s->magic = SOLO1_MAGIC;
2322 s->dev = pcidev;
2323 s->iobase = pci_resource_start(pcidev, 0);
2324 s->sbbase = pci_resource_start(pcidev, 1);
2325 s->vcbase = pci_resource_start(pcidev, 2);
2326 s->ddmabase = s->vcbase + DDMABASE_OFFSET;
2327 s->mpubase = pci_resource_start(pcidev, 3);
2328 s->gameport.io = pci_resource_start(pcidev, 4);
2329 s->irq = pcidev->irq;
2330 ret = -EBUSY;
2331 if (!request_region(s->iobase, IOBASE_EXTENT, "ESS Solo1")) {
2332 printk(KERN_ERR "solo1: io ports in use\n");
2333 goto err_region1;
2334 }
2335 if (!request_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT, "ESS Solo1")) {
2336 printk(KERN_ERR "solo1: io ports in use\n");
2337 goto err_region2;
2338 }
2339 if (!request_region(s->ddmabase, DDMABASE_EXTENT, "ESS Solo1")) {
2340 printk(KERN_ERR "solo1: io ports in use\n");
2341 goto err_region3;
2342 }
2343 if (!request_region(s->mpubase, MPUBASE_EXTENT, "ESS Solo1")) {
2344 printk(KERN_ERR "solo1: io ports in use\n");
2345 goto err_region4;
2346 }
2347 if (s->gameport.io && !request_region(s->gameport.io, GAMEPORT_EXTENT, "ESS Solo1")) {
2348 printk(KERN_ERR "solo1: gameport io ports in use\n");
2349 s->gameport.io = 0;
2350 }
2351 if ((ret=request_irq(s->irq,solo1_interrupt,SA_SHIRQ,"ESS Solo1",s))) {
2352 printk(KERN_ERR "solo1: irq %u in use\n", s->irq);
2353 goto err_irq;
2354 }
2355 printk(KERN_INFO "solo1: joystick port at %#x\n", s->gameport.io+1);
2356 /* register devices */
2357 if ((s->dev_audio = register_sound_dsp(&solo1_audio_fops, -1)) < 0) {
2358 ret = s->dev_audio;
2359 goto err_dev1;
2360 }
2361 if ((s->dev_mixer = register_sound_mixer(&solo1_mixer_fops, -1)) < 0) {
2362 ret = s->dev_mixer;
2363 goto err_dev2;
2364 }
2365 if ((s->dev_midi = register_sound_midi(&solo1_midi_fops, -1)) < 0) {
2366 ret = s->dev_midi;
2367 goto err_dev3;
2368 }
2369 if ((s->dev_dmfm = register_sound_special(&solo1_dmfm_fops, 15 /* ?? */)) < 0) {
2370 ret = s->dev_dmfm;
2371 goto err_dev4;
2372 }
2373 if (setup_solo1(s)) {
2374 ret = -EIO;
2375 goto err;
2376 }
2377 /* register gameport */
2378 gameport_register_port(&s->gameport);
2379 /* store it in the driver field */
2380 pci_set_drvdata(pcidev, s);
2381 return 0;
2382
2383 err:
2384 unregister_sound_dsp(s->dev_dmfm);
2385 err_dev4:
2386 unregister_sound_dsp(s->dev_midi);
2387 err_dev3:
2388 unregister_sound_mixer(s->dev_mixer);
2389 err_dev2:
2390 unregister_sound_dsp(s->dev_audio);
2391 err_dev1:
2392 printk(KERN_ERR "solo1: initialisation error\n");
2393 free_irq(s->irq, s);
2394 err_irq:
2395 if (s->gameport.io)
2396 release_region(s->gameport.io, GAMEPORT_EXTENT);
2397 release_region(s->iobase, IOBASE_EXTENT);
2398 err_region4:
2399 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2400 err_region3:
2401 release_region(s->ddmabase, DDMABASE_EXTENT);
2402 err_region2:
2403 release_region(s->mpubase, MPUBASE_EXTENT);
2404 err_region1:
2405 kfree(s);
2406 return ret;
2407 }
2408
2409 static void __devinit solo1_remove(struct pci_dev *dev)
2410 {
2411 struct solo1_state *s = pci_get_drvdata(dev);
2412
2413 if (!s)
2414 return;
2415 /* stop DMA controller */
2416 outb(0, s->iobase+6);
2417 outb(0, s->ddmabase+0xd); /* DMA master clear */
2418 outb(3, s->sbbase+6); /* reset sequencer and FIFO */
2419 synchronize_irq();
2420 pci_write_config_word(s->dev, 0x60, 0); /* turn off DDMA controller address space */
2421 free_irq(s->irq, s);
2422 if (s->gameport.io) {
2423 gameport_unregister_port(&s->gameport);
2424 release_region(s->gameport.io, GAMEPORT_EXTENT);
2425 }
2426 release_region(s->iobase, IOBASE_EXTENT);
2427 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2428 release_region(s->ddmabase, DDMABASE_EXTENT);
2429 release_region(s->mpubase, MPUBASE_EXTENT);
2430 unregister_sound_dsp(s->dev_audio);
2431 unregister_sound_mixer(s->dev_mixer);
2432 unregister_sound_midi(s->dev_midi);
2433 unregister_sound_special(s->dev_dmfm);
2434 kfree(s);
2435 pci_set_drvdata(dev, NULL);
2436 }
2437
2438 static struct pci_device_id id_table[] __devinitdata = {
2439 { PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_SOLO1, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2440 { 0, }
2441 };
2442
2443 MODULE_DEVICE_TABLE(pci, id_table);
2444
2445 static struct pci_driver solo1_driver = {
2446 name: "ESS Solo1",
2447 id_table: id_table,
2448 probe: solo1_probe,
2449 remove: solo1_remove,
2450 suspend: solo1_suspend,
2451 resume: solo1_resume
2452 };
2453
2454
2455 static int __init init_solo1(void)
2456 {
2457 if (!pci_present()) /* No PCI bus in this machine! */
2458 return -ENODEV;
2459 printk(KERN_INFO "solo1: version v0.19 time " __TIME__ " " __DATE__ "\n");
2460 if (!pci_register_driver(&solo1_driver)) {
2461 pci_unregister_driver(&solo1_driver);
2462 return -ENODEV;
2463 }
2464 return 0;
2465 }
2466
2467 /* --------------------------------------------------------------------- */
2468
2469 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2470 MODULE_DESCRIPTION("ESS Solo1 Driver");
2471
2472 static void __exit cleanup_solo1(void)
2473 {
2474 printk(KERN_INFO "solo1: unloading\n");
2475 pci_unregister_driver(&solo1_driver);
2476 }
2477
2478 /* --------------------------------------------------------------------- */
2479
2480 module_init(init_solo1);
2481 module_exit(cleanup_solo1);
2482
2483