File: /usr/src/linux/drivers/sound/i810_audio.c
1 /*
2 * Intel i810 and friends ICH driver for Linux
3 * Alan Cox <alan@redhat.com>
4 *
5 * Built from:
6 * Low level code: Zach Brown (original nonworking i810 OSS driver)
7 * Jaroslav Kysela <perex@suse.cz> (working ALSA driver)
8 *
9 * Framework: Thomas Sailer <sailer@ife.ee.ethz.ch>
10 * Extended by: Zach Brown <zab@redhat.com>
11 * and others..
12 *
13 * Hardware Provided By:
14 * Analog Devices (A major AC97 codec maker)
15 * Intel Corp (you've probably heard of them already)
16 *
17 * AC97 clues and assistance provided by
18 * Analog Devices
19 * Zach 'Fufu' Brown
20 * Jeff Garzik
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 *
36 *
37 * Intel 810 theory of operation
38 *
39 * The chipset provides three DMA channels that talk to an AC97
40 * CODEC (AC97 is a digital/analog mixer standard). At its simplest
41 * you get 48Khz audio with basic volume and mixer controls. At the
42 * best you get rate adaption in the codec. We set the card up so
43 * that we never take completion interrupts but instead keep the card
44 * chasing its tail around a ring buffer. This is needed for mmap
45 * mode audio and happens to work rather well for non-mmap modes too.
46 *
47 * The board has one output channel for PCM audio (supported) and
48 * a stereo line in and mono microphone input. Again these are normally
49 * locked to 48Khz only. Right now recording is not finished.
50 *
51 * There is no midi support, no synth support. Use timidity. To get
52 * esd working you need to use esd -r 48000 as it won't probe 48KHz
53 * by default. mpg123 can't handle 48Khz only audio so use xmms.
54 *
55 * Fix The Sound On Dell
56 *
57 * Not everyone uses 48KHz. We know of no way to detect this reliably
58 * and certainly not to get the right data. If your i810 audio sounds
59 * stupid you may need to investigate other speeds. According to Analog
60 * they tend to use a 14.318MHz clock which gives you a base rate of
61 * 41194Hz.
62 *
63 * This is available via the 'ftsodell=1' option.
64 *
65 * If you need to force a specific rate set the clocking= option
66 */
67
68 #include <linux/module.h>
69 #include <linux/version.h>
70 #include <linux/string.h>
71 #include <linux/ctype.h>
72 #include <linux/ioport.h>
73 #include <linux/sched.h>
74 #include <linux/delay.h>
75 #include <linux/sound.h>
76 #include <linux/slab.h>
77 #include <linux/soundcard.h>
78 #include <linux/pci.h>
79 #include <asm/io.h>
80 #include <asm/dma.h>
81 #include <linux/init.h>
82 #include <linux/poll.h>
83 #include <linux/spinlock.h>
84 #include <linux/smp_lock.h>
85 #include <linux/ac97_codec.h>
86 #include <linux/wrapper.h>
87 #include <asm/uaccess.h>
88 #include <asm/hardirq.h>
89
90 #ifndef PCI_DEVICE_ID_INTEL_82801
91 #define PCI_DEVICE_ID_INTEL_82801 0x2415
92 #endif
93 #ifndef PCI_DEVICE_ID_INTEL_82901
94 #define PCI_DEVICE_ID_INTEL_82901 0x2425
95 #endif
96 #ifndef PCI_DEVICE_ID_INTEL_ICH2
97 #define PCI_DEVICE_ID_INTEL_ICH2 0x2445
98 #endif
99 #ifndef PCI_DEVICE_ID_INTEL_ICH3
100 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485
101 #endif
102 #ifndef PCI_DEVICE_ID_INTEL_440MX
103 #define PCI_DEVICE_ID_INTEL_440MX 0x7195
104 #endif
105
106 static int ftsodell=0;
107 static int strict_clocking=0;
108 static unsigned int clocking=48000;
109 static int spdif_locked=0;
110
111 //#define DEBUG
112 //#define DEBUG2
113 //#define DEBUG_INTERRUPTS
114
115 #define ADC_RUNNING 1
116 #define DAC_RUNNING 2
117
118 #define I810_FMT_16BIT 1
119 #define I810_FMT_STEREO 2
120 #define I810_FMT_MASK 3
121
122 #define SPDIF_ON 0x0004
123 #define SURR_ON 0x0010
124 #define CENTER_LFE_ON 0x0020
125 #define VOL_MUTED 0x8000
126
127 /* the 810's array of pointers to data buffers */
128
129 struct sg_item {
130 #define BUSADDR_MASK 0xFFFFFFFE
131 u32 busaddr;
132 #define CON_IOC 0x80000000 /* interrupt on completion */
133 #define CON_BUFPAD 0x40000000 /* pad underrun with last sample, else 0 */
134 #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */
135 u32 control;
136 };
137
138 /* an instance of the i810 channel */
139 #define SG_LEN 32
140 struct i810_channel
141 {
142 /* these sg guys should probably be allocated
143 seperately as nocache. Must be 8 byte aligned */
144 struct sg_item sg[SG_LEN]; /* 32*8 */
145 u32 offset; /* 4 */
146 u32 port; /* 4 */
147 u32 used;
148 u32 num;
149 };
150
151 /*
152 * we have 3 seperate dma engines. pcm in, pcm out, and mic.
153 * each dma engine has controlling registers. These goofy
154 * names are from the datasheet, but make it easy to write
155 * code while leafing through it.
156 */
157
158 #define ENUM_ENGINE(PRE,DIG) \
159 enum { \
160 PRE##_BDBAR = 0x##DIG##0, /* Buffer Descriptor list Base Address */ \
161 PRE##_CIV = 0x##DIG##4, /* Current Index Value */ \
162 PRE##_LVI = 0x##DIG##5, /* Last Valid Index */ \
163 PRE##_SR = 0x##DIG##6, /* Status Register */ \
164 PRE##_PICB = 0x##DIG##8, /* Position In Current Buffer */ \
165 PRE##_PIV = 0x##DIG##a, /* Prefetched Index Value */ \
166 PRE##_CR = 0x##DIG##b /* Control Register */ \
167 }
168
169 ENUM_ENGINE(OFF,0); /* Offsets */
170 ENUM_ENGINE(PI,0); /* PCM In */
171 ENUM_ENGINE(PO,1); /* PCM Out */
172 ENUM_ENGINE(MC,2); /* Mic In */
173
174 enum {
175 GLOB_CNT = 0x2c, /* Global Control */
176 GLOB_STA = 0x30, /* Global Status */
177 CAS = 0x34 /* Codec Write Semaphore Register */
178 };
179
180 /* interrupts for a dma engine */
181 #define DMA_INT_FIFO (1<<4) /* fifo under/over flow */
182 #define DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */
183 #define DMA_INT_LVI (1<<2) /* last valid done */
184 #define DMA_INT_CELV (1<<1) /* last valid is current */
185 #define DMA_INT_DCH (1) /* DMA Controller Halted (happens on LVI interrupts) */
186 #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI)
187
188 /* interrupts for the whole chip */
189 #define INT_SEC (1<<11)
190 #define INT_PRI (1<<10)
191 #define INT_MC (1<<7)
192 #define INT_PO (1<<6)
193 #define INT_PI (1<<5)
194 #define INT_MO (1<<2)
195 #define INT_NI (1<<1)
196 #define INT_GPI (1<<0)
197 #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI)
198
199
200 #define DRIVER_VERSION "0.04"
201
202 /* magic numbers to protect our data structures */
203 #define I810_CARD_MAGIC 0x5072696E /* "Prin" */
204 #define I810_STATE_MAGIC 0x63657373 /* "cess" */
205 #define I810_DMA_MASK 0xffffffff /* DMA buffer mask for pci_alloc_consist */
206 #define NR_HW_CH 3
207
208 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
209 #define NR_AC97 2
210
211 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */
212 /* stream at a minimum for this card to be happy */
213 static const unsigned sample_size[] = { 1, 2, 2, 4 };
214 /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */
215 /* values are one less than might be expected */
216 static const unsigned sample_shift[] = { -1, 0, 0, 1 };
217
218 enum {
219 ICH82801AA = 0,
220 ICH82901AB,
221 INTEL440MX,
222 INTELICH2,
223 INTELICH3
224 };
225
226 static char * card_names[] = {
227 "Intel ICH 82801AA",
228 "Intel ICH 82901AB",
229 "Intel 440MX",
230 "Intel ICH2",
231 "Intel ICH3"
232 };
233
234 static struct pci_device_id i810_pci_tbl [] __initdata = {
235 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA},
237 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82901,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB},
239 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX},
241 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2},
243 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH3,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3},
245 {0,}
246 };
247
248 MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
249
250 /* "software" or virtual channel, an instance of opened /dev/dsp */
251 struct i810_state {
252 unsigned int magic;
253 struct i810_card *card; /* Card info */
254
255 /* single open lock mechanism, only used for recording */
256 struct semaphore open_sem;
257 wait_queue_head_t open_wait;
258
259 /* file mode */
260 mode_t open_mode;
261
262 /* virtual channel number */
263 int virt;
264
265 struct dmabuf {
266 /* wave sample stuff */
267 unsigned int rate;
268 unsigned char fmt, enable, trigger;
269
270 /* hardware channel */
271 struct i810_channel *read_channel;
272 struct i810_channel *write_channel;
273
274 /* OSS buffer management stuff */
275 void *rawbuf;
276 dma_addr_t dma_handle;
277 unsigned buforder;
278 unsigned numfrag;
279 unsigned fragshift;
280
281 /* our buffer acts like a circular ring */
282 unsigned hwptr; /* where dma last started, updated by update_ptr */
283 unsigned swptr; /* where driver last clear/filled, updated by read/write */
284 int count; /* bytes to be consumed or been generated by dma machine */
285 unsigned total_bytes; /* total bytes dmaed by hardware */
286
287 unsigned error; /* number of over/underruns */
288 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */
289
290 /* redundant, but makes calculations easier */
291 /* what the hardware uses */
292 unsigned dmasize;
293 unsigned fragsize;
294 unsigned fragsamples;
295
296 /* what we tell the user to expect */
297 unsigned userfrags;
298 unsigned userfragsize;
299
300 /* OSS stuff */
301 unsigned mapped:1;
302 unsigned ready:1;
303 unsigned update_flag;
304 unsigned ossfragsize;
305 unsigned ossmaxfrags;
306 unsigned subdivision;
307 } dmabuf;
308 };
309
310
311 struct i810_card {
312 struct i810_channel channel[3];
313 unsigned int magic;
314
315 /* We keep i810 cards in a linked list */
316 struct i810_card *next;
317
318 /* The i810 has a certain amount of cross channel interaction
319 so we use a single per card lock */
320 spinlock_t lock;
321
322 /* PCI device stuff */
323 struct pci_dev * pci_dev;
324 u16 pci_id;
325
326 /* soundcore stuff */
327 int dev_audio;
328
329 /* structures for abstraction of hardware facilities, codecs, banks and channels*/
330 struct ac97_codec *ac97_codec[NR_AC97];
331 struct i810_state *states[NR_HW_CH];
332
333 u16 ac97_features;
334 u16 ac97_status;
335 u16 channels;
336
337 /* hardware resources */
338 unsigned long iobase;
339 unsigned long ac97base;
340 u32 irq;
341
342 /* Function support */
343 struct i810_channel *(*alloc_pcm_channel)(struct i810_card *);
344 struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *);
345 struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *);
346 void (*free_pcm_channel)(struct i810_card *, int chan);
347 };
348
349 static struct i810_card *devs = NULL;
350
351 static int i810_open_mixdev(struct inode *inode, struct file *file);
352 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
353 unsigned long arg);
354
355 static inline unsigned ld2(unsigned int x)
356 {
357 unsigned r = 0;
358
359 if (x >= 0x10000) {
360 x >>= 16;
361 r += 16;
362 }
363 if (x >= 0x100) {
364 x >>= 8;
365 r += 8;
366 }
367 if (x >= 0x10) {
368 x >>= 4;
369 r += 4;
370 }
371 if (x >= 4) {
372 x >>= 2;
373 r += 2;
374 }
375 if (x >= 2)
376 r++;
377 return r;
378 }
379
380 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg);
381 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data);
382
383 static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card)
384 {
385 if(card->channel[1].used==1)
386 return NULL;
387 card->channel[1].used=1;
388 return &card->channel[1];
389 }
390
391 static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card)
392 {
393 if(card->channel[0].used==1)
394 return NULL;
395 card->channel[0].used=1;
396 return &card->channel[0];
397 }
398
399 static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card)
400 {
401 if(card->channel[2].used==1)
402 return NULL;
403 card->channel[2].used=1;
404 return &card->channel[2];
405 }
406
407 static void i810_free_pcm_channel(struct i810_card *card, int channel)
408 {
409 card->channel[channel].used=0;
410 }
411
412 static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate )
413 {
414 unsigned long id = 0L;
415
416 id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16);
417 id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff;
418 #ifdef DEBUG
419 printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id);
420 #endif
421 switch ( id ) {
422 case 0x41445361: /* AD1886 */
423 if (rate == 48000) {
424 return 1;
425 }
426 break;
427 default: /* all other codecs, until we know otherwiae */
428 if (rate == 48000 || rate == 44100 || rate == 32000) {
429 return 1;
430 }
431 break;
432 }
433 return (0);
434 }
435
436 /* i810_set_spdif_output
437 *
438 * Configure the S/PDIF output transmitter. When we turn on
439 * S/PDIF, we turn off the analog output. This may not be
440 * the right thing to do.
441 *
442 * Assumptions:
443 * The DSP sample rate must already be set to a supported
444 * S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort.
445 */
446 static void i810_set_spdif_output(struct i810_state *state, int slots, int rate)
447 {
448 int vol;
449 int aud_reg;
450 struct ac97_codec *codec = state->card->ac97_codec[0];
451
452 if(!(state->card->ac97_features & 4)) {
453 #ifdef DEBUG
454 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
455 #endif
456 state->card->ac97_status &= ~SPDIF_ON;
457 } else {
458 if ( slots == -1 ) { /* Turn off S/PDIF */
459 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
460 i810_ac97_set(codec, AC97_EXTENDED_STATUS, (aud_reg & ~AC97_EA_SPDIF));
461
462 /* If the volume wasn't muted before we turned on S/PDIF, unmute it */
463 if ( !(state->card->ac97_status & VOL_MUTED) ) {
464 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
465 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED));
466 }
467 state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON);
468 return;
469 }
470
471 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
472 state->card->ac97_status = vol & VOL_MUTED;
473
474 /* Set S/PDIF transmitter sample rate */
475 aud_reg = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
476 switch ( rate ) {
477 case 32000:
478 aud_reg = (aud_reg & AC97_SC_SPSR_MASK) | AC97_SC_SPSR_32K;
479 break;
480 case 44100:
481 aud_reg = (aud_reg & AC97_SC_SPSR_MASK) | AC97_SC_SPSR_44K;
482 break;
483 case 48000:
484 aud_reg = (aud_reg & AC97_SC_SPSR_MASK) | AC97_SC_SPSR_48K;
485 break;
486 default:
487 #ifdef DEBUG
488 printk(KERN_WARNING "i810_audio: %d sample rate not supported by S/PDIF.\n", rate);
489 #endif
490 /* turn off S/PDIF */
491 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
492 i810_ac97_set(codec, AC97_EXTENDED_STATUS, (aud_reg & ~AC97_EA_SPDIF));
493 state->card->ac97_status &= ~SPDIF_ON;
494 return;
495 }
496
497 i810_ac97_set(codec, AC97_SPDIF_CONTROL, aud_reg);
498
499 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
500 aud_reg = (aud_reg & AC97_EA_SLOT_MASK) | slots | AC97_EA_VRA | AC97_EA_SPDIF;
501 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
502 state->card->ac97_status |= SPDIF_ON;
503
504 /* Check to make sure the configuration is valid */
505 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
506 if ( ! (aud_reg & 0x0400) ) {
507 #ifdef DEBUG
508 printk(KERN_WARNING "i810_audio: S/PDIF transmitter configuration not valid (0x%04x).\n", aud_reg);
509 #endif
510
511 /* turn off S/PDIF */
512 i810_ac97_set(codec, AC97_EXTENDED_STATUS, (aud_reg & ~AC97_EA_SPDIF));
513 state->card->ac97_status &= ~SPDIF_ON;
514 return;
515 }
516 /* Mute the analog output */
517 /* Should this only mute the PCM volume??? */
518 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED));
519 }
520 }
521
522 /* i810_set_dac_channels
523 *
524 * Configure the codec's multi-channel DACs
525 *
526 * The logic is backwards. Setting the bit to 1 turns off the DAC.
527 *
528 * What about the ICH? We currently configure it using the
529 * SNDCTL_DSP_CHANNELS ioctl. If we're turnning on the DAC,
530 * does that imply that we want the ICH set to support
531 * these channels?
532 *
533 * TODO:
534 * vailidate that the codec really supports these DACs
535 * before turning them on.
536 */
537 static void i810_set_dac_channels(struct i810_state *state, int channel)
538 {
539 int aud_reg;
540 struct ac97_codec *codec = state->card->ac97_codec[0];
541
542 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
543 aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK;
544 state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON);
545
546 switch ( channel ) {
547 case 2: /* always enabled */
548 break;
549 case 4:
550 aud_reg &= ~AC97_EA_PRJ;
551 state->card->ac97_status |= SURR_ON;
552 break;
553 case 6:
554 aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK);
555 state->card->ac97_status |= SURR_ON | CENTER_LFE_ON;
556 break;
557 default:
558 break;
559 }
560 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
561
562 }
563
564
565 /* set playback sample rate */
566 static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate)
567 {
568 struct dmabuf *dmabuf = &state->dmabuf;
569 u32 new_rate;
570 struct ac97_codec *codec=state->card->ac97_codec[0];
571
572 if(!(state->card->ac97_features&0x0001))
573 {
574 dmabuf->rate = clocking;
575 return clocking;
576 }
577
578 if (rate > 48000)
579 rate = 48000;
580 if (rate < 8000)
581 rate = 8000;
582 dmabuf->rate = rate;
583
584 /*
585 * Adjust for misclocked crap
586 */
587 rate = ( rate * clocking)/48000;
588 if(strict_clocking && rate < 8000) {
589 rate = 8000;
590 dmabuf->rate = (rate * 48000)/clocking;
591 }
592
593 new_rate = ac97_set_dac_rate(codec, rate);
594
595 if(new_rate != rate) {
596 dmabuf->rate = (new_rate * 48000)/clocking;
597 rate = new_rate;
598 }
599 #ifdef DEBUG
600 printk("i810_audio: called i810_set_dac_rate : rate = %d/%d\n", dmabuf->rate, rate);
601 #endif
602 return dmabuf->rate;
603 }
604
605 /* set recording sample rate */
606 static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate)
607 {
608 struct dmabuf *dmabuf = &state->dmabuf;
609 u32 new_rate;
610 struct ac97_codec *codec=state->card->ac97_codec[0];
611
612 if(!(state->card->ac97_features&0x0001))
613 {
614 dmabuf->rate = clocking;
615 return clocking;
616 }
617
618 if (rate > 48000)
619 rate = 48000;
620 if (rate < 8000)
621 rate = 8000;
622 dmabuf->rate = rate;
623
624 /*
625 * Adjust for misclocked crap
626 */
627
628 rate = ( rate * clocking)/48000;
629 if(strict_clocking && rate < 8000) {
630 rate = 8000;
631 dmabuf->rate = (rate * 48000)/clocking;
632 }
633
634 new_rate = ac97_set_adc_rate(codec, rate);
635
636 if(new_rate != rate) {
637 dmabuf->rate = (new_rate * 48000)/clocking;
638 rate = new_rate;
639 }
640 #ifdef DEBUG
641 printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate);
642 #endif
643 return dmabuf->rate;
644 }
645
646 /* get current playback/recording dma buffer pointer (byte offset from LBA),
647 called with spinlock held! */
648
649 static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec)
650 {
651 struct dmabuf *dmabuf = &state->dmabuf;
652 unsigned int civ, offset;
653 struct i810_channel *c;
654
655 if (!dmabuf->enable)
656 return 0;
657 if (rec)
658 c = dmabuf->read_channel;
659 else
660 c = dmabuf->write_channel;
661 do {
662 civ = inb(state->card->iobase+c->port+OFF_CIV);
663 offset = (civ + 1) * dmabuf->fragsize -
664 2 * inw(state->card->iobase+c->port+OFF_PICB);
665 /* CIV changed before we read PICB (very seldom) ?
666 * then PICB was rubbish, so try again */
667 } while (civ != inb(state->card->iobase+c->port+OFF_CIV));
668
669 return offset;
670 }
671
672 //static void resync_dma_ptrs(struct i810_state *state, int rec)
673 //{
674 // struct dmabuf *dmabuf = &state->dmabuf;
675 // struct i810_channel *c;
676 // int offset;
677 //
678 // if(rec) {
679 // c = dmabuf->read_channel;
680 // } else {
681 // c = dmabuf->write_channel;
682 // }
683 // if(c==NULL)
684 // return;
685 // offset = inb(state->card->iobase+c->port+OFF_CIV);
686 // if(offset == inb(state->card->iobase+c->port+OFF_LVI))
687 // offset++;
688 // offset *= dmabuf->fragsize;
689 //
690 // dmabuf->hwptr=dmabuf->swptr = offset;
691 //}
692
693 /* Stop recording (lock held) */
694 static inline void __stop_adc(struct i810_state *state)
695 {
696 struct dmabuf *dmabuf = &state->dmabuf;
697 struct i810_card *card = state->card;
698
699 dmabuf->enable &= ~ADC_RUNNING;
700 outb(0, card->iobase + PI_CR);
701 // wait for the card to acknowledge shutdown
702 while( inb(card->iobase + PI_CR) != 0 ) ;
703 // now clear any latent interrupt bits (like the halt bit)
704 outb( inb(card->iobase + PI_SR), card->iobase + PI_SR );
705 outl( inl(card->iobase + GLOB_STA) & INT_PI, card->iobase + GLOB_STA);
706 }
707
708 static void stop_adc(struct i810_state *state)
709 {
710 struct i810_card *card = state->card;
711 unsigned long flags;
712
713 spin_lock_irqsave(&card->lock, flags);
714 __stop_adc(state);
715 spin_unlock_irqrestore(&card->lock, flags);
716 }
717
718 static void start_adc(struct i810_state *state)
719 {
720 struct dmabuf *dmabuf = &state->dmabuf;
721 struct i810_card *card = state->card;
722 unsigned long flags;
723
724 if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable &&
725 (dmabuf->trigger & PCM_ENABLE_INPUT)) {
726 spin_lock_irqsave(&card->lock, flags);
727 dmabuf->enable |= ADC_RUNNING;
728 outb((1<<4) | (1<<2) | 1, card->iobase + PI_CR);
729 spin_unlock_irqrestore(&card->lock, flags);
730 }
731 }
732
733 /* stop playback (lock held) */
734 static inline void __stop_dac(struct i810_state *state)
735 {
736 struct dmabuf *dmabuf = &state->dmabuf;
737 struct i810_card *card = state->card;
738
739 dmabuf->enable &= ~DAC_RUNNING;
740 outb(0, card->iobase + PO_CR);
741 // wait for the card to acknowledge shutdown
742 while( inb(card->iobase + PO_CR) != 0 ) ;
743 // now clear any latent interrupt bits (like the halt bit)
744 outb( inb(card->iobase + PO_SR), card->iobase + PO_SR );
745 outl( inl(card->iobase + GLOB_STA) & INT_PO, card->iobase + GLOB_STA);
746 }
747
748 static void stop_dac(struct i810_state *state)
749 {
750 struct i810_card *card = state->card;
751 unsigned long flags;
752
753 spin_lock_irqsave(&card->lock, flags);
754 __stop_dac(state);
755 spin_unlock_irqrestore(&card->lock, flags);
756 }
757
758 static void start_dac(struct i810_state *state)
759 {
760 struct dmabuf *dmabuf = &state->dmabuf;
761 struct i810_card *card = state->card;
762 unsigned long flags;
763
764 if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable &&
765 (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
766 spin_lock_irqsave(&card->lock, flags);
767 dmabuf->enable |= DAC_RUNNING;
768 outb((1<<4) | (1<<2) | 1, card->iobase + PO_CR);
769 spin_unlock_irqrestore(&card->lock, flags);
770 }
771 }
772
773 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
774 #define DMABUF_MINORDER 1
775
776 /* allocate DMA buffer, playback and recording buffer should be allocated seperately */
777 static int alloc_dmabuf(struct i810_state *state)
778 {
779 struct dmabuf *dmabuf = &state->dmabuf;
780 void *rawbuf= NULL;
781 int order, size;
782 struct page *page, *pend;
783
784 /* If we don't have any oss frag params, then use our default ones */
785 if(dmabuf->ossmaxfrags == 0)
786 dmabuf->ossmaxfrags = 4;
787 if(dmabuf->ossfragsize == 0)
788 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags;
789 size = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
790
791 /* alloc enough to satisfy the oss params */
792 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) {
793 if ( (PAGE_SIZE<<order) > size )
794 continue;
795 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev,
796 PAGE_SIZE << order,
797 &dmabuf->dma_handle)))
798 break;
799 }
800 if (!rawbuf)
801 return -ENOMEM;
802
803
804 #ifdef DEBUG
805 printk("i810_audio: allocated %ld (order = %d) bytes at %p\n",
806 PAGE_SIZE << order, order, rawbuf);
807 #endif
808
809 dmabuf->ready = dmabuf->mapped = 0;
810 dmabuf->rawbuf = rawbuf;
811 dmabuf->buforder = order;
812
813 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
814 pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
815 for (page = virt_to_page(rawbuf); page <= pend; page++)
816 mem_map_reserve(page);
817
818 return 0;
819 }
820
821 /* free DMA buffer */
822 static void dealloc_dmabuf(struct i810_state *state)
823 {
824 struct dmabuf *dmabuf = &state->dmabuf;
825 struct page *page, *pend;
826
827 if (dmabuf->rawbuf) {
828 /* undo marking the pages as reserved */
829 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1);
830 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++)
831 mem_map_unreserve(page);
832 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder,
833 dmabuf->rawbuf, dmabuf->dma_handle);
834 }
835 dmabuf->rawbuf = NULL;
836 dmabuf->mapped = dmabuf->ready = 0;
837 }
838
839 static int prog_dmabuf(struct i810_state *state, unsigned rec)
840 {
841 struct dmabuf *dmabuf = &state->dmabuf;
842 struct i810_channel *c;
843 struct sg_item *sg;
844 unsigned long flags;
845 int ret;
846 unsigned fragint;
847 int i;
848
849 spin_lock_irqsave(&state->card->lock, flags);
850 if(dmabuf->enable & DAC_RUNNING)
851 __stop_dac(state);
852 if(dmabuf->enable & ADC_RUNNING)
853 __stop_adc(state);
854 dmabuf->total_bytes = 0;
855 dmabuf->count = dmabuf->error = 0;
856 dmabuf->swptr = dmabuf->hwptr = 0;
857 spin_unlock_irqrestore(&state->card->lock, flags);
858
859 /* allocate DMA buffer if not allocated yet */
860 if (dmabuf->rawbuf)
861 dealloc_dmabuf(state);
862 if ((ret = alloc_dmabuf(state)))
863 return ret;
864
865 /* FIXME: figure out all this OSS fragment stuff */
866 /* I did, it now does what it should according to the OSS API. DL */
867 dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder;
868 dmabuf->numfrag = SG_LEN;
869 dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag;
870 dmabuf->fragsamples = dmabuf->fragsize >> 1;
871 dmabuf->userfragsize = dmabuf->ossfragsize;
872 dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize;
873
874 memset(dmabuf->rawbuf, 0, dmabuf->dmasize);
875
876 if(dmabuf->ossmaxfrags == 4) {
877 fragint = 8;
878 dmabuf->fragshift = 2;
879 } else if (dmabuf->ossmaxfrags == 8) {
880 fragint = 4;
881 dmabuf->fragshift = 3;
882 } else if (dmabuf->ossmaxfrags == 16) {
883 fragint = 2;
884 dmabuf->fragshift = 4;
885 } else {
886 fragint = 1;
887 dmabuf->fragshift = 5;
888 }
889 /*
890 * Now set up the ring
891 */
892 if(dmabuf->read_channel)
893 c = dmabuf->read_channel;
894 else
895 c = dmabuf->write_channel;
896 while(c != NULL) {
897 sg=&c->sg[0];
898 /*
899 * Load up 32 sg entries and take an interrupt at half
900 * way (we might want more interrupts later..)
901 */
902
903 for(i=0;i<dmabuf->numfrag;i++)
904 {
905 sg->busaddr=virt_to_bus(dmabuf->rawbuf+dmabuf->fragsize*i);
906 // the card will always be doing 16bit stereo
907 sg->control=dmabuf->fragsamples;
908 sg->control|=CON_BUFPAD;
909 // set us up to get IOC interrupts as often as needed to
910 // satisfy numfrag requirements, no more
911 if( ((i+1) % fragint) == 0) {
912 sg->control|=CON_IOC;
913 }
914 sg++;
915 }
916 spin_lock_irqsave(&state->card->lock, flags);
917 outb(2, state->card->iobase+c->port+OFF_CR); /* reset DMA machine */
918 outl(virt_to_bus(&c->sg[0]), state->card->iobase+c->port+OFF_BDBAR);
919 outb(0, state->card->iobase+c->port+OFF_CIV);
920 outb(0, state->card->iobase+c->port+OFF_LVI);
921 dmabuf->count = 0;
922
923 spin_unlock_irqrestore(&state->card->lock, flags);
924
925 if(c != dmabuf->write_channel)
926 c = dmabuf->write_channel;
927 else
928 c = NULL;
929 }
930
931 /* set the ready flag for the dma buffer */
932 dmabuf->ready = 1;
933
934 #ifdef DEBUG
935 printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, "
936 "fragsize = %d dmasize = %d\n",
937 dmabuf->rate, dmabuf->fmt, dmabuf->numfrag,
938 dmabuf->fragsize, dmabuf->dmasize);
939 #endif
940
941 return 0;
942 }
943
944 static void __i810_update_lvi(struct i810_state *state, int rec)
945 {
946 struct dmabuf *dmabuf = &state->dmabuf;
947 int x, port;
948
949 port = state->card->iobase;
950 if(rec)
951 port += dmabuf->read_channel->port;
952 else
953 port += dmabuf->write_channel->port;
954
955 if(dmabuf->mapped) {
956 if(rec)
957 dmabuf->swptr = (dmabuf->hwptr + dmabuf->dmasize
958 - dmabuf->count) % dmabuf->dmasize;
959 else
960 dmabuf->swptr = (dmabuf->hwptr + dmabuf->count)
961 % dmabuf->dmasize;
962 }
963 /*
964 * two special cases, count == 0 on write
965 * means no data, and count == dmasize
966 * means no data on read, handle appropriately
967 */
968 if(!rec && dmabuf->count == 0) {
969 outb(inb(port+OFF_CIV),port+OFF_LVI);
970 return;
971 }
972 if(rec && dmabuf->count == dmabuf->dmasize) {
973 outb(inb(port+OFF_CIV),port+OFF_LVI);
974 return;
975 }
976 /* swptr - 1 is the tail of our transfer */
977 x = (dmabuf->dmasize + dmabuf->swptr - 1) % dmabuf->dmasize;
978 x /= dmabuf->fragsize;
979 outb(x&31, port+OFF_LVI);
980 }
981
982 static void i810_update_lvi(struct i810_state *state, int rec)
983 {
984 struct dmabuf *dmabuf = &state->dmabuf;
985 unsigned long flags;
986
987 if(!dmabuf->ready)
988 return;
989 spin_lock_irqsave(&state->card->lock, flags);
990 __i810_update_lvi(state, rec);
991 spin_unlock_irqrestore(&state->card->lock, flags);
992 }
993
994 /* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */
995 static void i810_update_ptr(struct i810_state *state)
996 {
997 struct dmabuf *dmabuf = &state->dmabuf;
998 unsigned hwptr;
999 int diff;
1000
1001 /* error handling and process wake up for DAC */
1002 if (dmabuf->enable == ADC_RUNNING) {
1003 /* update hardware pointer */
1004 hwptr = i810_get_dma_addr(state, 1);
1005 diff = (dmabuf->dmasize + hwptr - dmabuf->hwptr) % dmabuf->dmasize;
1006 // printk("HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1007 dmabuf->hwptr = hwptr;
1008 dmabuf->total_bytes += diff;
1009 dmabuf->count += diff;
1010 if (dmabuf->count > dmabuf->dmasize) {
1011 /* buffer underrun or buffer overrun */
1012 /* this is normal for the end of a read */
1013 /* only give an error if we went past the */
1014 /* last valid sg entry */
1015 if(inb(state->card->iobase + PI_CIV) !=
1016 inb(state->card->iobase + PI_LVI)) {
1017 printk(KERN_WARNING "i810_audio: DMA overrun on read\n");
1018 dmabuf->error++;
1019 }
1020 }
1021 if (dmabuf->count > dmabuf->userfragsize)
1022 wake_up(&dmabuf->wait);
1023 }
1024 /* error handling and process wake up for DAC */
1025 if (dmabuf->enable == DAC_RUNNING) {
1026 /* update hardware pointer */
1027 hwptr = i810_get_dma_addr(state, 0);
1028 diff = (dmabuf->dmasize + hwptr - dmabuf->hwptr) % dmabuf->dmasize;
1029 // printk("HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1030 dmabuf->hwptr = hwptr;
1031 dmabuf->total_bytes += diff;
1032 dmabuf->count -= diff;
1033 if (dmabuf->count < 0) {
1034 /* buffer underrun or buffer overrun */
1035 /* this is normal for the end of a write */
1036 /* only give an error if we went past the */
1037 /* last valid sg entry */
1038 if(inb(state->card->iobase + PO_CIV) !=
1039 inb(state->card->iobase + PO_LVI)) {
1040 printk(KERN_WARNING "i810_audio: DMA overrun on write\n");
1041 printk("i810_audio: CIV %d, LVI %d, hwptr %x, "
1042 "count %d\n",
1043 inb(state->card->iobase + PO_CIV),
1044 inb(state->card->iobase + PO_LVI),
1045 dmabuf->hwptr, dmabuf->count);
1046 dmabuf->error++;
1047 }
1048 }
1049 if (dmabuf->count < (dmabuf->dmasize-dmabuf->userfragsize))
1050 wake_up(&dmabuf->wait);
1051 }
1052 }
1053
1054 static int drain_dac(struct i810_state *state, int nonblock)
1055 {
1056 DECLARE_WAITQUEUE(wait, current);
1057 struct dmabuf *dmabuf = &state->dmabuf;
1058 unsigned long flags;
1059 unsigned long tmo;
1060 int count;
1061
1062 if (!dmabuf->ready)
1063 return 0;
1064
1065 add_wait_queue(&dmabuf->wait, &wait);
1066 for (;;) {
1067 /* It seems that we have to set the current state to TASK_INTERRUPTIBLE
1068 every time to make the process really go to sleep */
1069 current->state = TASK_INTERRUPTIBLE;
1070
1071 spin_lock_irqsave(&state->card->lock, flags);
1072 i810_update_ptr(state);
1073 count = dmabuf->count;
1074 spin_unlock_irqrestore(&state->card->lock, flags);
1075
1076 if (count <= 0)
1077 break;
1078
1079 if (signal_pending(current))
1080 break;
1081
1082 i810_update_lvi(state,0);
1083 if (dmabuf->enable != DAC_RUNNING)
1084 start_dac(state);
1085
1086 if (nonblock) {
1087 remove_wait_queue(&dmabuf->wait, &wait);
1088 current->state = TASK_RUNNING;
1089 return -EBUSY;
1090 }
1091
1092 tmo = (dmabuf->dmasize * HZ) / dmabuf->rate;
1093 tmo >>= 1;
1094 if (!schedule_timeout(tmo ? tmo : 1) && tmo){
1095 printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n");
1096 break;
1097 }
1098 }
1099 stop_dac(state);
1100 synchronize_irq();
1101 remove_wait_queue(&dmabuf->wait, &wait);
1102 current->state = TASK_RUNNING;
1103 if (signal_pending(current))
1104 return -ERESTARTSYS;
1105
1106 return 0;
1107 }
1108
1109 static void i810_channel_interrupt(struct i810_card *card)
1110 {
1111 int i, count;
1112
1113 #ifdef DEBUG_INTERRUPTS
1114 printk("CHANNEL ");
1115 #endif
1116 for(i=0;i<NR_HW_CH;i++)
1117 {
1118 struct i810_state *state = card->states[i];
1119 struct i810_channel *c;
1120 struct dmabuf *dmabuf;
1121 unsigned long port = card->iobase;
1122 u16 status;
1123
1124 if(!state)
1125 continue;
1126 if(!state->dmabuf.ready)
1127 continue;
1128 dmabuf = &state->dmabuf;
1129 if(dmabuf->enable & DAC_RUNNING)
1130 c=dmabuf->write_channel;
1131 else if(dmabuf->enable & ADC_RUNNING)
1132 c=dmabuf->read_channel;
1133 else /* This can occur going from R/W to close */
1134 continue;
1135
1136 port+=c->port;
1137
1138 status = inw(port + OFF_SR);
1139 #ifdef DEBUG_INTERRUPTS
1140 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status);
1141 #endif
1142 if(status & DMA_INT_COMPLETE)
1143 {
1144 i810_update_ptr(state);
1145 #ifdef DEBUG_INTERRUPTS
1146 printk("COMP %d ", dmabuf->hwptr /
1147 dmabuf->fragsize);
1148 #endif
1149 }
1150 if(status & DMA_INT_LVI)
1151 {
1152 i810_update_ptr(state);
1153 wake_up(&dmabuf->wait);
1154 #ifdef DEBUG_INTERRUPTS
1155 printk("LVI ");
1156 #endif
1157 }
1158 if(status & DMA_INT_DCH)
1159 {
1160 i810_update_ptr(state);
1161 if(dmabuf->enable & DAC_RUNNING)
1162 count = dmabuf->count;
1163 else
1164 count = dmabuf->dmasize - dmabuf->count;
1165 if(count > 0) {
1166 outb(inb(port+OFF_CR) | 1, port+OFF_CR);
1167 } else {
1168 wake_up(&dmabuf->wait);
1169 #ifdef DEBUG_INTERRUPTS
1170 printk("DCH - STOP ");
1171 #endif
1172 }
1173 }
1174 outw(status & DMA_INT_MASK, port + OFF_SR);
1175 }
1176 #ifdef DEBUG_INTERRUPTS
1177 printk(")\n");
1178 #endif
1179 }
1180
1181 static void i810_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1182 {
1183 struct i810_card *card = (struct i810_card *)dev_id;
1184 u32 status;
1185
1186 spin_lock(&card->lock);
1187
1188 status = inl(card->iobase + GLOB_STA);
1189
1190 if(!(status & INT_MASK))
1191 {
1192 spin_unlock(&card->lock);
1193 return; /* not for us */
1194 }
1195
1196 if(status & (INT_PO|INT_PI|INT_MC))
1197 i810_channel_interrupt(card);
1198
1199 /* clear 'em */
1200 outl(status & INT_MASK, card->iobase + GLOB_STA);
1201 spin_unlock(&card->lock);
1202 }
1203
1204 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be copied to
1205 the user's buffer. it is filled by the dma machine and drained by this loop. */
1206 static ssize_t i810_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1207 {
1208 struct i810_state *state = (struct i810_state *)file->private_data;
1209 struct dmabuf *dmabuf = &state->dmabuf;
1210 ssize_t ret;
1211 unsigned long flags;
1212 unsigned int swptr;
1213 int cnt;
1214
1215 #ifdef DEBUG2
1216 printk("i810_audio: i810_read called, count = %d\n", count);
1217 #endif
1218
1219 if (ppos != &file->f_pos)
1220 return -ESPIPE;
1221 if (dmabuf->mapped)
1222 return -ENXIO;
1223 if (dmabuf->enable & DAC_RUNNING)
1224 return -ENODEV;
1225 if (!dmabuf->read_channel) {
1226 dmabuf->ready = 0;
1227 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
1228 if (!dmabuf->read_channel) {
1229 return -EBUSY;
1230 }
1231 }
1232 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1233 return ret;
1234 if (!access_ok(VERIFY_WRITE, buffer, count))
1235 return -EFAULT;
1236 dmabuf->trigger &= ~PCM_ENABLE_OUTPUT;
1237 ret = 0;
1238
1239 while (count > 0) {
1240 spin_lock_irqsave(&state->card->lock, flags);
1241 swptr = dmabuf->swptr;
1242 if (dmabuf->count > dmabuf->dmasize) {
1243 dmabuf->count = dmabuf->dmasize;
1244 }
1245 cnt = dmabuf->count - dmabuf->fragsize;
1246 // this is to make the copy_to_user simpler below
1247 if(cnt > (dmabuf->dmasize - swptr))
1248 cnt = dmabuf->dmasize - swptr;
1249 spin_unlock_irqrestore(&state->card->lock, flags);
1250
1251 if (cnt > count)
1252 cnt = count;
1253 if (cnt <= 0) {
1254 unsigned long tmo;
1255 if(!dmabuf->enable) {
1256 dmabuf->trigger |= PCM_ENABLE_INPUT;
1257 start_adc(state);
1258 }
1259 i810_update_lvi(state,1);
1260 if (file->f_flags & O_NONBLOCK) {
1261 if (!ret) ret = -EAGAIN;
1262 return ret;
1263 }
1264 /* This isnt strictly right for the 810 but it'll do */
1265 tmo = (dmabuf->dmasize * HZ) / (dmabuf->rate * 2);
1266 tmo >>= 1;
1267 /* There are two situations when sleep_on_timeout returns, one is when
1268 the interrupt is serviced correctly and the process is waked up by
1269 ISR ON TIME. Another is when timeout is expired, which means that
1270 either interrupt is NOT serviced correctly (pending interrupt) or it
1271 is TOO LATE for the process to be scheduled to run (scheduler latency)
1272 which results in a (potential) buffer overrun. And worse, there is
1273 NOTHING we can do to prevent it. */
1274 if (!interruptible_sleep_on_timeout(&dmabuf->wait, tmo)) {
1275 #ifdef DEBUG
1276 printk(KERN_ERR "i810_audio: recording schedule timeout, "
1277 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1278 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1279 dmabuf->hwptr, dmabuf->swptr);
1280 #endif
1281 /* a buffer overrun, we delay the recovery until next time the
1282 while loop begin and we REALLY have space to record */
1283 }
1284 if (signal_pending(current)) {
1285 ret = ret ? ret : -ERESTARTSYS;
1286 return ret;
1287 }
1288 continue;
1289 }
1290
1291 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
1292 if (!ret) ret = -EFAULT;
1293 return ret;
1294 }
1295
1296 swptr = (swptr + cnt) % dmabuf->dmasize;
1297
1298 spin_lock_irqsave(&state->card->lock, flags);
1299 dmabuf->swptr = swptr;
1300 dmabuf->count -= cnt;
1301 spin_unlock_irqrestore(&state->card->lock, flags);
1302
1303 count -= cnt;
1304 buffer += cnt;
1305 ret += cnt;
1306 }
1307 i810_update_lvi(state,1);
1308 if(!(dmabuf->enable & ADC_RUNNING))
1309 start_adc(state);
1310 return ret;
1311 }
1312
1313 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to
1314 the soundcard. it is drained by the dma machine and filled by this loop. */
1315 static ssize_t i810_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1316 {
1317 struct i810_state *state = (struct i810_state *)file->private_data;
1318 struct dmabuf *dmabuf = &state->dmabuf;
1319 ssize_t ret;
1320 unsigned long flags;
1321 unsigned int swptr = 0;
1322 int cnt, x;
1323
1324 #ifdef DEBUG2
1325 printk("i810_audio: i810_write called, count = %d\n", count);
1326 #endif
1327
1328 if (ppos != &file->f_pos)
1329 return -ESPIPE;
1330 if (dmabuf->mapped)
1331 return -ENXIO;
1332 if (dmabuf->enable & ADC_RUNNING)
1333 return -ENODEV;
1334 if (!dmabuf->write_channel) {
1335 dmabuf->ready = 0;
1336 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
1337 if(!dmabuf->write_channel)
1338 return -EBUSY;
1339 }
1340 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1341 return ret;
1342 if (!access_ok(VERIFY_READ, buffer, count))
1343 return -EFAULT;
1344 dmabuf->trigger &= ~PCM_ENABLE_INPUT;
1345 ret = 0;
1346
1347 while (count > 0) {
1348 spin_lock_irqsave(&state->card->lock, flags);
1349 swptr = dmabuf->swptr;
1350 if (dmabuf->count < 0) {
1351 dmabuf->count = 0;
1352 }
1353 cnt = dmabuf->dmasize - dmabuf->fragsize - dmabuf->count;
1354 // this is to make the copy_from_user simpler below
1355 if(cnt > (dmabuf->dmasize - swptr))
1356 cnt = dmabuf->dmasize - swptr;
1357 spin_unlock_irqrestore(&state->card->lock, flags);
1358
1359 #ifdef DEBUG2
1360 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt);
1361 #endif
1362 if (cnt > count)
1363 cnt = count;
1364 if (cnt <= 0) {
1365 unsigned long tmo;
1366 // There is data waiting to be played
1367 if(!dmabuf->enable && dmabuf->count) {
1368 /* force the starting incase SETTRIGGER has been used */
1369 /* to stop it, otherwise this is a deadlock situation */
1370 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
1371 start_dac(state);
1372 }
1373 // Update the LVI pointer in case we have already
1374 // written data in this syscall and are just waiting
1375 // on the tail bit of data
1376 i810_update_lvi(state,0);
1377 if (file->f_flags & O_NONBLOCK) {
1378 if (!ret) ret = -EAGAIN;
1379 return ret;
1380 }
1381 /* Not strictly correct but works */
1382 tmo = (dmabuf->dmasize * HZ) / (dmabuf->rate * 4);
1383 /* There are two situations when sleep_on_timeout returns, one is when
1384 the interrupt is serviced correctly and the process is waked up by
1385 ISR ON TIME. Another is when timeout is expired, which means that
1386 either interrupt is NOT serviced correctly (pending interrupt) or it
1387 is TOO LATE for the process to be scheduled to run (scheduler latency)
1388 which results in a (potential) buffer underrun. And worse, there is
1389 NOTHING we can do to prevent it. */
1390 if (!interruptible_sleep_on_timeout(&dmabuf->wait, tmo)) {
1391 #ifdef DEBUG
1392 printk(KERN_ERR "i810_audio: playback schedule timeout, "
1393 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1394 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1395 dmabuf->hwptr, dmabuf->swptr);
1396 #endif
1397 /* a buffer underrun, we delay the recovery until next time the
1398 while loop begin and we REALLY have data to play */
1399 //return ret;
1400 }
1401 if (signal_pending(current)) {
1402 if (!ret) ret = -ERESTARTSYS;
1403 return ret;
1404 }
1405 continue;
1406 }
1407 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
1408 if (!ret) ret = -EFAULT;
1409 return ret;
1410 }
1411
1412 swptr = (swptr + cnt) % dmabuf->dmasize;
1413
1414 spin_lock_irqsave(&state->card->lock, flags);
1415 dmabuf->swptr = swptr;
1416 dmabuf->count += cnt;
1417 spin_unlock_irqrestore(&state->card->lock, flags);
1418
1419 count -= cnt;
1420 buffer += cnt;
1421 ret += cnt;
1422 }
1423 if (swptr % dmabuf->fragsize) {
1424 x = dmabuf->fragsize - (swptr % dmabuf->fragsize);
1425 memset(dmabuf->rawbuf + swptr, '\0', x);
1426 }
1427 i810_update_lvi(state,0);
1428 if (!dmabuf->enable && dmabuf->count >= dmabuf->userfragsize)
1429 start_dac(state);
1430
1431 return ret;
1432 }
1433
1434 /* No kernel lock - we have our own spinlock */
1435 static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait)
1436 {
1437 struct i810_state *state = (struct i810_state *)file->private_data;
1438 struct dmabuf *dmabuf = &state->dmabuf;
1439 unsigned long flags;
1440 unsigned int mask = 0;
1441
1442 if(!dmabuf->ready)
1443 return 0;
1444 poll_wait(file, &dmabuf->wait, wait);
1445 spin_lock_irqsave(&state->card->lock, flags);
1446 i810_update_ptr(state);
1447 if (file->f_mode & FMODE_READ && dmabuf->enable & ADC_RUNNING) {
1448 if (dmabuf->count >= (signed)dmabuf->fragsize)
1449 mask |= POLLIN | POLLRDNORM;
1450 }
1451 if (file->f_mode & FMODE_WRITE && dmabuf->enable & DAC_RUNNING) {
1452 if (dmabuf->mapped) {
1453 if (dmabuf->count >= (signed)dmabuf->fragsize)
1454 mask |= POLLOUT | POLLWRNORM;
1455 } else {
1456 if ((signed)dmabuf->dmasize >= dmabuf->count + (signed)dmabuf->fragsize)
1457 mask |= POLLOUT | POLLWRNORM;
1458 }
1459 }
1460 spin_unlock_irqrestore(&state->card->lock, flags);
1461
1462 return mask;
1463 }
1464
1465 static int i810_mmap(struct file *file, struct vm_area_struct *vma)
1466 {
1467 struct i810_state *state = (struct i810_state *)file->private_data;
1468 struct dmabuf *dmabuf = &state->dmabuf;
1469 int ret = -EINVAL;
1470 unsigned long size;
1471
1472 lock_kernel();
1473 if (vma->vm_flags & VM_WRITE) {
1474 if (!dmabuf->write_channel &&
1475 (dmabuf->write_channel =
1476 state->card->alloc_pcm_channel(state->card)) == NULL) {
1477 ret = -EBUSY;
1478 goto out;
1479 }
1480 }
1481 if (vma->vm_flags & VM_READ) {
1482 if (!dmabuf->read_channel &&
1483 (dmabuf->read_channel =
1484 state->card->alloc_rec_pcm_channel(state->card)) == NULL) {
1485 ret = -EBUSY;
1486 goto out;
1487 }
1488 }
1489 if ((ret = prog_dmabuf(state, 0)) != 0)
1490 goto out;
1491
1492 ret = -EINVAL;
1493 if (vma->vm_pgoff != 0)
1494 goto out;
1495 size = vma->vm_end - vma->vm_start;
1496 if (size > (PAGE_SIZE << dmabuf->buforder))
1497 goto out;
1498 ret = -EAGAIN;
1499 if (remap_page_range(vma->vm_start, virt_to_phys(dmabuf->rawbuf),
1500 size, vma->vm_page_prot))
1501 goto out;
1502 dmabuf->mapped = 1;
1503 if(vma->vm_flags & VM_WRITE)
1504 dmabuf->count = dmabuf->dmasize;
1505 else
1506 dmabuf->count = 0;
1507 ret = 0;
1508 #ifdef DEBUG
1509 printk("i810_audio: mmap'ed %ld bytes of data space\n", size);
1510 #endif
1511 out:
1512 unlock_kernel();
1513 return ret;
1514 }
1515
1516 static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1517 {
1518 struct i810_state *state = (struct i810_state *)file->private_data;
1519 struct dmabuf *dmabuf = &state->dmabuf;
1520 unsigned long flags;
1521 audio_buf_info abinfo;
1522 count_info cinfo;
1523 unsigned int i_glob_cnt;
1524 int val = 0, mapped, ret;
1525 struct ac97_codec *codec = state->card->ac97_codec[0];
1526
1527 mapped = ((file->f_mode & FMODE_WRITE) && dmabuf->mapped) ||
1528 ((file->f_mode & FMODE_READ) && dmabuf->mapped);
1529 #ifdef DEBUG
1530 printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *(int *)arg : 0);
1531 #endif
1532
1533 switch (cmd)
1534 {
1535 case OSS_GETVERSION:
1536 #ifdef DEBUG
1537 printk("OSS_GETVERSION\n");
1538 #endif
1539 return put_user(SOUND_VERSION, (int *)arg);
1540
1541 case SNDCTL_DSP_RESET:
1542 #ifdef DEBUG
1543 printk("SNDCTL_DSP_RESET\n");
1544 #endif
1545 /* FIXME: spin_lock ? */
1546 if (dmabuf->enable == DAC_RUNNING) {
1547 stop_dac(state);
1548 }
1549 if (dmabuf->enable == ADC_RUNNING) {
1550 stop_adc(state);
1551 }
1552 synchronize_irq();
1553 dmabuf->ready = 0;
1554 dmabuf->swptr = dmabuf->hwptr = 0;
1555 dmabuf->count = dmabuf->total_bytes = 0;
1556 return 0;
1557
1558 case SNDCTL_DSP_SYNC:
1559 #ifdef DEBUG
1560 printk("SNDCTL_DSP_SYNC\n");
1561 #endif
1562 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK)
1563 return 0;
1564 drain_dac(state, 0);
1565 dmabuf->ready = 0;
1566 dmabuf->swptr = dmabuf->hwptr = 0;
1567 dmabuf->count = dmabuf->total_bytes = 0;
1568 return 0;
1569
1570 case SNDCTL_DSP_SPEED: /* set smaple rate */
1571 #ifdef DEBUG
1572 printk("SNDCTL_DSP_SPEED\n");
1573 #endif
1574 if (get_user(val, (int *)arg))
1575 return -EFAULT;
1576 if (val >= 0) {
1577 if (file->f_mode & FMODE_WRITE) {
1578 if ( (state->card->ac97_status & SPDIF_ON) ) { /* S/PDIF Enabled */
1579 /* AD1886 only supports 48000, need to check that */
1580 if ( i810_valid_spdif_rate ( codec, val ) ) {
1581 /* Set DAC rate */
1582 i810_set_spdif_output ( state, -1, 0 );
1583 stop_dac(state);
1584 dmabuf->ready = 0;
1585 spin_lock_irqsave(&state->card->lock, flags);
1586 i810_set_dac_rate(state, val);
1587 spin_unlock_irqrestore(&state->card->lock, flags);
1588 /* Set S/PDIF transmitter rate. */
1589 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val );
1590 if ( ! (state->card->ac97_status & SPDIF_ON) ) {
1591 val = dmabuf->rate;
1592 }
1593 } else { /* Not a valid rate for S/PDIF, ignore it */
1594 val = dmabuf->rate;
1595 }
1596 } else {
1597 stop_dac(state);
1598 dmabuf->ready = 0;
1599 spin_lock_irqsave(&state->card->lock, flags);
1600 i810_set_dac_rate(state, val);
1601 spin_unlock_irqrestore(&state->card->lock, flags);
1602 }
1603 }
1604 if (file->f_mode & FMODE_READ) {
1605 stop_adc(state);
1606 dmabuf->ready = 0;
1607 spin_lock_irqsave(&state->card->lock, flags);
1608 i810_set_adc_rate(state, val);
1609 spin_unlock_irqrestore(&state->card->lock, flags);
1610 }
1611 }
1612 return put_user(dmabuf->rate, (int *)arg);
1613
1614 case SNDCTL_DSP_STEREO: /* set stereo or mono channel */
1615 #ifdef DEBUG
1616 printk("SNDCTL_DSP_STEREO\n");
1617 #endif
1618 if (get_user(val, (int *)arg))
1619 return -EFAULT;
1620
1621 if (dmabuf->enable & DAC_RUNNING) {
1622 stop_dac(state);
1623 }
1624 if (dmabuf->enable & ADC_RUNNING) {
1625 stop_adc(state);
1626 }
1627 return put_user(1, (int *)arg);
1628
1629 case SNDCTL_DSP_GETBLKSIZE:
1630 if (file->f_mode & FMODE_WRITE) {
1631 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)))
1632 return val;
1633 }
1634 if (file->f_mode & FMODE_READ) {
1635 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)))
1636 return val;
1637 }
1638 #ifdef DEBUG
1639 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize);
1640 #endif
1641 return put_user(dmabuf->userfragsize, (int *)arg);
1642
1643 case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/
1644 #ifdef DEBUG
1645 printk("SNDCTL_DSP_GETFMTS\n");
1646 #endif
1647 return put_user(AFMT_S16_LE, (int *)arg);
1648
1649 case SNDCTL_DSP_SETFMT: /* Select sample format */
1650 #ifdef DEBUG
1651 printk("SNDCTL_DSP_SETFMT\n");
1652 #endif
1653 if (get_user(val, (int *)arg))
1654 return -EFAULT;
1655
1656 switch ( val ) {
1657 case AFMT_S16_LE:
1658 break;
1659 case AFMT_QUERY:
1660 default:
1661 val = AFMT_S16_LE;
1662 break;
1663 }
1664 return put_user(val, (int *)arg);
1665
1666 case SNDCTL_DSP_CHANNELS:
1667 #ifdef DEBUG
1668 printk("SNDCTL_DSP_CHANNELS\n");
1669 #endif
1670 if (get_user(val, (int *)arg))
1671 return -EFAULT;
1672
1673 if (val > 0) {
1674 if (dmabuf->enable & DAC_RUNNING) {
1675 stop_dac(state);
1676 }
1677 if (dmabuf->enable & ADC_RUNNING) {
1678 stop_adc(state);
1679 }
1680 } else {
1681 return put_user(state->card->channels, (int *)arg);
1682 }
1683
1684 /* ICH and ICH0 only support 2 channels */
1685 if ( state->card->pci_id == 0x2415 || state->card->pci_id == 0x2425 )
1686 return put_user(2, (int *)arg);
1687
1688 /* Multi-channel support was added with ICH2. Bits in */
1689 /* Global Status and Global Control register are now */
1690 /* used to indicate this. */
1691
1692 i_glob_cnt = inl(state->card->iobase + GLOB_CNT);
1693
1694 /* Current # of channels enabled */
1695 if ( i_glob_cnt & 0x0100000 )
1696 ret = 4;
1697 else if ( i_glob_cnt & 0x0200000 )
1698 ret = 6;
1699 else
1700 ret = 2;
1701
1702 switch ( val ) {
1703 case 2: /* 2 channels is always supported */
1704 outl(state->card->iobase + GLOB_CNT, (i_glob_cnt & 0xcfffff));
1705 /* Do we need to change mixer settings???? */
1706 break;
1707 case 4: /* Supported on some chipsets, better check first */
1708 if ( state->card->channels >= 4 ) {
1709 outl(state->card->iobase + GLOB_CNT, ((i_glob_cnt & 0xcfffff) | 0x0100000));
1710 /* Do we need to change mixer settings??? */
1711 } else {
1712 val = ret;
1713 }
1714 break;
1715 case 6: /* Supported on some chipsets, better check first */
1716 if ( state->card->channels >= 6 ) {
1717 outl(state->card->iobase + GLOB_CNT, ((i_glob_cnt & 0xcfffff) | 0x0200000));
1718 /* Do we need to change mixer settings??? */
1719 } else {
1720 val = ret;
1721 }
1722 break;
1723 default: /* nothing else is ever supported by the chipset */
1724 val = ret;
1725 break;
1726 }
1727
1728 return put_user(val, (int *)arg);
1729
1730 case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */
1731 /* we update the swptr to the end of the last sg segment then return */
1732 #ifdef DEBUG
1733 printk("SNDCTL_DSP_POST\n");
1734 #endif
1735 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING))
1736 return 0;
1737 if((dmabuf->swptr % dmabuf->fragsize) != 0) {
1738 val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize);
1739 dmabuf->swptr += val;
1740 dmabuf->count += val;
1741 }
1742 return 0;
1743
1744 case SNDCTL_DSP_SUBDIVIDE:
1745 if (dmabuf->subdivision)
1746 return -EINVAL;
1747 if (get_user(val, (int *)arg))
1748 return -EFAULT;
1749 if (val != 1 && val != 2 && val != 4)
1750 return -EINVAL;
1751 #ifdef DEBUG
1752 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val);
1753 #endif
1754 dmabuf->subdivision = val;
1755 dmabuf->ready = 0;
1756 return 0;
1757
1758 case SNDCTL_DSP_SETFRAGMENT:
1759 if (get_user(val, (int *)arg))
1760 return -EFAULT;
1761
1762 dmabuf->ossfragsize = 1<<(val & 0xffff);
1763 dmabuf->ossmaxfrags = (val >> 16) & 0xffff;
1764 if (dmabuf->ossmaxfrags <= 4)
1765 dmabuf->ossmaxfrags = 4;
1766 else if (dmabuf->ossmaxfrags <= 8)
1767 dmabuf->ossmaxfrags = 8;
1768 else if (dmabuf->ossmaxfrags <= 16)
1769 dmabuf->ossmaxfrags = 16;
1770 else
1771 dmabuf->ossmaxfrags = 32;
1772 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
1773 if (val < 16384)
1774 val = 16384;
1775 if (val > 65536)
1776 val = 65536;
1777 dmabuf->ossmaxfrags = val/dmabuf->ossfragsize;
1778 if(dmabuf->ossmaxfrags<4)
1779 dmabuf->ossfragsize = val/4;
1780 dmabuf->ready = 0;
1781 #ifdef DEBUG
1782 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val,
1783 dmabuf->ossfragsize, dmabuf->ossmaxfrags);
1784 #endif
1785
1786 return 0;
1787
1788 case SNDCTL_DSP_GETOSPACE:
1789 if (!(file->f_mode & FMODE_WRITE))
1790 return -EINVAL;
1791 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
1792 return val;
1793 spin_lock_irqsave(&state->card->lock, flags);
1794 i810_update_ptr(state);
1795 abinfo.fragsize = dmabuf->userfragsize;
1796 abinfo.fragstotal = dmabuf->userfrags;
1797 if(dmabuf->mapped)
1798 abinfo.bytes = dmabuf->count;
1799 else
1800 abinfo.bytes = dmabuf->dmasize - dmabuf->count;
1801 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
1802 spin_unlock_irqrestore(&state->card->lock, flags);
1803 #ifdef DEBUG
1804 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes,
1805 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
1806 #endif
1807 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1808
1809 case SNDCTL_DSP_GETOPTR:
1810 if (!(file->f_mode & FMODE_WRITE))
1811 return -EINVAL;
1812 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
1813 return val;
1814 spin_lock_irqsave(&state->card->lock, flags);
1815 i810_update_ptr(state);
1816 cinfo.bytes = dmabuf->total_bytes;
1817 cinfo.ptr = dmabuf->hwptr;
1818 cinfo.blocks = (dmabuf->dmasize - dmabuf->count)/dmabuf->userfragsize;
1819 if (dmabuf->mapped) {
1820 dmabuf->count = (dmabuf->dmasize -
1821 (dmabuf->count & (dmabuf->userfragsize-1)));
1822 __i810_update_lvi(state, 0);
1823 }
1824 spin_unlock_irqrestore(&state->card->lock, flags);
1825 #ifdef DEBUG
1826 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes,
1827 cinfo.blocks, cinfo.ptr, dmabuf->count);
1828 #endif
1829 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1830
1831 case SNDCTL_DSP_GETISPACE:
1832 if (!(file->f_mode & FMODE_READ))
1833 return -EINVAL;
1834 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0)
1835 return val;
1836 spin_lock_irqsave(&state->card->lock, flags);
1837 i810_update_ptr(state);
1838 abinfo.fragsize = dmabuf->userfragsize;
1839 abinfo.fragstotal = dmabuf->userfrags;
1840 abinfo.bytes = dmabuf->dmasize - dmabuf->count;
1841 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
1842 spin_unlock_irqrestore(&state->card->lock, flags);
1843 #ifdef DEBUG
1844 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes,
1845 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
1846 #endif
1847 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1848
1849 case SNDCTL_DSP_GETIPTR:
1850 if (!(file->f_mode & FMODE_READ))
1851 return -EINVAL;
1852 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
1853 return val;
1854 spin_lock_irqsave(&state->card->lock, flags);
1855 i810_update_ptr(state);
1856 cinfo.bytes = dmabuf->total_bytes;
1857 cinfo.blocks = dmabuf->count/dmabuf->userfragsize;
1858 cinfo.ptr = dmabuf->hwptr;
1859 if (dmabuf->mapped) {
1860 dmabuf->count &= (dmabuf->userfragsize-1);
1861 __i810_update_lvi(state, 1);
1862 }
1863 spin_unlock_irqrestore(&state->card->lock, flags);
1864 #ifdef DEBUG
1865 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes,
1866 cinfo.blocks, cinfo.ptr, dmabuf->count);
1867 #endif
1868 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1869
1870 case SNDCTL_DSP_NONBLOCK:
1871 #ifdef DEBUG
1872 printk("SNDCTL_DSP_NONBLOCK\n");
1873 #endif
1874 file->f_flags |= O_NONBLOCK;
1875 return 0;
1876
1877 case SNDCTL_DSP_GETCAPS:
1878 #ifdef DEBUG
1879 printk("SNDCTL_DSP_GETCAPS\n");
1880 #endif
1881 return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND,
1882 (int *)arg);
1883
1884 case SNDCTL_DSP_GETTRIGGER:
1885 val = 0;
1886 #ifdef DEBUG
1887 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger);
1888 #endif
1889 return put_user(dmabuf->trigger, (int *)arg);
1890
1891 case SNDCTL_DSP_SETTRIGGER:
1892 if (get_user(val, (int *)arg))
1893 return -EFAULT;
1894 #ifdef DEBUG
1895 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
1896 #endif
1897 if( !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) {
1898 stop_adc(state);
1899 }
1900 if( !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) {
1901 stop_dac(state);
1902 }
1903 dmabuf->trigger = val;
1904 if(val & PCM_ENABLE_OUTPUT) {
1905 if (!dmabuf->write_channel) {
1906 dmabuf->ready = 0;
1907 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
1908 if (!dmabuf->write_channel)
1909 return -EBUSY;
1910 }
1911 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1912 return ret;
1913 if (dmabuf->mapped) {
1914 dmabuf->count = dmabuf->dmasize;
1915 i810_update_lvi(state,0);
1916 }
1917 if (!dmabuf->enable && dmabuf->count > dmabuf->userfragsize)
1918 start_dac(state);
1919 }
1920 if(val & PCM_ENABLE_INPUT) {
1921 if (!dmabuf->read_channel) {
1922 dmabuf->ready = 0;
1923 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
1924 if (!dmabuf->read_channel)
1925 return -EBUSY;
1926 }
1927 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1928 return ret;
1929 if (dmabuf->mapped) {
1930 dmabuf->count = 0;
1931 i810_update_lvi(state,1);
1932 }
1933 if (!dmabuf->enable && dmabuf->count <
1934 (dmabuf->dmasize - dmabuf->userfragsize))
1935 start_adc(state);
1936 }
1937 return 0;
1938
1939 case SNDCTL_DSP_SETDUPLEX:
1940 #ifdef DEBUG
1941 printk("SNDCTL_DSP_SETDUPLEX\n");
1942 #endif
1943 return -EINVAL;
1944
1945 case SNDCTL_DSP_GETODELAY:
1946 if (!(file->f_mode & FMODE_WRITE))
1947 return -EINVAL;
1948 spin_lock_irqsave(&state->card->lock, flags);
1949 i810_update_ptr(state);
1950 val = dmabuf->count;
1951 spin_unlock_irqrestore(&state->card->lock, flags);
1952 #ifdef DEBUG
1953 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count);
1954 #endif
1955 return put_user(val, (int *)arg);
1956
1957 case SOUND_PCM_READ_RATE:
1958 #ifdef DEBUG
1959 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate);
1960 #endif
1961 return put_user(dmabuf->rate, (int *)arg);
1962
1963 case SOUND_PCM_READ_CHANNELS:
1964 #ifdef DEBUG
1965 printk("SOUND_PCM_READ_CHANNELS\n");
1966 #endif
1967 return put_user(2, (int *)arg);
1968
1969 case SOUND_PCM_READ_BITS:
1970 #ifdef DEBUG
1971 printk("SOUND_PCM_READ_BITS\n");
1972 #endif
1973 return put_user(AFMT_S16_LE, (int *)arg);
1974
1975 case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */
1976 #ifdef DEBUG
1977 printk("SNDCTL_DSP_SETSPDIF\n");
1978 #endif
1979 if (get_user(val, (int *)arg))
1980 return -EFAULT;
1981
1982 /* Check to make sure the codec supports S/PDIF transmitter */
1983
1984 if((state->card->ac97_features & 4)) {
1985 /* mask out the transmitter speed bits so the user can't set them */
1986 val &= ~0x3000;
1987
1988 /* Add the current transmitter speed bits to the passed value */
1989 ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
1990 val |= (ret & 0x3000);
1991
1992 i810_ac97_set(codec, AC97_SPDIF_CONTROL, val);
1993 if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) {
1994 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val);
1995 return -EFAULT;
1996 }
1997 }
1998 #ifdef DEBUG
1999 else
2000 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2001 #endif
2002 return put_user(val, (int *)arg);
2003
2004 case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */
2005 #ifdef DEBUG
2006 printk("SNDCTL_DSP_GETSPDIF\n");
2007 #endif
2008 if (get_user(val, (int *)arg))
2009 return -EFAULT;
2010
2011 /* Check to make sure the codec supports S/PDIF transmitter */
2012
2013 if(!(state->card->ac97_features & 4)) {
2014 #ifdef DEBUG
2015 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2016 #endif
2017 val = 0;
2018 } else {
2019 val = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2020 }
2021 //return put_user((val & 0xcfff), (int *)arg);
2022 return put_user(val, (int *)arg);
2023
2024 case SNDCTL_DSP_GETCHANNELMASK:
2025 #ifdef DEBUG
2026 printk("SNDCTL_DSP_GETCHANNELMASK\n");
2027 #endif
2028 if (get_user(val, (int *)arg))
2029 return -EFAULT;
2030
2031 /* Based on AC'97 DAC support, not ICH hardware */
2032 val = DSP_BIND_FRONT;
2033 if ( state->card->ac97_features & 0x0004 )
2034 val |= DSP_BIND_SPDIF;
2035
2036 if ( state->card->ac97_features & 0x0080 )
2037 val |= DSP_BIND_SURR;
2038 if ( state->card->ac97_features & 0x0140 )
2039 val |= DSP_BIND_CENTER_LFE;
2040
2041 return put_user(val, (int *)arg);
2042
2043 case SNDCTL_DSP_BIND_CHANNEL:
2044 #ifdef DEBUG
2045 printk("SNDCTL_DSP_BIND_CHANNEL\n");
2046 #endif
2047 if (get_user(val, (int *)arg))
2048 return -EFAULT;
2049 if ( val == DSP_BIND_QUERY ) {
2050 val = DSP_BIND_FRONT; /* Always report this as being enabled */
2051 if ( state->card->ac97_status & SPDIF_ON )
2052 val |= DSP_BIND_SPDIF;
2053 else {
2054 if ( state->card->ac97_status & SURR_ON )
2055 val |= DSP_BIND_SURR;
2056 if ( state->card->ac97_status & CENTER_LFE_ON )
2057 val |= DSP_BIND_CENTER_LFE;
2058 }
2059 } else { /* Not a query, set it */
2060 if (!(file->f_mode & FMODE_WRITE))
2061 return -EINVAL;
2062 if ( dmabuf->enable == DAC_RUNNING ) {
2063 stop_dac(state);
2064 }
2065 if ( val & DSP_BIND_SPDIF ) { /* Turn on SPDIF */
2066 /* Ok, this should probably define what slots
2067 * to use. For now, we'll only set it to the
2068 * defaults:
2069 *
2070 * non multichannel codec maps to slots 3&4
2071 * 2 channel codec maps to slots 7&8
2072 * 4 channel codec maps to slots 6&9
2073 * 6 channel codec maps to slots 10&11
2074 *
2075 * there should be some way for the app to
2076 * select the slot assignment.
2077 */
2078
2079 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate );
2080 if ( !(state->card->ac97_status & SPDIF_ON) )
2081 val &= ~DSP_BIND_SPDIF;
2082 } else {
2083 int mask;
2084 int channels;
2085
2086 /* Turn off S/PDIF if it was on */
2087 if ( state->card->ac97_status & SPDIF_ON )
2088 i810_set_spdif_output ( state, -1, 0 );
2089
2090 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE);
2091 switch (mask) {
2092 case DSP_BIND_FRONT:
2093 channels = 2;
2094 break;
2095 case DSP_BIND_FRONT|DSP_BIND_SURR:
2096 channels = 4;
2097 break;
2098 case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2099 channels = 6;
2100 break;
2101 default:
2102 val = DSP_BIND_FRONT;
2103 channels = 2;
2104 break;
2105 }
2106 i810_set_dac_channels ( state, channels );
2107
2108 /* check that they really got turned on */
2109 if ( !state->card->ac97_status & SURR_ON )
2110 val &= ~DSP_BIND_SURR;
2111 if ( !state->card->ac97_status & CENTER_LFE_ON )
2112 val &= ~DSP_BIND_CENTER_LFE;
2113 }
2114 }
2115 return put_user(val, (int *)arg);
2116
2117 case SNDCTL_DSP_MAPINBUF:
2118 case SNDCTL_DSP_MAPOUTBUF:
2119 case SNDCTL_DSP_SETSYNCRO:
2120 case SOUND_PCM_WRITE_FILTER:
2121 case SOUND_PCM_READ_FILTER:
2122 #ifdef DEBUG
2123 printk("SNDCTL_* -EINVAL\n");
2124 #endif
2125 return -EINVAL;
2126 }
2127 return -EINVAL;
2128 }
2129
2130 static int i810_open(struct inode *inode, struct file *file)
2131 {
2132 int i = 0;
2133 struct i810_card *card = devs;
2134 struct i810_state *state = NULL;
2135 struct dmabuf *dmabuf = NULL;
2136
2137 /* find an avaiable virtual channel (instance of /dev/dsp) */
2138 while (card != NULL) {
2139 for (i = 0; i < NR_HW_CH; i++) {
2140 if (card->states[i] == NULL) {
2141 state = card->states[i] = (struct i810_state *)
2142 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2143 if (state == NULL)
2144 return -ENOMEM;
2145 memset(state, 0, sizeof(struct i810_state));
2146 dmabuf = &state->dmabuf;
2147 goto found_virt;
2148 }
2149 }
2150 card = card->next;
2151 }
2152 /* no more virtual channel avaiable */
2153 if (!state)
2154 return -ENODEV;
2155
2156 found_virt:
2157 /* initialize the virtual channel */
2158 state->virt = i;
2159 state->card = card;
2160 state->magic = I810_STATE_MAGIC;
2161 init_waitqueue_head(&dmabuf->wait);
2162 init_MUTEX(&state->open_sem);
2163 file->private_data = state;
2164 dmabuf->trigger = 0;
2165
2166 /* allocate hardware channels */
2167 if(file->f_mode & FMODE_READ) {
2168 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) {
2169 kfree (card->states[i]);
2170 card->states[i] = NULL;;
2171 return -EBUSY;
2172 }
2173 i810_set_adc_rate(state, 8000);
2174 dmabuf->trigger |= PCM_ENABLE_INPUT;
2175 }
2176 if(file->f_mode & FMODE_WRITE) {
2177 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) {
2178 kfree (card->states[i]);
2179 card->states[i] = NULL;;
2180 return -EBUSY;
2181 }
2182 /* Initialize to 8kHz? What if we don't support 8kHz? */
2183 /* Let's change this to check for S/PDIF stuff */
2184
2185 if ( spdif_locked ) {
2186 i810_set_dac_rate(state, spdif_locked);
2187 i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked);
2188 } else {
2189 i810_set_dac_rate(state, 8000);
2190 }
2191 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
2192 }
2193
2194 /* set default sample format. According to OSS Programmer's Guide /dev/dsp
2195 should be default to unsigned 8-bits, mono, with sample rate 8kHz and
2196 /dev/dspW will accept 16-bits sample, but we don't support those so we
2197 set it immediately to stereo and 16bit, which is all we do support */
2198 dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO;
2199 dmabuf->ossfragsize = 0;
2200 dmabuf->ossmaxfrags = 0;
2201 dmabuf->subdivision = 0;
2202
2203 state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2204
2205 return 0;
2206 }
2207
2208 static int i810_release(struct inode *inode, struct file *file)
2209 {
2210 struct i810_state *state = (struct i810_state *)file->private_data;
2211 struct i810_card *card = state->card;
2212 struct dmabuf *dmabuf = &state->dmabuf;
2213 unsigned long flags;
2214
2215 lock_kernel();
2216
2217 /* stop DMA state machine and free DMA buffers/channels */
2218 if(dmabuf->enable & DAC_RUNNING ||
2219 (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
2220 drain_dac(state,0);
2221 }
2222 if(dmabuf->enable & ADC_RUNNING) {
2223 stop_adc(state);
2224 }
2225 spin_lock_irqsave(&card->lock, flags);
2226 dealloc_dmabuf(state);
2227 if (file->f_mode & FMODE_WRITE) {
2228 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num);
2229 }
2230 if (file->f_mode & FMODE_READ) {
2231 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num);
2232 }
2233
2234 state->card->states[state->virt] = NULL;
2235 kfree(state);
2236 spin_unlock_irqrestore(&card->lock, flags);
2237 unlock_kernel();
2238
2239 return 0;
2240 }
2241
2242 static /*const*/ struct file_operations i810_audio_fops = {
2243 owner: THIS_MODULE,
2244 llseek: no_llseek,
2245 read: i810_read,
2246 write: i810_write,
2247 poll: i810_poll,
2248 ioctl: i810_ioctl,
2249 mmap: i810_mmap,
2250 open: i810_open,
2251 release: i810_release,
2252 };
2253
2254 /* Write AC97 codec registers */
2255
2256 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg)
2257 {
2258 struct i810_card *card = dev->private_data;
2259 int count = 100;
2260 u8 reg_set = ((dev->id)?((reg&0x7f)|0x80):(reg&0x7f));
2261
2262 while(count-- && (inb(card->iobase + CAS) & 1))
2263 udelay(1);
2264
2265 return inw(card->ac97base + reg_set);
2266 }
2267
2268 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data)
2269 {
2270 struct i810_card *card = dev->private_data;
2271 int count = 100;
2272 u8 reg_set = ((dev->id)?((reg&0x7f)|0x80):(reg&0x7f));
2273
2274 while(count-- && (inb(card->iobase + CAS) & 1))
2275 udelay(1);
2276 outw(data, card->ac97base + reg_set);
2277 }
2278
2279
2280 /* OSS /dev/mixer file operation methods */
2281
2282 static int i810_open_mixdev(struct inode *inode, struct file *file)
2283 {
2284 int i;
2285 int minor = MINOR(inode->i_rdev);
2286 struct i810_card *card = devs;
2287
2288 for (card = devs; card != NULL; card = card->next)
2289 for (i = 0; i < NR_AC97; i++)
2290 if (card->ac97_codec[i] != NULL &&
2291 card->ac97_codec[i]->dev_mixer == minor) {
2292 file->private_data = card->ac97_codec[i];
2293 return 0;
2294 }
2295 return -ENODEV;
2296 }
2297
2298 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2299 unsigned long arg)
2300 {
2301 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2302
2303 return codec->mixer_ioctl(codec, cmd, arg);
2304 }
2305
2306 static /*const*/ struct file_operations i810_mixer_fops = {
2307 owner: THIS_MODULE,
2308 llseek: no_llseek,
2309 ioctl: i810_ioctl_mixdev,
2310 open: i810_open_mixdev,
2311 };
2312
2313 /* AC97 codec initialisation. */
2314 static int __init i810_ac97_init(struct i810_card *card)
2315 {
2316 int num_ac97 = 0;
2317 int total_channels = 0;
2318 struct ac97_codec *codec;
2319 u16 eid;
2320 int i=0;
2321 u32 reg;
2322
2323 reg = inl(card->iobase + GLOB_CNT);
2324
2325 if((reg&2)==0) /* Cold required */
2326 reg|=2;
2327 else
2328 reg|=4; /* Warm */
2329
2330 reg&=~8; /* ACLink on */
2331 outl(reg , card->iobase + GLOB_CNT);
2332
2333 while(i<10)
2334 {
2335 if((inl(card->iobase+GLOB_CNT)&4)==0)
2336 break;
2337 current->state = TASK_UNINTERRUPTIBLE;
2338 schedule_timeout(HZ/20);
2339 i++;
2340 }
2341 if(i==10)
2342 {
2343 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n");
2344 return 0;
2345 }
2346
2347 current->state = TASK_UNINTERRUPTIBLE;
2348 schedule_timeout(HZ/5);
2349
2350 /* Number of channels supported */
2351 /* What about the codec? Just because the ICH supports */
2352 /* multiple channels doesn't mean the codec does. */
2353 /* we'll have to modify this in the codec section below */
2354 /* to reflect what the codec has. */
2355 /* ICH and ICH0 only support 2 channels so don't bother */
2356 /* to check.... */
2357
2358 card->channels = 2;
2359 reg = inl(card->iobase + GLOB_STA);
2360 if ( reg & 0x0200000 )
2361 card->channels = 6;
2362 else if ( reg & 0x0100000 )
2363 card->channels = 4;
2364 printk("i810_audio: Audio Controller supports %d channels.\n", card->channels);
2365
2366 inw(card->ac97base);
2367
2368 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
2369
2370 /* The ICH programmer's reference says you should */
2371 /* check the ready status before probing. So we chk */
2372 /* What do we do if it's not ready? Wait and try */
2373 /* again, or abort? */
2374 reg = inl(card->iobase + GLOB_STA);
2375 if (!(reg & (0x100 << num_ac97))) {
2376 if(num_ac97 == 0)
2377 printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
2378 break; /* I think this works, if not ready stop */
2379 }
2380
2381 if ((codec = kmalloc(sizeof(struct ac97_codec), GFP_KERNEL)) == NULL)
2382 return -ENOMEM;
2383 memset(codec, 0, sizeof(struct ac97_codec));
2384
2385 /* initialize some basic codec information, other fields will be filled
2386 in ac97_probe_codec */
2387 codec->private_data = card;
2388 codec->id = num_ac97;
2389
2390 codec->codec_read = i810_ac97_get;
2391 codec->codec_write = i810_ac97_set;
2392
2393 if (ac97_probe_codec(codec) == 0)
2394 break;
2395
2396 /* power up everything, modify this when implementing power saving */
2397 i810_ac97_set(codec, AC97_POWER_CONTROL,
2398 i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
2399 /* wait for analog ready */
2400 for (i=10;
2401 i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf);
2402 i--)
2403 {
2404 current->state = TASK_UNINTERRUPTIBLE;
2405 schedule_timeout(HZ/20);
2406 }
2407
2408 /* Store state information about S/PDIF transmitter */
2409 card->ac97_status = 0;
2410
2411 /* Don't attempt to get eid until powerup is complete */
2412 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2413
2414 if(eid==0xFFFFFF)
2415 {
2416 printk(KERN_WARNING "i810_audio: no codec attached ?\n");
2417 kfree(codec);
2418 break;
2419 }
2420
2421 card->ac97_features = eid;
2422
2423 /* Now check the codec for useful features to make up for
2424 the dumbness of the 810 hardware engine */
2425
2426 if(!(eid&0x0001))
2427 printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
2428 else
2429 {
2430 /* Enable variable rate mode */
2431 i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
2432 i810_ac97_set(codec,AC97_EXTENDED_STATUS,
2433 i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
2434
2435 if(!(i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1))
2436 {
2437 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
2438 card->ac97_features&=~1;
2439 }
2440 }
2441
2442 /* Determine how many channels the codec(s) support */
2443 /* - The primary codec always supports 2 */
2444 /* - If the codec supports AMAP, surround DACs will */
2445 /* automaticlly get assigned to slots. */
2446 /* * Check for surround DACs and increment if */
2447 /* found. */
2448 /* - Else check if the codec is revision 2.2 */
2449 /* * If surround DACs exist, assign them to slots */
2450 /* and increment channel count. */
2451
2452 /* All of this only applies to ICH2 and above. ICH */
2453 /* and ICH0 only support 2 channels. ICH2 will only */
2454 /* support multiple codecs in a "split audio" config. */
2455 /* as described above. */
2456
2457 /* TODO: Remove all the debugging messages! */
2458
2459 if((eid & 0xc000) == 0) /* primary codec */
2460 total_channels += 2;
2461
2462 if(eid & 0x200) { /* GOOD, AMAP support */
2463 if (eid & 0x0080) /* L/R Surround channels */
2464 total_channels += 2;
2465 if (eid & 0x0140) /* LFE and Center channels */
2466 total_channels += 2;
2467 printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", num_ac97, total_channels);
2468 } else if (eid & 0x0400) { /* this only works on 2.2 compliant codecs */
2469 eid &= 0xffcf;
2470 if((eid & 0xc000) != 0) {
2471 switch ( total_channels ) {
2472 case 2:
2473 /* Set dsa1, dsa0 to 01 */
2474 eid |= 0x0010;
2475 break;
2476 case 4:
2477 /* Set dsa1, dsa0 to 10 */
2478 eid |= 0x0020;
2479 break;
2480 case 6:
2481 /* Set dsa1, dsa0 to 11 */
2482 eid |= 0x0030;
2483 break;
2484 }
2485 total_channels += 2;
2486 }
2487 i810_ac97_set(codec, AC97_EXTENDED_ID, eid);
2488 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
2489 printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", num_ac97, eid);
2490 if (eid & 0x0080) /* L/R Surround channels */
2491 total_channels += 2;
2492 if (eid & 0x0140) /* LFE and Center channels */
2493 total_channels += 2;
2494 printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", num_ac97, total_channels);
2495 } else {
2496 printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", num_ac97, total_channels);
2497 }
2498
2499 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) {
2500 printk(KERN_ERR "i810_audio: couldn't register mixer!\n");
2501 kfree(codec);
2502 break;
2503 }
2504
2505 card->ac97_codec[num_ac97] = codec;
2506 }
2507
2508 /* pick the minimum of channels supported by ICHx or codec(s) */
2509 card->channels = (card->channels > total_channels)?total_channels:card->channels;
2510
2511 return num_ac97;
2512 }
2513
2514 static void __init i810_configure_clocking (void)
2515 {
2516 struct i810_card *card;
2517 struct i810_state *state;
2518 struct dmabuf *dmabuf;
2519 unsigned int i, offset, new_offset;
2520 unsigned long flags;
2521
2522 card = devs;
2523 /* We could try to set the clocking for multiple cards, but can you even have
2524 * more than one i810 in a machine? Besides, clocking is global, so unless
2525 * someone actually thinks more than one i810 in a machine is possible and
2526 * decides to rewrite that little bit, setting the rate for more than one card
2527 * is a waste of time.
2528 */
2529 if(card != NULL) {
2530 state = card->states[0] = (struct i810_state *)
2531 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2532 if (state == NULL)
2533 return;
2534 memset(state, 0, sizeof(struct i810_state));
2535 dmabuf = &state->dmabuf;
2536
2537 dmabuf->write_channel = card->alloc_pcm_channel(card);
2538 state->virt = 0;
2539 state->card = card;
2540 state->magic = I810_STATE_MAGIC;
2541 init_waitqueue_head(&dmabuf->wait);
2542 init_MUTEX(&state->open_sem);
2543 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT;
2544 dmabuf->trigger = PCM_ENABLE_OUTPUT;
2545 i810_set_dac_rate(state, 48000);
2546 if(prog_dmabuf(state, 0) != 0) {
2547 goto config_out_nodmabuf;
2548 }
2549 if(dmabuf->dmasize < 16384) {
2550 goto config_out;
2551 }
2552 dmabuf->count = dmabuf->dmasize;
2553 outb(31,card->iobase+dmabuf->write_channel->port+OFF_LVI);
2554 save_flags(flags);
2555 cli();
2556 start_dac(state);
2557 offset = i810_get_dma_addr(state, 0);
2558 mdelay(50);
2559 new_offset = i810_get_dma_addr(state, 0);
2560 stop_dac(state);
2561 outb(2,card->iobase+dmabuf->write_channel->port+OFF_CR);
2562 restore_flags(flags);
2563 i = new_offset - offset;
2564 #ifdef DEBUG
2565 printk("i810_audio: %d bytes in 50 milliseconds\n", i);
2566 #endif
2567 if(i == 0)
2568 goto config_out;
2569 i = i / 4 * 20;
2570 if (i > 48500 || i < 47500) {
2571 clocking = clocking * clocking / i;
2572 printk("i810_audio: setting clocking to %d\n", clocking);
2573 }
2574 config_out:
2575 dealloc_dmabuf(state);
2576 config_out_nodmabuf:
2577 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num);
2578 kfree(state);
2579 card->states[0] = NULL;
2580 }
2581 }
2582
2583 /* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered
2584 until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */
2585
2586 static int __init i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
2587 {
2588 struct i810_card *card;
2589
2590 if (pci_enable_device(pci_dev))
2591 return -EIO;
2592
2593 if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) {
2594 printk(KERN_ERR "intel810: architecture does not support"
2595 " 32bit PCI busmaster DMA\n");
2596 return -ENODEV;
2597 }
2598
2599 if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) {
2600 printk(KERN_ERR "i810_audio: out of memory\n");
2601 return -ENOMEM;
2602 }
2603 memset(card, 0, sizeof(*card));
2604
2605 card->iobase = pci_resource_start (pci_dev, 1);
2606 card->ac97base = pci_resource_start (pci_dev, 0);
2607 card->pci_dev = pci_dev;
2608 card->pci_id = pci_id->device;
2609 card->irq = pci_dev->irq;
2610 card->next = devs;
2611 card->magic = I810_CARD_MAGIC;
2612 spin_lock_init(&card->lock);
2613 devs = card;
2614
2615 pci_set_master(pci_dev);
2616
2617 printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, IRQ %d\n",
2618 card_names[pci_id->driver_data], card->iobase, card->ac97base,
2619 card->irq);
2620
2621 card->alloc_pcm_channel = i810_alloc_pcm_channel;
2622 card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel;
2623 card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel;
2624 card->free_pcm_channel = i810_free_pcm_channel;
2625 card->channel[0].offset = 0;
2626 card->channel[0].port = 0x00;
2627 card->channel[0].num=0;
2628 card->channel[1].offset = 0;
2629 card->channel[1].port = 0x10;
2630 card->channel[1].num=1;
2631 card->channel[2].offset = 0;
2632 card->channel[2].port = 0x20;
2633 card->channel[2].num=2;
2634
2635 /* claim our iospace and irq */
2636 request_region(card->iobase, 64, card_names[pci_id->driver_data]);
2637 request_region(card->ac97base, 256, card_names[pci_id->driver_data]);
2638
2639 if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ,
2640 card_names[pci_id->driver_data], card)) {
2641 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq);
2642 release_region(card->iobase, 64);
2643 release_region(card->ac97base, 256);
2644 kfree(card);
2645 return -ENODEV;
2646 }
2647
2648 /* initialize AC97 codec and register /dev/mixer */
2649 if (i810_ac97_init(card) <= 0) {
2650 release_region(card->iobase, 64);
2651 release_region(card->ac97base, 256);
2652 free_irq(card->irq, card);
2653 kfree(card);
2654 return -ENODEV;
2655 }
2656 pci_dev->driver_data = card;
2657
2658 if(clocking == 48000) {
2659 i810_configure_clocking();
2660 }
2661
2662 /* register /dev/dsp */
2663 if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) {
2664 int i;
2665 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n");
2666 release_region(card->iobase, 64);
2667 release_region(card->ac97base, 256);
2668 free_irq(card->irq, card);
2669 for (i = 0; i < NR_AC97; i++)
2670 if (card->ac97_codec[i] != NULL) {
2671 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
2672 kfree (card->ac97_codec[i]);
2673 }
2674 kfree(card);
2675 return -ENODEV;
2676 }
2677
2678 return 0;
2679 }
2680
2681 static void __exit i810_remove(struct pci_dev *pci_dev)
2682 {
2683 int i;
2684 struct i810_card *card = pci_dev->driver_data;
2685 /* free hardware resources */
2686 free_irq(card->irq, devs);
2687 release_region(card->iobase, 64);
2688 release_region(card->ac97base, 256);
2689
2690 /* unregister audio devices */
2691 for (i = 0; i < NR_AC97; i++)
2692 if (card->ac97_codec[i] != NULL) {
2693 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
2694 kfree (card->ac97_codec[i]);
2695 }
2696 unregister_sound_dsp(card->dev_audio);
2697 kfree(card);
2698 }
2699
2700
2701 MODULE_AUTHOR("");
2702 MODULE_DESCRIPTION("Intel 810 audio support");
2703 MODULE_PARM(ftsodell, "i");
2704 MODULE_PARM(clocking, "i");
2705 MODULE_PARM(strict_clocking, "i");
2706 MODULE_PARM(spdif_locked, "i");
2707
2708 #define I810_MODULE_NAME "intel810_audio"
2709
2710 static struct pci_driver i810_pci_driver = {
2711 name: I810_MODULE_NAME,
2712 id_table: i810_pci_tbl,
2713 probe: i810_probe,
2714 remove: i810_remove,
2715 };
2716
2717
2718 static int __init i810_init_module (void)
2719 {
2720 if (!pci_present()) /* No PCI bus in this machine! */
2721 return -ENODEV;
2722
2723 printk(KERN_INFO "Intel 810 + AC97 Audio, version "
2724 DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
2725
2726 if (!pci_register_driver(&i810_pci_driver)) {
2727 pci_unregister_driver(&i810_pci_driver);
2728 return -ENODEV;
2729 }
2730 if(ftsodell != 0) {
2731 printk("i810_audio: ftsodell is now a deprecated option.\n");
2732 }
2733 if(clocking == 48000) {
2734 i810_configure_clocking();
2735 }
2736 if(spdif_locked > 0 ) {
2737 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) {
2738 printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked);
2739 } else {
2740 printk("i810_audio: S/PDIF can only be locked to 32000, 441000, or 48000Hz.\n");
2741 spdif_locked = 0;
2742 }
2743 }
2744
2745 return 0;
2746 }
2747
2748 static void __exit i810_cleanup_module (void)
2749 {
2750 pci_unregister_driver(&i810_pci_driver);
2751 }
2752
2753 module_init(i810_init_module);
2754 module_exit(i810_cleanup_module);
2755