File: /usr/src/linux/drivers/sound/maestro3.c
1 /*****************************************************************************
2 *
3 * ESS Maestro3/Allegro driver for Linux 2.4.x
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * (c) Copyright 2000 Zach Brown <zab@zabbo.net>
20 *
21 * I need to thank many people for helping make this driver happen.
22 * As always, Eric Brombaugh was a hacking machine and killed many bugs
23 * that I was too dumb to notice. Howard Kim at ESS provided reference boards
24 * and as much docs as he could. Todd and Mick at Dell tested snapshots on
25 * an army of laptops. msw and deviant at Red Hat also humoured me by hanging
26 * their laptops every few hours in the name of science.
27 *
28 * Shouts go out to Mike "DJ XPCom" Ang.
29 *
30 * History
31 * v1.22 - Feb 28 2001 - Zach Brown <zab@zabbo.net>
32 * allocate mem at insmod/setup, rather than open
33 * limit pci dma addresses to 28bit, thanks guys.
34 * v1.21 - Feb 04 2001 - Zach Brown <zab@zabbo.net>
35 * fix up really dumb notifier -> suspend oops
36 * v1.20 - Jan 30 2001 - Zach Brown <zab@zabbo.net>
37 * get rid of pm callback and use pci_dev suspend/resume instead
38 * m3_probe cleanups, including pm oops think-o
39 * v1.10 - Jan 6 2001 - Zach Brown <zab@zabbo.net>
40 * revert to lame remap_page_range mmap() just to make it work
41 * record mmap fixed.
42 * fix up incredibly broken open/release resource management
43 * duh. fix record format setting.
44 * add SMP locking and cleanup formatting here and there
45 * v1.00 - Dec 16 2000 - Zach Brown <zab@zabbo.net>
46 * port to sexy 2.4 interfaces
47 * properly align instance allocations so recording works
48 * clean up function namespace a little :/
49 * update PCI IDs based on mail from ESS
50 * arbitrarily bump version number to show its 2.4 now,
51 * 2.2 will stay 0., oss_audio port gets 2.
52 * v0.03 - Nov 05 2000 - Zach Brown <zab@zabbo.net>
53 * disable recording but allow dsp to be opened read
54 * pull out most silly compat defines
55 * v0.02 - Nov 04 2000 - Zach Brown <zab@zabbo.net>
56 * changed clocking setup for m3, slowdown fixed.
57 * codec reset is hopefully reliable now
58 * rudimentary apm/power management makes suspend/resume work
59 * v0.01 - Oct 31 2000 - Zach Brown <zab@zabbo.net>
60 * first release
61 * v0.00 - Sep 09 2000 - Zach Brown <zab@zabbo.net>
62 * first pass derivation from maestro.c
63 *
64 * TODO
65 * in/out allocated contiguously so fullduplex mmap will work?
66 * no beep on init (mute)
67 * resetup msrc data memory if freq changes?
68 *
69 * --
70 *
71 * Allow me to ramble a bit about the m3 architecture. The core of the
72 * chip is the 'assp', the custom ESS dsp that runs the show. It has
73 * a small amount of code and data ram. ESS drops binary dsp code images
74 * on our heads, but we don't get to see specs on the dsp.
75 *
76 * The constant piece of code on the dsp is the 'kernel'. It also has a
77 * chunk of the dsp memory that is statically set aside for its control
78 * info. This is the KDATA defines in maestro3.h. Part of its core
79 * data is a list of code addresses that point to the pieces of DSP code
80 * that it should walk through in its loop. These other pieces of code
81 * do the real work. The kernel presumably jumps into each of them in turn.
82 * These code images tend to have their own data area, and one can have
83 * multiple data areas representing different states for each of the 'client
84 * instance' code portions. There is generally a list in the kernel data
85 * that points to the data instances for a given piece of code.
86 *
87 * We've only been given the binary image for the 'minisrc', mini sample
88 * rate converter. This is rather annoying because it limits the work
89 * we can do on the dsp, but it also greatly simplifies the job of managing
90 * dsp data memory for the code and data for our playing streams :). We
91 * statically allocate the minisrc code into a region we 'know' to be free
92 * based on the map of the binary kernel image we're loading. We also
93 * statically allocate the data areas for the maximum number of pcm streams
94 * we can be dealing with. This max is set by the length of the static list
95 * in the kernel data that records the number of minisrc data regions we
96 * can have. Thats right, all software dsp mixing with static code list
97 * limits. Rock.
98 *
99 * How sound goes in and out is still a relative mystery. It appears
100 * that the dsp has the ability to get input and output through various
101 * 'connections'. To do IO from or to a connection, you put the address
102 * of the minisrc client area in the static kernel data lists for that
103 * input or output. so for pcm -> dsp -> mixer, we put the minisrc data
104 * instance in the DMA list and also in the list for the mixer. I guess
105 * it Just Knows which is in/out, and we give some dma control info that
106 * helps. There are all sorts of cool inputs/outputs that it seems we can't
107 * use without dsp code images that know how to use them.
108 *
109 * So at init time we preload all the memory allocation stuff and set some
110 * system wide parameters. When we really get a sound to play we build
111 * up its minisrc header (stream parameters, buffer addresses, input/output
112 * settings). Then we throw its header on the various lists. We also
113 * tickle some KDATA settings that ask the assp to raise clock interrupts
114 * and do some amount of software mixing before handing data to the ac97.
115 *
116 * Sorry for the vague details. Feel free to ask Eric or myself if you
117 * happen to be trying to use this driver elsewhere. Please accept my
118 * apologies for the quality of the OSS support code, its passed through
119 * too many hands now and desperately wants to be rethought.
120 */
121
122 /*****************************************************************************/
123
124 #include <linux/config.h>
125 #include <linux/module.h>
126 #include <linux/kernel.h>
127 #include <linux/string.h>
128 #include <linux/ctype.h>
129 #include <linux/ioport.h>
130 #include <linux/sched.h>
131 #include <linux/delay.h>
132 #include <linux/sound.h>
133 #include <linux/slab.h>
134 #include <linux/soundcard.h>
135 #include <linux/pci.h>
136 #include <linux/vmalloc.h>
137 #include <asm/io.h>
138 #include <asm/dma.h>
139 #include <linux/init.h>
140 #include <linux/poll.h>
141 #include <linux/reboot.h>
142 #include <asm/uaccess.h>
143 #include <asm/hardirq.h>
144 #include <linux/spinlock.h>
145 #include <linux/ac97_codec.h>
146
147 /*
148 * for crizappy mmap()
149 */
150 #include <linux/wrapper.h>
151
152 #include "maestro3.h"
153
154 #define M_DEBUG 1
155
156 #define DRIVER_VERSION "1.22"
157 #define M3_MODULE_NAME "maestro3"
158 #define PFX M3_MODULE_NAME ": "
159
160 #define M3_STATE_MAGIC 0x734d724d
161 #define M3_CARD_MAGIC 0x646e6f50
162
163 #define ESS_FMT_STEREO 0x01
164 #define ESS_FMT_16BIT 0x02
165 #define ESS_FMT_MASK 0x03
166 #define ESS_DAC_SHIFT 0
167 #define ESS_ADC_SHIFT 4
168
169 #define DAC_RUNNING 1
170 #define ADC_RUNNING 2
171
172 #define SND_DEV_DSP16 5
173
174 #ifdef M_DEBUG
175 static int debug=0;
176 #define DPMOD 1 /* per module load */
177 #define DPSTR 2 /* per 'stream' */
178 #define DPSYS 3 /* per syscall */
179 #define DPCRAP 4 /* stuff the user shouldn't see unless they're really debuggin */
180 #define DPINT 5 /* per interrupt, LOTS */
181 #define DPRINTK(DP, args...) {if (debug >= (DP)) printk(KERN_DEBUG PFX args);}
182 #else
183 #define DPRINTK(x)
184 #endif
185
186 struct m3_list {
187 int curlen;
188 u16 mem_addr;
189 int max;
190 };
191
192 int external_amp = 1;
193
194 struct m3_state {
195 unsigned int magic;
196 struct m3_card *card;
197 unsigned char fmt, enable;
198
199 int index;
200
201 /* this locks around the oss state in the driver */
202 spinlock_t lock;
203
204 struct semaphore open_sem;
205 wait_queue_head_t open_wait;
206 mode_t open_mode;
207
208 int dev_audio;
209
210 struct assp_instance {
211 u16 code, data;
212 } dac_inst, adc_inst;
213
214 /* should be in dmabuf */
215 unsigned int rateadc, ratedac;
216
217 struct dmabuf {
218 void *rawbuf;
219 unsigned buforder;
220 unsigned numfrag;
221 unsigned fragshift;
222 unsigned hwptr, swptr;
223 unsigned total_bytes;
224 int count;
225 unsigned error; /* over/underrun */
226 wait_queue_head_t wait;
227 /* redundant, but makes calculations easier */
228 unsigned fragsize;
229 unsigned dmasize;
230 unsigned fragsamples;
231 /* OSS stuff */
232 unsigned mapped:1;
233 unsigned ready:1;
234 unsigned endcleared:1;
235 unsigned ossfragshift;
236 int ossmaxfrags;
237 unsigned subdivision;
238 /* new in m3 */
239 int mixer_index, dma_index, msrc_index, adc1_index;
240 int in_lists;
241 /* 2.4.. */
242 dma_addr_t handle;
243
244 } dma_dac, dma_adc;
245 };
246
247 struct m3_card {
248 unsigned int magic;
249
250 struct m3_card *next;
251
252 struct ac97_codec *ac97;
253 spinlock_t ac97_lock;
254
255 int card_type;
256
257 #define NR_DSPS 1
258 #define MAX_DSPS NR_DSPS
259 struct m3_state channels[MAX_DSPS];
260
261 /* this locks around the physical registers on the card */
262 spinlock_t lock;
263
264 /* hardware resources */
265 struct pci_dev *pcidev;
266 u32 iobase;
267 u32 irq;
268
269 int dacs_active;
270
271 int timer_users;
272
273 struct m3_list msrc_list,
274 mixer_list,
275 adc1_list,
276 dma_list;
277
278 /* for storing reset state..*/
279 u8 reset_state;
280
281 u16 *suspend_mem;
282 int in_suspend;
283 wait_queue_head_t suspend_queue;
284 };
285
286 /*
287 * an arbitrary volume we set the internal
288 * volume settings to so that the ac97 volume
289 * range is a little less insane. 0x7fff is
290 * max.
291 */
292 #define ARB_VOLUME ( 0x6800 )
293
294 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
295
296 enum {
297 ESS_ALLEGRO,
298 ESS_MAESTRO3,
299 /*
300 * a maestro3 with 'hardware strapping', only
301 * found inside ESS?
302 */
303 ESS_MAESTRO3HW,
304 };
305
306 static char *card_names[] = {
307 [ESS_ALLEGRO] = "Allegro",
308 [ESS_MAESTRO3] = "Maestro3(i)",
309 [ESS_MAESTRO3HW] = "Maestro3(i)hw"
310 };
311
312 #ifndef PCI_VENDOR_ESS
313 #define PCI_VENDOR_ESS 0x125D
314 #endif
315
316 #define M3_DEVICE(DEV, TYPE) \
317 { \
318 vendor: PCI_VENDOR_ESS, \
319 device: DEV, \
320 subvendor: PCI_ANY_ID, \
321 subdevice: PCI_ANY_ID, \
322 class: PCI_CLASS_MULTIMEDIA_AUDIO << 8, \
323 class_mask: 0xffff << 8, \
324 driver_data: TYPE, \
325 }
326
327 static struct pci_device_id m3_id_table[] __initdata = {
328 M3_DEVICE(0x1988, ESS_ALLEGRO),
329 M3_DEVICE(0x1998, ESS_MAESTRO3),
330 M3_DEVICE(0x199a, ESS_MAESTRO3HW),
331 {0,}
332 };
333
334 MODULE_DEVICE_TABLE (pci, m3_id_table);
335
336 /*
337 * reports seem to indicate that the m3 is limited
338 * to 28bit bus addresses. aaaargggh...
339 */
340 #define M3_PCI_DMA_MASK 0x0fffffff
341
342 static unsigned
343 ld2(unsigned int x)
344 {
345 unsigned r = 0;
346
347 if (x >= 0x10000) {
348 x >>= 16;
349 r += 16;
350 }
351 if (x >= 0x100) {
352 x >>= 8;
353 r += 8;
354 }
355 if (x >= 0x10) {
356 x >>= 4;
357 r += 4;
358 }
359 if (x >= 4) {
360 x >>= 2;
361 r += 2;
362 }
363 if (x >= 2)
364 r++;
365 return r;
366 }
367
368 static struct m3_card *devs = NULL;
369
370 /*
371 * I'm not very good at laying out functions in a file :)
372 */
373 static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf);
374 static int m3_suspend(struct pci_dev *pci_dev, u32 state);
375 static void check_suspend(struct m3_card *card);
376
377 struct notifier_block m3_reboot_nb = {m3_notifier, NULL, 0};
378
379 static void m3_outw(struct m3_card *card,
380 u16 value, unsigned long reg)
381 {
382 check_suspend(card);
383 outw(value, card->iobase + reg);
384 }
385
386 static u16 m3_inw(struct m3_card *card, unsigned long reg)
387 {
388 check_suspend(card);
389 return inw(card->iobase + reg);
390 }
391 static void m3_outb(struct m3_card *card,
392 u8 value, unsigned long reg)
393 {
394 check_suspend(card);
395 outb(value, card->iobase + reg);
396 }
397 static u8 m3_inb(struct m3_card *card, unsigned long reg)
398 {
399 check_suspend(card);
400 return inb(card->iobase + reg);
401 }
402
403 /*
404 * access 16bit words to the code or data regions of the dsp's memory.
405 * index addresses 16bit words.
406 */
407 static u16 __m3_assp_read(struct m3_card *card, u16 region, u16 index)
408 {
409 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
410 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
411 return m3_inw(card, DSP_PORT_MEMORY_DATA);
412 }
413 static u16 m3_assp_read(struct m3_card *card, u16 region, u16 index)
414 {
415 unsigned long flags;
416 u16 ret;
417
418 spin_lock_irqsave(&(card->lock), flags);
419 ret = __m3_assp_read(card, region, index);
420 spin_unlock_irqrestore(&(card->lock), flags);
421
422 return ret;
423 }
424
425 static void __m3_assp_write(struct m3_card *card,
426 u16 region, u16 index, u16 data)
427 {
428 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
429 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
430 m3_outw(card, data, DSP_PORT_MEMORY_DATA);
431 }
432 static void m3_assp_write(struct m3_card *card,
433 u16 region, u16 index, u16 data)
434 {
435 unsigned long flags;
436
437 spin_lock_irqsave(&(card->lock), flags);
438 __m3_assp_write(card, region, index, data);
439 spin_unlock_irqrestore(&(card->lock), flags);
440 }
441
442 static void m3_assp_halt(struct m3_card *card)
443 {
444 card->reset_state = m3_inb(card, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
445 mdelay(10);
446 m3_outb(card, card->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
447 }
448
449 static void m3_assp_continue(struct m3_card *card)
450 {
451 m3_outb(card, card->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
452 }
453
454 /*
455 * This makes me sad. the maestro3 has lists
456 * internally that must be packed.. 0 terminates,
457 * apparently, or maybe all unused entries have
458 * to be 0, the lists have static lengths set
459 * by the binary code images.
460 */
461
462 static int m3_add_list(struct m3_card *card,
463 struct m3_list *list, u16 val)
464 {
465 DPRINTK(DPSTR, "adding val 0x%x to list 0x%p at pos %d\n",
466 val, list, list->curlen);
467
468 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
469 list->mem_addr + list->curlen,
470 val);
471
472 return list->curlen++;
473
474 }
475
476 static void m3_remove_list(struct m3_card *card,
477 struct m3_list *list, int index)
478 {
479 u16 val;
480 int lastindex = list->curlen - 1;
481
482 DPRINTK(DPSTR, "removing ind %d from list 0x%p\n",
483 index, list);
484
485 if(index != lastindex) {
486 val = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
487 list->mem_addr + lastindex);
488 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
489 list->mem_addr + index,
490 val);
491 }
492
493 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
494 list->mem_addr + lastindex,
495 0);
496
497 list->curlen--;
498 }
499
500 static void set_fmt(struct m3_state *s, unsigned char mask, unsigned char data)
501 {
502 int tmp;
503
504 s->fmt = (s->fmt & mask) | data;
505
506 tmp = (s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK;
507
508 /* write to 'mono' word */
509 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
510 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 1,
511 (tmp & ESS_FMT_STEREO) ? 0 : 1);
512 /* write to '8bit' word */
513 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
514 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 2,
515 (tmp & ESS_FMT_16BIT) ? 0 : 1);
516
517 tmp = (s->fmt >> ESS_ADC_SHIFT) & ESS_FMT_MASK;
518
519 /* write to 'mono' word */
520 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
521 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 1,
522 (tmp & ESS_FMT_STEREO) ? 0 : 1);
523 /* write to '8bit' word */
524 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
525 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 2,
526 (tmp & ESS_FMT_16BIT) ? 0 : 1);
527 }
528
529 static void set_dac_rate(struct m3_state *s, unsigned int rate)
530 {
531 u32 freq;
532
533 if (rate > 48000)
534 rate = 48000;
535 if (rate < 8000)
536 rate = 8000;
537
538 s->ratedac = rate;
539
540 freq = ((rate << 15) + 24000 ) / 48000;
541 if(freq)
542 freq--;
543
544 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
545 s->dac_inst.data + CDATA_FREQUENCY,
546 freq);
547 }
548
549 static void set_adc_rate(struct m3_state *s, unsigned int rate)
550 {
551 u32 freq;
552
553 if (rate > 48000)
554 rate = 48000;
555 if (rate < 8000)
556 rate = 8000;
557
558 s->rateadc = rate;
559
560 freq = ((rate << 15) + 24000 ) / 48000;
561 if(freq)
562 freq--;
563
564 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
565 s->adc_inst.data + CDATA_FREQUENCY,
566 freq);
567 }
568
569 static void inc_timer_users(struct m3_card *card)
570 {
571 unsigned long flags;
572
573 spin_lock_irqsave(&card->lock, flags);
574
575 card->timer_users++;
576 DPRINTK(DPSYS, "inc timer users now %d\n",
577 card->timer_users);
578 if(card->timer_users != 1)
579 goto out;
580
581 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
582 KDATA_TIMER_COUNT_RELOAD,
583 240 ) ;
584
585 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
586 KDATA_TIMER_COUNT_CURRENT,
587 240 ) ;
588
589 m3_outw(card,
590 m3_inw(card, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
591 HOST_INT_CTRL);
592 out:
593 spin_unlock_irqrestore(&card->lock, flags);
594 }
595
596 static void dec_timer_users(struct m3_card *card)
597 {
598 unsigned long flags;
599
600 spin_lock_irqsave(&card->lock, flags);
601
602 card->timer_users--;
603 DPRINTK(DPSYS, "dec timer users now %d\n",
604 card->timer_users);
605 if(card->timer_users > 0 )
606 goto out;
607
608 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
609 KDATA_TIMER_COUNT_RELOAD,
610 0 ) ;
611
612 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
613 KDATA_TIMER_COUNT_CURRENT,
614 0 ) ;
615
616 m3_outw(card, m3_inw(card, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
617 HOST_INT_CTRL);
618 out:
619 spin_unlock_irqrestore(&card->lock, flags);
620 }
621
622 /*
623 * {start,stop}_{adc,dac} should be called
624 * while holding the 'state' lock and they
625 * will try to grab the 'card' lock..
626 */
627 static void stop_adc(struct m3_state *s)
628 {
629 if (! (s->enable & ADC_RUNNING))
630 return;
631
632 s->enable &= ~ADC_RUNNING;
633 dec_timer_users(s->card);
634
635 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
636 s->adc_inst.data + CDATA_INSTANCE_READY, 0);
637
638 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
639 KDATA_ADC1_REQUEST, 0);
640 }
641
642 static void stop_dac(struct m3_state *s)
643 {
644 if (! (s->enable & DAC_RUNNING))
645 return;
646
647 DPRINTK(DPSYS, "stop_dac()\n");
648
649 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
650 s->dac_inst.data + CDATA_INSTANCE_READY, 0);
651
652 s->enable &= ~DAC_RUNNING;
653 s->card->dacs_active--;
654 dec_timer_users(s->card);
655
656 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
657 KDATA_MIXER_TASK_NUMBER,
658 s->card->dacs_active ) ;
659 }
660
661 static void start_dac(struct m3_state *s)
662 {
663 if( (!s->dma_dac.mapped && s->dma_dac.count < 1) ||
664 !s->dma_dac.ready ||
665 (s->enable & DAC_RUNNING))
666 return;
667
668 DPRINTK(DPSYS, "start_dac()\n");
669
670 s->enable |= DAC_RUNNING;
671 s->card->dacs_active++;
672 inc_timer_users(s->card);
673
674 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
675 s->dac_inst.data + CDATA_INSTANCE_READY, 1);
676
677 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
678 KDATA_MIXER_TASK_NUMBER,
679 s->card->dacs_active ) ;
680 }
681
682 static void start_adc(struct m3_state *s)
683 {
684 if ((! s->dma_adc.mapped &&
685 s->dma_adc.count >= (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
686 || !s->dma_adc.ready
687 || (s->enable & ADC_RUNNING) )
688 return;
689
690 DPRINTK(DPSYS, "start_adc()\n");
691
692 s->enable |= ADC_RUNNING;
693 inc_timer_users(s->card);
694
695 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
696 KDATA_ADC1_REQUEST, 1);
697
698 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
699 s->adc_inst.data + CDATA_INSTANCE_READY, 1);
700 }
701
702 static struct play_vals {
703 u16 addr, val;
704 } pv[] = {
705 {CDATA_LEFT_VOLUME, ARB_VOLUME},
706 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
707 {SRC3_DIRECTION_OFFSET, 0} ,
708 /* +1, +2 are stereo/16 bit */
709 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
710 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
711 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
712 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
713 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
714 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
715 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
716 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
717 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
718 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
719 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
720 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
721 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
722 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
723 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
724 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
725 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
726 };
727
728
729 /* the mode passed should be already shifted and masked */
730 static void m3_play_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
731 {
732 int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
733 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
734 int dsp_in_buffer = s->dac_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
735 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
736 struct dmabuf *db = &s->dma_dac;
737 int i;
738
739 DPRINTK(DPSTR, "mode=%d rate=%d buf=%p len=%d.\n",
740 mode, rate, buffer, size);
741
742 #define LO(x) ((x) & 0xffff)
743 #define HI(x) LO((x) >> 16)
744
745 /* host dma buffer pointers */
746
747 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
748 s->dac_inst.data + CDATA_HOST_SRC_ADDRL,
749 LO(virt_to_bus(buffer)));
750
751 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
752 s->dac_inst.data + CDATA_HOST_SRC_ADDRH,
753 HI(virt_to_bus(buffer)));
754
755 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
756 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
757 LO(virt_to_bus(buffer) + size));
758
759 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
760 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
761 HI(virt_to_bus(buffer) + size));
762
763 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
764 s->dac_inst.data + CDATA_HOST_SRC_CURRENTL,
765 LO(virt_to_bus(buffer)));
766
767 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
768 s->dac_inst.data + CDATA_HOST_SRC_CURRENTH,
769 HI(virt_to_bus(buffer)));
770 #undef LO
771 #undef HI
772
773 /* dsp buffers */
774
775 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
776 s->dac_inst.data + CDATA_IN_BUF_BEGIN,
777 dsp_in_buffer);
778
779 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
780 s->dac_inst.data + CDATA_IN_BUF_END_PLUS_1,
781 dsp_in_buffer + (dsp_in_size / 2));
782
783 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
784 s->dac_inst.data + CDATA_IN_BUF_HEAD,
785 dsp_in_buffer);
786
787 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
788 s->dac_inst.data + CDATA_IN_BUF_TAIL,
789 dsp_in_buffer);
790
791 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
792 s->dac_inst.data + CDATA_OUT_BUF_BEGIN,
793 dsp_out_buffer);
794
795 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
796 s->dac_inst.data + CDATA_OUT_BUF_END_PLUS_1,
797 dsp_out_buffer + (dsp_out_size / 2));
798
799 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
800 s->dac_inst.data + CDATA_OUT_BUF_HEAD,
801 dsp_out_buffer);
802
803 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
804 s->dac_inst.data + CDATA_OUT_BUF_TAIL,
805 dsp_out_buffer);
806
807 /*
808 * some per client initializers
809 */
810
811 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
812 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 12,
813 s->dac_inst.data + 40 + 8);
814
815 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
816 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 19,
817 s->dac_inst.code + MINISRC_COEF_LOC);
818
819 /* enable or disable low pass filter? */
820 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
821 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 22,
822 s->ratedac > 45000 ? 0xff : 0 );
823
824 /* tell it which way dma is going? */
825 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
826 s->dac_inst.data + CDATA_DMA_CONTROL,
827 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
828
829 /*
830 * set an armload of static initializers
831 */
832 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++)
833 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
834 s->dac_inst.data + pv[i].addr, pv[i].val);
835
836 /*
837 * put us in the lists if we're not already there
838 */
839
840 if(db->in_lists == 0) {
841
842 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
843 s->dac_inst.data >> DP_SHIFT_COUNT);
844
845 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
846 s->dac_inst.data >> DP_SHIFT_COUNT);
847
848 db->mixer_index = m3_add_list(s->card, &s->card->mixer_list,
849 s->dac_inst.data >> DP_SHIFT_COUNT);
850
851 db->in_lists = 1;
852 }
853
854 set_dac_rate(s,rate);
855 start_dac(s);
856 }
857
858 /*
859 * Native record driver
860 */
861 static struct rec_vals {
862 u16 addr, val;
863 } rv[] = {
864 {CDATA_LEFT_VOLUME, ARB_VOLUME},
865 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
866 {SRC3_DIRECTION_OFFSET, 1} ,
867 /* +1, +2 are stereo/16 bit */
868 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
869 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
870 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
871 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
872 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
873 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
874 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
875 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
876 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
877 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
878 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
879 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
880 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
881 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
882 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
883 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
884 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
885 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
886 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
887 };
888
889 /* again, passed mode is alrady shifted/masked */
890 static void m3_rec_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
891 {
892 int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
893 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
894 int dsp_in_buffer = s->adc_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
895 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
896 struct dmabuf *db = &s->dma_adc;
897 int i;
898
899 DPRINTK(DPSTR, "rec_setup mode=%d rate=%d buf=%p len=%d.\n",
900 mode, rate, buffer, size);
901
902 #define LO(x) ((x) & 0xffff)
903 #define HI(x) LO((x) >> 16)
904
905 /* host dma buffer pointers */
906
907 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
908 s->adc_inst.data + CDATA_HOST_SRC_ADDRL,
909 LO(virt_to_bus(buffer)));
910
911 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
912 s->adc_inst.data + CDATA_HOST_SRC_ADDRH,
913 HI(virt_to_bus(buffer)));
914
915 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
916 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
917 LO(virt_to_bus(buffer) + size));
918
919 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
920 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
921 HI(virt_to_bus(buffer) + size));
922
923 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
924 s->adc_inst.data + CDATA_HOST_SRC_CURRENTL,
925 LO(virt_to_bus(buffer)));
926
927 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
928 s->adc_inst.data + CDATA_HOST_SRC_CURRENTH,
929 HI(virt_to_bus(buffer)));
930 #undef LO
931 #undef HI
932
933 /* dsp buffers */
934
935 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
936 s->adc_inst.data + CDATA_IN_BUF_BEGIN,
937 dsp_in_buffer);
938
939 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
940 s->adc_inst.data + CDATA_IN_BUF_END_PLUS_1,
941 dsp_in_buffer + (dsp_in_size / 2));
942
943 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
944 s->adc_inst.data + CDATA_IN_BUF_HEAD,
945 dsp_in_buffer);
946
947 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
948 s->adc_inst.data + CDATA_IN_BUF_TAIL,
949 dsp_in_buffer);
950
951 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
952 s->adc_inst.data + CDATA_OUT_BUF_BEGIN,
953 dsp_out_buffer);
954
955 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
956 s->adc_inst.data + CDATA_OUT_BUF_END_PLUS_1,
957 dsp_out_buffer + (dsp_out_size / 2));
958
959 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
960 s->adc_inst.data + CDATA_OUT_BUF_HEAD,
961 dsp_out_buffer);
962
963 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
964 s->adc_inst.data + CDATA_OUT_BUF_TAIL,
965 dsp_out_buffer);
966
967 /*
968 * some per client initializers
969 */
970
971 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
972 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 12,
973 s->adc_inst.data + 40 + 8);
974
975 /* tell it which way dma is going? */
976 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
977 s->adc_inst.data + CDATA_DMA_CONTROL,
978 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
979 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
980
981 /*
982 * set an armload of static initializers
983 */
984 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++)
985 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
986 s->adc_inst.data + rv[i].addr, rv[i].val);
987
988 /*
989 * put us in the lists if we're not already there
990 */
991
992 if(db->in_lists == 0) {
993
994 db->adc1_index = m3_add_list(s->card, &s->card->adc1_list,
995 s->adc_inst.data >> DP_SHIFT_COUNT);
996
997 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
998 s->adc_inst.data >> DP_SHIFT_COUNT);
999
1000 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
1001 s->adc_inst.data >> DP_SHIFT_COUNT);
1002
1003 db->in_lists = 1;
1004 }
1005
1006 set_adc_rate(s,rate);
1007 start_adc(s);
1008 }
1009 /* --------------------------------------------------------------------- */
1010
1011 static void set_dmaa(struct m3_state *s, unsigned int addr, unsigned int count)
1012 {
1013 DPRINTK(DPINT,"set_dmaa??\n");
1014 }
1015
1016 static void set_dmac(struct m3_state *s, unsigned int addr, unsigned int count)
1017 {
1018 DPRINTK(DPINT,"set_dmac??\n");
1019 }
1020
1021 u32 get_dma_pos(struct m3_card *card,
1022 int instance_addr)
1023 {
1024 u16 hi = 0, lo = 0;
1025 int retry = 10;
1026
1027 /*
1028 * try and get a valid answer
1029 */
1030 while(retry--) {
1031 hi = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1032 instance_addr + CDATA_HOST_SRC_CURRENTH);
1033
1034 lo = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1035 instance_addr + CDATA_HOST_SRC_CURRENTL);
1036
1037 if(hi == m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1038 instance_addr + CDATA_HOST_SRC_CURRENTH))
1039 break;
1040 }
1041 return lo | (hi<<16);
1042 }
1043
1044 u32 get_dmaa(struct m3_state *s)
1045 {
1046 u32 offset;
1047
1048 offset = get_dma_pos(s->card, s->dac_inst.data) -
1049 virt_to_bus(s->dma_dac.rawbuf);
1050
1051 DPRINTK(DPINT,"get_dmaa: 0x%08x\n",offset);
1052
1053 return offset;
1054 }
1055
1056 u32 get_dmac(struct m3_state *s)
1057 {
1058 u32 offset;
1059
1060 offset = get_dma_pos(s->card, s->adc_inst.data) -
1061 virt_to_bus(s->dma_adc.rawbuf);
1062
1063 DPRINTK(DPINT,"get_dmac: 0x%08x\n",offset);
1064
1065 return offset;
1066
1067 }
1068
1069 static void m3_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1070
1071 static int
1072 prog_dmabuf(struct m3_state *s, unsigned rec)
1073 {
1074 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1075 unsigned rate = rec ? s->rateadc : s->ratedac;
1076 unsigned bytepersec;
1077 unsigned bufs;
1078 unsigned char fmt;
1079 unsigned long flags;
1080
1081 spin_lock_irqsave(&s->lock, flags);
1082
1083 fmt = s->fmt;
1084 if (rec) {
1085 stop_adc(s);
1086 fmt >>= ESS_ADC_SHIFT;
1087 } else {
1088 stop_dac(s);
1089 fmt >>= ESS_DAC_SHIFT;
1090 }
1091 fmt &= ESS_FMT_MASK;
1092
1093 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1094
1095 bytepersec = rate << sample_shift[fmt];
1096 bufs = PAGE_SIZE << db->buforder;
1097 if (db->ossfragshift) {
1098 if ((1000 << db->ossfragshift) < bytepersec)
1099 db->fragshift = ld2(bytepersec/1000);
1100 else
1101 db->fragshift = db->ossfragshift;
1102 } else {
1103 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1104 if (db->fragshift < 3)
1105 db->fragshift = 3;
1106 }
1107 db->numfrag = bufs >> db->fragshift;
1108 while (db->numfrag < 4 && db->fragshift > 3) {
1109 db->fragshift--;
1110 db->numfrag = bufs >> db->fragshift;
1111 }
1112 db->fragsize = 1 << db->fragshift;
1113 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1114 db->numfrag = db->ossmaxfrags;
1115 db->fragsamples = db->fragsize >> sample_shift[fmt];
1116 db->dmasize = db->numfrag << db->fragshift;
1117
1118 DPRINTK(DPSTR,"prog_dmabuf: numfrag: %d fragsize: %d dmasize: %d\n",db->numfrag,db->fragsize,db->dmasize);
1119
1120 memset(db->rawbuf, (fmt & ESS_FMT_16BIT) ? 0 : 0x80, db->dmasize);
1121
1122 if (rec)
1123 m3_rec_setup(s, fmt, s->rateadc, db->rawbuf, db->dmasize);
1124 else
1125 m3_play_setup(s, fmt, s->ratedac, db->rawbuf, db->dmasize);
1126
1127 db->ready = 1;
1128
1129 spin_unlock_irqrestore(&s->lock, flags);
1130
1131 return 0;
1132 }
1133
1134 static void clear_advance(struct m3_state *s)
1135 {
1136 unsigned char c = ((s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_16BIT) ? 0 : 0x80;
1137
1138 unsigned char *buf = s->dma_dac.rawbuf;
1139 unsigned bsize = s->dma_dac.dmasize;
1140 unsigned bptr = s->dma_dac.swptr;
1141 unsigned len = s->dma_dac.fragsize;
1142
1143 if (bptr + len > bsize) {
1144 unsigned x = bsize - bptr;
1145 memset(buf + bptr, c, x);
1146 /* account for wrapping? */
1147 bptr = 0;
1148 len -= x;
1149 }
1150 memset(buf + bptr, c, len);
1151 }
1152
1153 /* call with spinlock held! */
1154 static void m3_update_ptr(struct m3_state *s)
1155 {
1156 unsigned hwptr;
1157 int diff;
1158
1159 /* update ADC pointer */
1160 if (s->dma_adc.ready) {
1161 hwptr = get_dmac(s) % s->dma_adc.dmasize;
1162 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1163 s->dma_adc.hwptr = hwptr;
1164 s->dma_adc.total_bytes += diff;
1165 s->dma_adc.count += diff;
1166 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1167 wake_up(&s->dma_adc.wait);
1168 if (!s->dma_adc.mapped) {
1169 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1170 stop_adc(s);
1171 /* brute force everyone back in sync, sigh */
1172 s->dma_adc.count = 0;
1173 s->dma_adc.swptr = 0;
1174 s->dma_adc.hwptr = 0;
1175 s->dma_adc.error++;
1176 }
1177 }
1178 }
1179 /* update DAC pointer */
1180 if (s->dma_dac.ready) {
1181 hwptr = get_dmaa(s) % s->dma_dac.dmasize;
1182 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1183
1184 DPRINTK(DPINT,"updating dac: hwptr: %6d diff: %6d count: %6d\n",
1185 hwptr,diff,s->dma_dac.count);
1186
1187 s->dma_dac.hwptr = hwptr;
1188 s->dma_dac.total_bytes += diff;
1189
1190 if (s->dma_dac.mapped) {
1191
1192 s->dma_dac.count += diff;
1193 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize) {
1194 wake_up(&s->dma_dac.wait);
1195 }
1196 } else {
1197
1198 s->dma_dac.count -= diff;
1199
1200 if (s->dma_dac.count <= 0) {
1201 DPRINTK(DPCRAP,"underflow! diff: %d (0x%x) count: %d (0x%x) hw: %d (0x%x) sw: %d (0x%x)\n",
1202 diff, diff,
1203 s->dma_dac.count,
1204 s->dma_dac.count,
1205 hwptr, hwptr,
1206 s->dma_dac.swptr,
1207 s->dma_dac.swptr);
1208 stop_dac(s);
1209 /* brute force everyone back in sync, sigh */
1210 s->dma_dac.count = 0;
1211 s->dma_dac.swptr = hwptr;
1212 s->dma_dac.error++;
1213 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1214 clear_advance(s);
1215 s->dma_dac.endcleared = 1;
1216 }
1217 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize) {
1218 wake_up(&s->dma_dac.wait);
1219 DPRINTK(DPINT,"waking up DAC count: %d sw: %d hw: %d\n",
1220 s->dma_dac.count, s->dma_dac.swptr, hwptr);
1221 }
1222 }
1223 }
1224 }
1225
1226 static void m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1227 {
1228 struct m3_card *c = (struct m3_card *)dev_id;
1229 struct m3_state *s = &c->channels[0];
1230 u8 status;
1231
1232 status = inb(c->iobase+0x1A);
1233
1234 if(status == 0xff) return;
1235
1236 /* presumably acking the ints? */
1237 outw(status, c->iobase+0x1A);
1238
1239 if(c->in_suspend)
1240 return;
1241
1242 /*
1243 * ack an assp int if its running
1244 * and has an int pending
1245 */
1246 if( status & ASSP_INT_PENDING) {
1247 u8 ctl = inb(c->iobase + ASSP_CONTROL_B);
1248 if( !(ctl & STOP_ASSP_CLOCK)) {
1249 ctl = inb(c->iobase + ASSP_HOST_INT_STATUS );
1250 if(ctl & DSP2HOST_REQ_TIMER) {
1251 outb( DSP2HOST_REQ_TIMER, c->iobase + ASSP_HOST_INT_STATUS);
1252 /* update adc/dac info if it was a timer int */
1253 spin_lock(&s->lock);
1254 m3_update_ptr(s);
1255 spin_unlock(&s->lock);
1256 }
1257 }
1258 }
1259
1260 /* XXX is this needed? */
1261 if(status & 0x40)
1262 outb(0x40, c->iobase+0x1A);
1263 }
1264
1265
1266 /* --------------------------------------------------------------------- */
1267
1268 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value in %s\n";
1269
1270 #define VALIDATE_MAGIC(FOO,MAG) \
1271 ({ \
1272 if (!(FOO) || (FOO)->magic != MAG) { \
1273 printk(invalid_magic,__FUNCTION__); \
1274 return -ENXIO; \
1275 } \
1276 })
1277
1278 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,M3_STATE_MAGIC)
1279 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,M3_CARD_MAGIC)
1280
1281 /* --------------------------------------------------------------------- */
1282
1283 static int drain_dac(struct m3_state *s, int nonblock)
1284 {
1285 DECLARE_WAITQUEUE(wait,current);
1286 unsigned long flags;
1287 int count;
1288 signed long tmo;
1289
1290 if (s->dma_dac.mapped || !s->dma_dac.ready)
1291 return 0;
1292 current->state = TASK_INTERRUPTIBLE;
1293 add_wait_queue(&s->dma_dac.wait, &wait);
1294 for (;;) {
1295 spin_lock_irqsave(&s->lock, flags);
1296 count = s->dma_dac.count;
1297 spin_unlock_irqrestore(&s->lock, flags);
1298 if (count <= 0)
1299 break;
1300 if (signal_pending(current))
1301 break;
1302 if (nonblock) {
1303 remove_wait_queue(&s->dma_dac.wait, &wait);
1304 current->state = TASK_RUNNING;
1305 return -EBUSY;
1306 }
1307 tmo = (count * HZ) / s->ratedac;
1308 tmo >>= sample_shift[(s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK];
1309 /* XXX this is just broken. someone is waking us up alot, or schedule_timeout is broken.
1310 or something. who cares. - zach */
1311 if (!schedule_timeout(tmo ? tmo : 1) && tmo)
1312 DPRINTK(DPCRAP,"dma timed out?? %ld\n",jiffies);
1313 }
1314 remove_wait_queue(&s->dma_dac.wait, &wait);
1315 current->state = TASK_RUNNING;
1316 if (signal_pending(current))
1317 return -ERESTARTSYS;
1318 return 0;
1319 }
1320
1321 static ssize_t m3_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1322 {
1323 struct m3_state *s = (struct m3_state *)file->private_data;
1324 ssize_t ret;
1325 unsigned long flags;
1326 unsigned swptr;
1327 int cnt;
1328
1329 VALIDATE_STATE(s);
1330 if (ppos != &file->f_pos)
1331 return -ESPIPE;
1332 if (s->dma_adc.mapped)
1333 return -ENXIO;
1334 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1335 return ret;
1336 if (!access_ok(VERIFY_WRITE, buffer, count))
1337 return -EFAULT;
1338 ret = 0;
1339
1340 spin_lock_irqsave(&s->lock, flags);
1341
1342 while (count > 0) {
1343 int timed_out;
1344
1345 swptr = s->dma_adc.swptr;
1346 cnt = s->dma_adc.dmasize-swptr;
1347 if (s->dma_adc.count < cnt)
1348 cnt = s->dma_adc.count;
1349
1350 if (cnt > count)
1351 cnt = count;
1352
1353 if (cnt <= 0) {
1354 start_adc(s);
1355 if (file->f_flags & O_NONBLOCK)
1356 {
1357 ret = ret ? ret : -EAGAIN;
1358 goto out;
1359 }
1360
1361 spin_unlock_irqrestore(&s->lock, flags);
1362 timed_out = interruptible_sleep_on_timeout(&s->dma_adc.wait, HZ) == 0;
1363 spin_lock_irqsave(&s->lock, flags);
1364
1365 if(timed_out) {
1366 printk("read: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1367 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1368 s->dma_adc.hwptr, s->dma_adc.swptr);
1369 stop_adc(s);
1370 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1371 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1372 }
1373 if (signal_pending(current))
1374 {
1375 ret = ret ? ret : -ERESTARTSYS;
1376 goto out;
1377 }
1378 continue;
1379 }
1380
1381 spin_unlock_irqrestore(&s->lock, flags);
1382 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1383 ret = ret ? ret : -EFAULT;
1384 return ret;
1385 }
1386 spin_lock_irqsave(&s->lock, flags);
1387
1388 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1389 s->dma_adc.swptr = swptr;
1390 s->dma_adc.count -= cnt;
1391 count -= cnt;
1392 buffer += cnt;
1393 ret += cnt;
1394 start_adc(s);
1395 }
1396
1397 out:
1398 spin_unlock_irqrestore(&s->lock, flags);
1399 return ret;
1400 }
1401
1402 static ssize_t m3_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1403 {
1404 struct m3_state *s = (struct m3_state *)file->private_data;
1405 ssize_t ret;
1406 unsigned long flags;
1407 unsigned swptr;
1408 int cnt;
1409
1410 VALIDATE_STATE(s);
1411 if (ppos != &file->f_pos)
1412 return -ESPIPE;
1413 if (s->dma_dac.mapped)
1414 return -ENXIO;
1415 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1416 return ret;
1417 if (!access_ok(VERIFY_READ, buffer, count))
1418 return -EFAULT;
1419 ret = 0;
1420
1421 spin_lock_irqsave(&s->lock, flags);
1422
1423 while (count > 0) {
1424 int timed_out;
1425
1426 if (s->dma_dac.count < 0) {
1427 s->dma_dac.count = 0;
1428 s->dma_dac.swptr = s->dma_dac.hwptr;
1429 }
1430 swptr = s->dma_dac.swptr;
1431
1432 cnt = s->dma_dac.dmasize-swptr;
1433
1434 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1435 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1436
1437
1438 if (cnt > count)
1439 cnt = count;
1440
1441 if (cnt <= 0) {
1442 start_dac(s);
1443 if (file->f_flags & O_NONBLOCK) {
1444 if(!ret) ret = -EAGAIN;
1445 goto out;
1446 }
1447 spin_unlock_irqrestore(&s->lock, flags);
1448 timed_out = interruptible_sleep_on_timeout(&s->dma_dac.wait, HZ) == 0;
1449 spin_lock_irqsave(&s->lock, flags);
1450 if(timed_out) {
1451 DPRINTK(DPCRAP,"write: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1452 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1453 s->dma_dac.hwptr, s->dma_dac.swptr);
1454 stop_dac(s);
1455 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1456 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1457 }
1458 if (signal_pending(current)) {
1459 if (!ret) ret = -ERESTARTSYS;
1460 goto out;
1461 }
1462 continue;
1463 }
1464 spin_unlock_irqrestore(&s->lock, flags);
1465 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1466 if (!ret) ret = -EFAULT;
1467 return ret;
1468 }
1469 spin_lock_irqsave(&s->lock, flags);
1470
1471 DPRINTK(DPSYS,"wrote %6d bytes at sw: %6d cnt: %6d while hw: %6d\n",
1472 cnt, swptr, s->dma_dac.count, s->dma_dac.hwptr);
1473
1474 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1475
1476 s->dma_dac.swptr = swptr;
1477 s->dma_dac.count += cnt;
1478 s->dma_dac.endcleared = 0;
1479 count -= cnt;
1480 buffer += cnt;
1481 ret += cnt;
1482 start_dac(s);
1483 }
1484 out:
1485 spin_unlock_irqrestore(&s->lock, flags);
1486 return ret;
1487 }
1488
1489 static unsigned int m3_poll(struct file *file, struct poll_table_struct *wait)
1490 {
1491 struct m3_state *s = (struct m3_state *)file->private_data;
1492 unsigned long flags;
1493 unsigned int mask = 0;
1494
1495 VALIDATE_STATE(s);
1496 if (file->f_mode & FMODE_WRITE)
1497 poll_wait(file, &s->dma_dac.wait, wait);
1498 if (file->f_mode & FMODE_READ)
1499 poll_wait(file, &s->dma_adc.wait, wait);
1500
1501 spin_lock_irqsave(&s->lock, flags);
1502 m3_update_ptr(s);
1503
1504 if (file->f_mode & FMODE_READ) {
1505 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1506 mask |= POLLIN | POLLRDNORM;
1507 }
1508 if (file->f_mode & FMODE_WRITE) {
1509 if (s->dma_dac.mapped) {
1510 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1511 mask |= POLLOUT | POLLWRNORM;
1512 } else {
1513 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1514 mask |= POLLOUT | POLLWRNORM;
1515 }
1516 }
1517
1518 spin_unlock_irqrestore(&s->lock, flags);
1519 return mask;
1520 }
1521
1522 static int m3_mmap(struct file *file, struct vm_area_struct *vma)
1523 {
1524 struct m3_state *s = (struct m3_state *)file->private_data;
1525 unsigned long max_size, size, start, offset;
1526 struct dmabuf *db;
1527 int ret = -EINVAL;
1528
1529 VALIDATE_STATE(s);
1530 if (vma->vm_flags & VM_WRITE) {
1531 if ((ret = prog_dmabuf(s, 0)) != 0)
1532 return ret;
1533 db = &s->dma_dac;
1534 } else
1535 if (vma->vm_flags & VM_READ) {
1536 if ((ret = prog_dmabuf(s, 1)) != 0)
1537 return ret;
1538 db = &s->dma_adc;
1539 } else
1540 return -EINVAL;
1541
1542 max_size = db->dmasize;
1543
1544 start = vma->vm_start;
1545 offset = (vma->vm_pgoff << PAGE_SHIFT);
1546 size = vma->vm_end - vma->vm_start;
1547
1548 if(size > max_size)
1549 goto out;
1550 if(offset > max_size - size)
1551 goto out;
1552
1553 /*
1554 * this will be ->nopage() once I can
1555 * ask Jeff what the hell I'm doing wrong.
1556 */
1557 ret = -EAGAIN;
1558 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
1559 goto out;
1560
1561 db->mapped = 1;
1562 ret = 0;
1563
1564 out:
1565 return ret;
1566 }
1567
1568 /*
1569 * this function is a disaster..
1570 */
1571 #define get_user_ret(x, ptr, ret) ({ if(get_user(x, ptr)) return ret; })
1572 static int m3_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1573 {
1574 struct m3_state *s = (struct m3_state *)file->private_data;
1575 unsigned long flags;
1576 audio_buf_info abinfo;
1577 count_info cinfo;
1578 int val, mapped, ret;
1579 unsigned char fmtm, fmtd;
1580
1581 VALIDATE_STATE(s);
1582
1583 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1584 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1585
1586 DPRINTK(DPSYS,"m3_ioctl: cmd %d\n", cmd);
1587
1588 switch (cmd) {
1589 case OSS_GETVERSION:
1590 return put_user(SOUND_VERSION, (int *)arg);
1591
1592 case SNDCTL_DSP_SYNC:
1593 if (file->f_mode & FMODE_WRITE)
1594 return drain_dac(s, file->f_flags & O_NONBLOCK);
1595 return 0;
1596
1597 case SNDCTL_DSP_SETDUPLEX:
1598 /* XXX fix */
1599 return 0;
1600
1601 case SNDCTL_DSP_GETCAPS:
1602 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1603
1604 case SNDCTL_DSP_RESET:
1605 spin_lock_irqsave(&s->lock, flags);
1606 if (file->f_mode & FMODE_WRITE) {
1607 stop_dac(s);
1608 synchronize_irq();
1609 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1610 }
1611 if (file->f_mode & FMODE_READ) {
1612 stop_adc(s);
1613 synchronize_irq();
1614 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1615 }
1616 spin_unlock_irqrestore(&s->lock, flags);
1617 return 0;
1618
1619 case SNDCTL_DSP_SPEED:
1620 get_user_ret(val, (int *)arg, -EFAULT);
1621 spin_lock_irqsave(&s->lock, flags);
1622 if (val >= 0) {
1623 if (file->f_mode & FMODE_READ) {
1624 stop_adc(s);
1625 s->dma_adc.ready = 0;
1626 set_adc_rate(s, val);
1627 }
1628 if (file->f_mode & FMODE_WRITE) {
1629 stop_dac(s);
1630 s->dma_dac.ready = 0;
1631 set_dac_rate(s, val);
1632 }
1633 }
1634 spin_unlock_irqrestore(&s->lock, flags);
1635 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
1636
1637 case SNDCTL_DSP_STEREO:
1638 get_user_ret(val, (int *)arg, -EFAULT);
1639 spin_lock_irqsave(&s->lock, flags);
1640 fmtd = 0;
1641 fmtm = ~0;
1642 if (file->f_mode & FMODE_READ) {
1643 stop_adc(s);
1644 s->dma_adc.ready = 0;
1645 if (val)
1646 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1647 else
1648 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1649 }
1650 if (file->f_mode & FMODE_WRITE) {
1651 stop_dac(s);
1652 s->dma_dac.ready = 0;
1653 if (val)
1654 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1655 else
1656 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1657 }
1658 set_fmt(s, fmtm, fmtd);
1659 spin_unlock_irqrestore(&s->lock, flags);
1660 return 0;
1661
1662 case SNDCTL_DSP_CHANNELS:
1663 get_user_ret(val, (int *)arg, -EFAULT);
1664 spin_lock_irqsave(&s->lock, flags);
1665 if (val != 0) {
1666 fmtd = 0;
1667 fmtm = ~0;
1668 if (file->f_mode & FMODE_READ) {
1669 stop_adc(s);
1670 s->dma_adc.ready = 0;
1671 if (val >= 2)
1672 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1673 else
1674 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1675 }
1676 if (file->f_mode & FMODE_WRITE) {
1677 stop_dac(s);
1678 s->dma_dac.ready = 0;
1679 if (val >= 2)
1680 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1681 else
1682 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1683 }
1684 set_fmt(s, fmtm, fmtd);
1685 }
1686 spin_unlock_irqrestore(&s->lock, flags);
1687 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1688 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, (int *)arg);
1689
1690 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1691 return put_user(AFMT_U8|AFMT_S16_LE, (int *)arg);
1692
1693 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1694 get_user_ret(val, (int *)arg, -EFAULT);
1695 spin_lock_irqsave(&s->lock, flags);
1696 if (val != AFMT_QUERY) {
1697 fmtd = 0;
1698 fmtm = ~0;
1699 if (file->f_mode & FMODE_READ) {
1700 stop_adc(s);
1701 s->dma_adc.ready = 0;
1702 if (val == AFMT_S16_LE)
1703 fmtd |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
1704 else
1705 fmtm &= ~(ESS_FMT_16BIT << ESS_ADC_SHIFT);
1706 }
1707 if (file->f_mode & FMODE_WRITE) {
1708 stop_dac(s);
1709 s->dma_dac.ready = 0;
1710 if (val == AFMT_S16_LE)
1711 fmtd |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
1712 else
1713 fmtm &= ~(ESS_FMT_16BIT << ESS_DAC_SHIFT);
1714 }
1715 set_fmt(s, fmtm, fmtd);
1716 }
1717 spin_unlock_irqrestore(&s->lock, flags);
1718 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ?
1719 (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1720 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ?
1721 AFMT_S16_LE :
1722 AFMT_U8,
1723 (int *)arg);
1724
1725 case SNDCTL_DSP_POST:
1726 return 0;
1727
1728 case SNDCTL_DSP_GETTRIGGER:
1729 val = 0;
1730 if ((file->f_mode & FMODE_READ) && (s->enable & ADC_RUNNING))
1731 val |= PCM_ENABLE_INPUT;
1732 if ((file->f_mode & FMODE_WRITE) && (s->enable & DAC_RUNNING))
1733 val |= PCM_ENABLE_OUTPUT;
1734 return put_user(val, (int *)arg);
1735
1736 case SNDCTL_DSP_SETTRIGGER:
1737 get_user_ret(val, (int *)arg, -EFAULT);
1738 if (file->f_mode & FMODE_READ) {
1739 if (val & PCM_ENABLE_INPUT) {
1740 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1741 return ret;
1742 start_adc(s);
1743 } else
1744 stop_adc(s);
1745 }
1746 if (file->f_mode & FMODE_WRITE) {
1747 if (val & PCM_ENABLE_OUTPUT) {
1748 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1749 return ret;
1750 start_dac(s);
1751 } else
1752 stop_dac(s);
1753 }
1754 return 0;
1755
1756 case SNDCTL_DSP_GETOSPACE:
1757 if (!(file->f_mode & FMODE_WRITE))
1758 return -EINVAL;
1759 if (!(s->enable & DAC_RUNNING) && (val = prog_dmabuf(s, 0)) != 0)
1760 return val;
1761 spin_lock_irqsave(&s->lock, flags);
1762 m3_update_ptr(s);
1763 abinfo.fragsize = s->dma_dac.fragsize;
1764 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
1765 abinfo.fragstotal = s->dma_dac.numfrag;
1766 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1767 spin_unlock_irqrestore(&s->lock, flags);
1768 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1769
1770 case SNDCTL_DSP_GETISPACE:
1771 if (!(file->f_mode & FMODE_READ))
1772 return -EINVAL;
1773 if (!(s->enable & ADC_RUNNING) && (val = prog_dmabuf(s, 1)) != 0)
1774 return val;
1775 spin_lock_irqsave(&s->lock, flags);
1776 m3_update_ptr(s);
1777 abinfo.fragsize = s->dma_adc.fragsize;
1778 abinfo.bytes = s->dma_adc.count;
1779 abinfo.fragstotal = s->dma_adc.numfrag;
1780 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1781 spin_unlock_irqrestore(&s->lock, flags);
1782 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1783
1784 case SNDCTL_DSP_NONBLOCK:
1785 file->f_flags |= O_NONBLOCK;
1786 return 0;
1787
1788 case SNDCTL_DSP_GETODELAY:
1789 if (!(file->f_mode & FMODE_WRITE))
1790 return -EINVAL;
1791 spin_lock_irqsave(&s->lock, flags);
1792 m3_update_ptr(s);
1793 val = s->dma_dac.count;
1794 spin_unlock_irqrestore(&s->lock, flags);
1795 return put_user(val, (int *)arg);
1796
1797 case SNDCTL_DSP_GETIPTR:
1798 if (!(file->f_mode & FMODE_READ))
1799 return -EINVAL;
1800 spin_lock_irqsave(&s->lock, flags);
1801 m3_update_ptr(s);
1802 cinfo.bytes = s->dma_adc.total_bytes;
1803 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1804 cinfo.ptr = s->dma_adc.hwptr;
1805 if (s->dma_adc.mapped)
1806 s->dma_adc.count &= s->dma_adc.fragsize-1;
1807 spin_unlock_irqrestore(&s->lock, flags);
1808 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1809
1810 case SNDCTL_DSP_GETOPTR:
1811 if (!(file->f_mode & FMODE_WRITE))
1812 return -EINVAL;
1813 spin_lock_irqsave(&s->lock, flags);
1814 m3_update_ptr(s);
1815 cinfo.bytes = s->dma_dac.total_bytes;
1816 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
1817 cinfo.ptr = s->dma_dac.hwptr;
1818 if (s->dma_dac.mapped)
1819 s->dma_dac.count &= s->dma_dac.fragsize-1;
1820 spin_unlock_irqrestore(&s->lock, flags);
1821 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1822
1823 case SNDCTL_DSP_GETBLKSIZE:
1824 if (file->f_mode & FMODE_WRITE) {
1825 if ((val = prog_dmabuf(s, 0)))
1826 return val;
1827 return put_user(s->dma_dac.fragsize, (int *)arg);
1828 }
1829 if ((val = prog_dmabuf(s, 1)))
1830 return val;
1831 return put_user(s->dma_adc.fragsize, (int *)arg);
1832
1833 case SNDCTL_DSP_SETFRAGMENT:
1834 get_user_ret(val, (int *)arg, -EFAULT);
1835 spin_lock_irqsave(&s->lock, flags);
1836 if (file->f_mode & FMODE_READ) {
1837 s->dma_adc.ossfragshift = val & 0xffff;
1838 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1839 if (s->dma_adc.ossfragshift < 4)
1840 s->dma_adc.ossfragshift = 4;
1841 if (s->dma_adc.ossfragshift > 15)
1842 s->dma_adc.ossfragshift = 15;
1843 if (s->dma_adc.ossmaxfrags < 4)
1844 s->dma_adc.ossmaxfrags = 4;
1845 }
1846 if (file->f_mode & FMODE_WRITE) {
1847 s->dma_dac.ossfragshift = val & 0xffff;
1848 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1849 if (s->dma_dac.ossfragshift < 4)
1850 s->dma_dac.ossfragshift = 4;
1851 if (s->dma_dac.ossfragshift > 15)
1852 s->dma_dac.ossfragshift = 15;
1853 if (s->dma_dac.ossmaxfrags < 4)
1854 s->dma_dac.ossmaxfrags = 4;
1855 }
1856 spin_unlock_irqrestore(&s->lock, flags);
1857 return 0;
1858
1859 case SNDCTL_DSP_SUBDIVIDE:
1860 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1861 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1862 return -EINVAL;
1863 get_user_ret(val, (int *)arg, -EFAULT);
1864 if (val != 1 && val != 2 && val != 4)
1865 return -EINVAL;
1866 if (file->f_mode & FMODE_READ)
1867 s->dma_adc.subdivision = val;
1868 if (file->f_mode & FMODE_WRITE)
1869 s->dma_dac.subdivision = val;
1870 return 0;
1871
1872 case SOUND_PCM_READ_RATE:
1873 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
1874
1875 case SOUND_PCM_READ_CHANNELS:
1876 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1877 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, (int *)arg);
1878
1879 case SOUND_PCM_READ_BITS:
1880 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1881 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ? 16 : 8, (int *)arg);
1882
1883 case SOUND_PCM_WRITE_FILTER:
1884 case SNDCTL_DSP_SETSYNCRO:
1885 case SOUND_PCM_READ_FILTER:
1886 return -EINVAL;
1887
1888 }
1889 return -EINVAL;
1890 }
1891
1892 static int
1893 allocate_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1894 {
1895 int order;
1896
1897 DPRINTK(DPSTR,"allocating for dmabuf %p\n", db);
1898
1899 /*
1900 * alloc as big a chunk as we can, start with
1901 * 64k 'cause we're insane. based on order cause
1902 * the amazingly complicated prog_dmabuf wants it.
1903 *
1904 * pci_alloc_sonsistent guarantees that it won't cross a natural
1905 * boundry; the m3 hardware can't have dma cross a 64k bus
1906 * address boundry.
1907 */
1908 for (order = 16-PAGE_SHIFT; order >= 1; order--) {
1909 db->rawbuf = pci_alloc_consistent(pci_dev, PAGE_SIZE << order,
1910 &(db->handle));
1911 if(db->rawbuf)
1912 break;
1913 }
1914
1915 if (!db->rawbuf)
1916 return 1;
1917
1918 DPRINTK(DPSTR,"allocated %ld (%d) bytes at %p\n",
1919 PAGE_SIZE<<order, order, db->rawbuf);
1920
1921 {
1922 struct page *page, *pend;
1923
1924 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << order) - 1);
1925 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1926 mem_map_reserve(page);
1927 }
1928
1929
1930 db->buforder = order;
1931 db->ready = 0;
1932 db->mapped = 0;
1933
1934 return 0;
1935 }
1936
1937 static void
1938 nuke_lists(struct m3_card *card, struct dmabuf *db)
1939 {
1940 m3_remove_list(card, &(card->dma_list), db->dma_index);
1941 m3_remove_list(card, &(card->msrc_list), db->msrc_index);
1942 db->in_lists = 0;
1943 }
1944
1945 static void
1946 free_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1947 {
1948 if(db->rawbuf == NULL)
1949 return;
1950
1951 DPRINTK(DPSTR,"freeing %p from dmabuf %p\n",db->rawbuf, db);
1952
1953 {
1954 struct page *page, *pend;
1955 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1956 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1957 mem_map_unreserve(page);
1958 }
1959
1960
1961 pci_free_consistent(pci_dev, PAGE_SIZE << db->buforder,
1962 db->rawbuf, db->handle);
1963
1964 db->rawbuf = NULL;
1965 db->buforder = 0;
1966 db->mapped = 0;
1967 db->ready = 0;
1968 }
1969
1970 static int m3_open(struct inode *inode, struct file *file)
1971 {
1972 int minor = MINOR(inode->i_rdev);
1973 struct m3_card *c;
1974 struct m3_state *s = NULL;
1975 int i;
1976 unsigned char fmtm = ~0, fmts = 0;
1977 unsigned long flags;
1978
1979 /*
1980 * Scan the cards and find the channel. We only
1981 * do this at open time so it is ok
1982 */
1983 for(c = devs ; c != NULL ; c = c->next) {
1984
1985 for(i=0;i<NR_DSPS;i++) {
1986
1987 if(c->channels[i].dev_audio < 0)
1988 continue;
1989 if((c->channels[i].dev_audio ^ minor) & ~0xf)
1990 continue;
1991
1992 s = &c->channels[i];
1993 break;
1994 }
1995 }
1996
1997 if (!s)
1998 return -ENODEV;
1999
2000 VALIDATE_STATE(s);
2001
2002 file->private_data = s;
2003
2004 /* wait for device to become free */
2005 down(&s->open_sem);
2006 while (s->open_mode & file->f_mode) {
2007 if (file->f_flags & O_NONBLOCK) {
2008 up(&s->open_sem);
2009 return -EWOULDBLOCK;
2010 }
2011 up(&s->open_sem);
2012 interruptible_sleep_on(&s->open_wait);
2013 if (signal_pending(current))
2014 return -ERESTARTSYS;
2015 down(&s->open_sem);
2016 }
2017
2018 spin_lock_irqsave(&s->lock, flags);
2019
2020 if (file->f_mode & FMODE_READ) {
2021 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_ADC_SHIFT);
2022 if ((minor & 0xf) == SND_DEV_DSP16)
2023 fmts |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
2024
2025 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2026 set_adc_rate(s, 8000);
2027 }
2028 if (file->f_mode & FMODE_WRITE) {
2029 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_DAC_SHIFT);
2030 if ((minor & 0xf) == SND_DEV_DSP16)
2031 fmts |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
2032
2033 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2034 set_dac_rate(s, 8000);
2035 }
2036 set_fmt(s, fmtm, fmts);
2037 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2038
2039 MOD_INC_USE_COUNT;
2040 up(&s->open_sem);
2041 spin_unlock_irqrestore(&s->lock, flags);
2042 return 0;
2043 }
2044
2045 static int m3_release(struct inode *inode, struct file *file)
2046 {
2047 struct m3_state *s = (struct m3_state *)file->private_data;
2048 unsigned long flags;
2049
2050 VALIDATE_STATE(s);
2051 if (file->f_mode & FMODE_WRITE)
2052 drain_dac(s, file->f_flags & O_NONBLOCK);
2053
2054 down(&s->open_sem);
2055 spin_lock_irqsave(&s->lock, flags);
2056
2057 if (file->f_mode & FMODE_WRITE) {
2058 stop_dac(s);
2059 if(s->dma_dac.in_lists) {
2060 m3_remove_list(s->card, &(s->card->mixer_list), s->dma_dac.mixer_index);
2061 nuke_lists(s->card, &(s->dma_dac));
2062 }
2063 }
2064 if (file->f_mode & FMODE_READ) {
2065 stop_adc(s);
2066 if(s->dma_adc.in_lists) {
2067 m3_remove_list(s->card, &(s->card->adc1_list), s->dma_adc.adc1_index);
2068 nuke_lists(s->card, &(s->dma_adc));
2069 }
2070 }
2071
2072 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
2073
2074 spin_unlock_irqrestore(&s->lock, flags);
2075 up(&s->open_sem);
2076 wake_up(&s->open_wait);
2077
2078 MOD_DEC_USE_COUNT;
2079 return 0;
2080 }
2081
2082 /*
2083 * Wait for the ac97 serial bus to be free.
2084 * return nonzero if the bus is still busy.
2085 */
2086 static int m3_ac97_wait(struct m3_card *card)
2087 {
2088 int i = 10000;
2089
2090 while( (m3_inb(card, 0x30) & 1) && i--) ;
2091
2092 return i == 0;
2093 }
2094
2095 u16 m3_ac97_read(struct ac97_codec *codec, u8 reg)
2096 {
2097 u16 ret = 0;
2098 struct m3_card *card = codec->private_data;
2099
2100 spin_lock(&card->ac97_lock);
2101
2102 if(m3_ac97_wait(card)) {
2103 printk(KERN_ERR PFX "serial bus busy reading reg 0x%x\n",reg);
2104 goto out;
2105 }
2106
2107 m3_outb(card, 0x80 | (reg & 0x7f), 0x30);
2108
2109 if(m3_ac97_wait(card)) {
2110 printk(KERN_ERR PFX "serial bus busy finishing read reg 0x%x\n",reg);
2111 goto out;
2112 }
2113
2114 ret = m3_inw(card, 0x32);
2115 DPRINTK(DPCRAP,"reading 0x%04x from 0x%02x\n",ret, reg);
2116
2117 out:
2118 spin_unlock(&card->ac97_lock);
2119 return ret;
2120 }
2121
2122 void m3_ac97_write(struct ac97_codec *codec, u8 reg, u16 val)
2123 {
2124 struct m3_card *card = codec->private_data;
2125
2126 spin_lock(&card->ac97_lock);
2127
2128 if(m3_ac97_wait(card)) {
2129 printk(KERN_ERR PFX "serial bus busy writing 0x%x to 0x%x\n",val, reg);
2130 goto out;
2131 }
2132 DPRINTK(DPCRAP,"writing 0x%04x to 0x%02x\n", val, reg);
2133
2134 m3_outw(card, val, 0x32);
2135 m3_outb(card, reg & 0x7f, 0x30);
2136 out:
2137 spin_unlock(&card->ac97_lock);
2138 }
2139 /* OSS /dev/mixer file operation methods */
2140 static int m3_open_mixdev(struct inode *inode, struct file *file)
2141 {
2142 int minor = MINOR(inode->i_rdev);
2143 struct m3_card *card = devs;
2144
2145 MOD_INC_USE_COUNT;
2146 for (card = devs; card != NULL; card = card->next) {
2147 if((card->ac97 != NULL) && (card->ac97->dev_mixer == minor))
2148 break;
2149 }
2150
2151 if (!card) {
2152 MOD_DEC_USE_COUNT;
2153 return -ENODEV;
2154 }
2155
2156 file->private_data = card->ac97;
2157
2158 return 0;
2159 }
2160
2161 static int m3_release_mixdev(struct inode *inode, struct file *file)
2162 {
2163 MOD_DEC_USE_COUNT;
2164 return 0;
2165 }
2166
2167 static int m3_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2168 unsigned long arg)
2169 {
2170 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2171
2172 return codec->mixer_ioctl(codec, cmd, arg);
2173 }
2174
2175 static struct file_operations m3_mixer_fops = {
2176 llseek: no_llseek,
2177 ioctl: m3_ioctl_mixdev,
2178 open: m3_open_mixdev,
2179 release: m3_release_mixdev,
2180 };
2181
2182 void remote_codec_config(int io, int isremote)
2183 {
2184 isremote = isremote ? 1 : 0;
2185
2186 outw( (inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2187 io + RING_BUS_CTRL_B);
2188 outw( (inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2189 io + SDO_OUT_DEST_CTRL);
2190 outw( (inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2191 io + SDO_IN_DEST_CTRL);
2192 }
2193
2194 /*
2195 * hack, returns non zero on err
2196 */
2197 static int try_read_vendor(struct m3_card *card)
2198 {
2199 u16 ret;
2200
2201 if(m3_ac97_wait(card))
2202 return 1;
2203
2204 m3_outb(card, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2205
2206 if(m3_ac97_wait(card))
2207 return 1;
2208
2209 ret = m3_inw(card, 0x32);
2210
2211 return (ret == 0) || (ret == 0xffff);
2212 }
2213
2214 static void m3_codec_reset(struct m3_card *card, int busywait)
2215 {
2216 u16 dir;
2217 int delay1 = 0, delay2 = 0, i;
2218 int io = card->iobase;
2219
2220 switch (card->card_type) {
2221 /*
2222 * the onboard codec on the allegro seems
2223 * to want to wait a very long time before
2224 * coming back to life
2225 */
2226 case ESS_ALLEGRO:
2227 delay1 = 50;
2228 delay2 = 800;
2229 break;
2230 case ESS_MAESTRO3:
2231 case ESS_MAESTRO3HW:
2232 delay1 = 20;
2233 delay2 = 500;
2234 break;
2235 }
2236
2237 for(i = 0; i < 5; i ++) {
2238 dir = inw(io + GPIO_DIRECTION);
2239 dir |= 0x10; /* assuming pci bus master? */
2240
2241 remote_codec_config(io, 0);
2242
2243 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2244 udelay(20);
2245
2246 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2247 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2248 outw(0, io + GPIO_DATA);
2249 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2250
2251 if(busywait) {
2252 mdelay(delay1);
2253 } else {
2254 current->state = TASK_UNINTERRUPTIBLE;
2255 schedule_timeout((delay1 * HZ) / 1000);
2256 }
2257
2258 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2259 udelay(5);
2260 /* ok, bring back the ac-link */
2261 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2262 outw(~0, io + GPIO_MASK);
2263
2264 if(busywait) {
2265 mdelay(delay2);
2266 } else {
2267 current->state = TASK_UNINTERRUPTIBLE;
2268 schedule_timeout((delay2 * HZ) / 1000);
2269 }
2270 if(! try_read_vendor(card))
2271 break;
2272
2273 delay1 += 10;
2274 delay2 += 100;
2275
2276 DPRINTK(DPMOD, "retrying codec reset with delays of %d and %d ms\n",
2277 delay1, delay2);
2278 }
2279
2280 #if 0
2281 /* more gung-ho reset that doesn't
2282 * seem to work anywhere :)
2283 */
2284 tmp = inw(io + RING_BUS_CTRL_A);
2285 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2286 mdelay(20);
2287 outw(tmp, io + RING_BUS_CTRL_A);
2288 mdelay(50);
2289 #endif
2290 }
2291
2292 static int __init m3_codec_install(struct m3_card *card)
2293 {
2294 struct ac97_codec *codec;
2295
2296 if ((codec = kmalloc(sizeof(struct ac97_codec), GFP_KERNEL)) == NULL)
2297 return -ENOMEM;
2298 memset(codec, 0, sizeof(struct ac97_codec));
2299
2300 codec->private_data = card;
2301 codec->codec_read = m3_ac97_read;
2302 codec->codec_write = m3_ac97_write;
2303 /* someday we should support secondary codecs.. */
2304 codec->id = 0;
2305
2306 if (ac97_probe_codec(codec) == 0) {
2307 printk(KERN_ERR PFX "codec probe failed\n");
2308 kfree(codec);
2309 return -1;
2310 }
2311
2312 if ((codec->dev_mixer = register_sound_mixer(&m3_mixer_fops, -1)) < 0) {
2313 printk(KERN_ERR PFX "couldn't register mixer!\n");
2314 kfree(codec);
2315 return -1;
2316 }
2317
2318 card->ac97 = codec;
2319
2320 return 0;
2321 }
2322
2323
2324 #define MINISRC_LPF_LEN 10
2325 static u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2326 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2327 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2328 };
2329 static void m3_assp_init(struct m3_card *card)
2330 {
2331 int i;
2332
2333 /* zero kernel data */
2334 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2335 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2336 KDATA_BASE_ADDR + i, 0);
2337
2338 /* zero mixer data? */
2339 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2340 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2341 KDATA_BASE_ADDR2 + i, 0);
2342
2343 /* init dma pointer */
2344 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2345 KDATA_CURRENT_DMA,
2346 KDATA_DMA_XFER0);
2347
2348 /* write kernel into code memory.. */
2349 for(i = 0 ; i < sizeof(assp_kernel_image) / 2; i++) {
2350 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2351 REV_B_CODE_MEMORY_BEGIN + i,
2352 assp_kernel_image[i]);
2353 }
2354
2355 /*
2356 * We only have this one client and we know that 0x400
2357 * is free in our kernel's mem map, so lets just
2358 * drop it there. It seems that the minisrc doesn't
2359 * need vectors, so we won't bother with them..
2360 */
2361 for(i = 0 ; i < sizeof(assp_minisrc_image) / 2; i++) {
2362 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2363 0x400 + i,
2364 assp_minisrc_image[i]);
2365 }
2366
2367 /*
2368 * write the coefficients for the low pass filter?
2369 */
2370 for(i = 0; i < MINISRC_LPF_LEN ; i++) {
2371 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2372 0x400 + MINISRC_COEF_LOC + i,
2373 minisrc_lpf[i]);
2374 }
2375
2376 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2377 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2378 0x8000);
2379
2380 /*
2381 * the minisrc is the only thing on
2382 * our task list..
2383 */
2384 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2385 KDATA_TASK0,
2386 0x400);
2387
2388 /*
2389 * init the mixer number..
2390 */
2391
2392 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2393 KDATA_MIXER_TASK_NUMBER,0);
2394
2395 /*
2396 * EXTREME KERNEL MASTER VOLUME
2397 */
2398 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2399 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2400 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2401 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2402
2403 card->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2404 card->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2405 card->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2406 card->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2407 card->dma_list.mem_addr = KDATA_DMA_XFER0;
2408 card->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2409 card->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2410 card->msrc_list.max = MAX_INSTANCE_MINISRC;
2411 }
2412
2413 static int setup_msrc(struct m3_card *card,
2414 struct assp_instance *inst, int index)
2415 {
2416 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2417 MINISRC_IN_BUFFER_SIZE / 2 +
2418 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2419 int address, i;
2420
2421 /*
2422 * the revb memory map has 0x1100 through 0x1c00
2423 * free.
2424 */
2425
2426 /*
2427 * align instance address to 256 bytes so that it's
2428 * shifted list address is aligned.
2429 * list address = (mem address >> 1) >> 7;
2430 */
2431 data_bytes = (data_bytes + 255) & ~255;
2432 address = 0x1100 + ((data_bytes/2) * index);
2433
2434 if((address + (data_bytes/2)) >= 0x1c00) {
2435 printk(KERN_ERR PFX "no memory for %d bytes at ind %d (addr 0x%x)\n",
2436 data_bytes, index, address);
2437 return -1;
2438 }
2439
2440 for(i = 0; i < data_bytes/2 ; i++)
2441 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2442 address + i, 0);
2443
2444 inst->code = 0x400;
2445 inst->data = address;
2446
2447 return 0;
2448 }
2449
2450 static int m3_assp_client_init(struct m3_state *s)
2451 {
2452 setup_msrc(s->card, &(s->dac_inst), s->index * 2);
2453 setup_msrc(s->card, &(s->adc_inst), (s->index * 2) + 1);
2454
2455 return 0;
2456 }
2457
2458 static void m3_amp_enable(struct m3_card *card, int enable)
2459 {
2460 /*
2461 * this works for the reference board, have to find
2462 * out about others
2463 *
2464 * this needs more magic for 4 speaker, but..
2465 */
2466 int io = card->iobase;
2467 u16 gpo, polarity_port, polarity;
2468
2469 if(!external_amp)
2470 return;
2471
2472 switch (card->card_type) {
2473 case ESS_ALLEGRO:
2474 polarity_port = 0x1800;
2475 break;
2476 default:
2477 /* presumably this is for all 'maestro3's.. */
2478 polarity_port = 0x1100;
2479 break;
2480 }
2481
2482 gpo = (polarity_port >> 8) & 0x0F;
2483 polarity = polarity_port >> 12;
2484 if ( enable )
2485 polarity = !polarity;
2486 polarity = polarity << gpo;
2487 gpo = 1 << gpo;
2488
2489 outw(~gpo , io + GPIO_MASK);
2490
2491 outw( inw(io + GPIO_DIRECTION) | gpo ,
2492 io + GPIO_DIRECTION);
2493
2494 outw( (GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity) ,
2495 io + GPIO_DATA);
2496
2497 outw(0xffff , io + GPIO_MASK);
2498 }
2499
2500 static int
2501 maestro_config(struct m3_card *card)
2502 {
2503 struct pci_dev *pcidev = card->pcidev;
2504 u32 n;
2505 u8 t; /* makes as much sense as 'n', no? */
2506
2507 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2508 n &= REDUCED_DEBOUNCE;
2509 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2510 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2511
2512 outb(RESET_ASSP, card->iobase + ASSP_CONTROL_B);
2513 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2514 n &= ~INT_CLK_SELECT;
2515 if(card->card_type >= ESS_MAESTRO3) {
2516 n &= ~INT_CLK_MULT_ENABLE;
2517 n |= INT_CLK_SRC_NOT_PCI;
2518 }
2519 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2520 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2521
2522 if(card->card_type <= ESS_ALLEGRO) {
2523 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2524 n |= IN_CLK_12MHZ_SELECT;
2525 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2526 }
2527
2528 t = inb(card->iobase + ASSP_CONTROL_A);
2529 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2530 t |= ASSP_CLK_49MHZ_SELECT;
2531 t |= ASSP_0_WS_ENABLE;
2532 outb(t, card->iobase + ASSP_CONTROL_A);
2533
2534 outb(RUN_ASSP, card->iobase + ASSP_CONTROL_B);
2535
2536 return 0;
2537 }
2538
2539 static void m3_enable_ints(struct m3_card *card)
2540 {
2541 unsigned long io = card->iobase;
2542
2543 outw(ASSP_INT_ENABLE, io + HOST_INT_CTRL);
2544 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2545 io + ASSP_CONTROL_C);
2546 }
2547
2548 static struct file_operations m3_audio_fops = {
2549 llseek: &no_llseek,
2550 read: &m3_read,
2551 write: &m3_write,
2552 poll: &m3_poll,
2553 ioctl: &m3_ioctl,
2554 mmap: &m3_mmap,
2555 open: &m3_open,
2556 release: &m3_release,
2557 };
2558
2559 #ifdef CONFIG_PM
2560 int alloc_dsp_suspendmem(struct m3_card *card)
2561 {
2562 int len = sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2563
2564 if( (card->suspend_mem = vmalloc(len)) == NULL)
2565 return 1;
2566
2567 return 0;
2568 }
2569 void free_dsp_suspendmem(struct m3_card *card)
2570 {
2571 if(card->suspend_mem)
2572 vfree(card->suspend_mem);
2573 }
2574
2575 #else
2576 #define alloc_dsp_suspendmem(args...) 0
2577 #define free_dsp_suspendmem(args...)
2578 #endif
2579
2580 /*
2581 * great day! this function is ugly as hell.
2582 */
2583 static int __init m3_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
2584 {
2585 u32 n;
2586 int i;
2587 struct m3_card *card = NULL;
2588 int ret = 0;
2589 int card_type = pci_id->driver_data;
2590
2591 DPRINTK(DPMOD, "in maestro_install\n");
2592
2593 if (pci_enable_device(pci_dev))
2594 return -EIO;
2595
2596 if (pci_set_dma_mask(pci_dev, M3_PCI_DMA_MASK)) {
2597 printk(KERN_ERR PFX "architecture does not support limiting to 28bit PCI bus addresses\n");
2598 return -ENODEV;
2599 }
2600
2601 pci_set_master(pci_dev);
2602
2603 if( (card = kmalloc(sizeof(struct m3_card), GFP_KERNEL)) == NULL) {
2604 printk(KERN_WARNING PFX "out of memory\n");
2605 return -ENOMEM;
2606 }
2607 memset(card, 0, sizeof(struct m3_card));
2608 card->pcidev = pci_dev;
2609 init_waitqueue_head(&card->suspend_queue);
2610
2611 if ( ! request_region(pci_resource_start(pci_dev, 0),
2612 pci_resource_len (pci_dev, 0), M3_MODULE_NAME)) {
2613
2614 printk(KERN_WARNING PFX "unable to reserve I/O space.\n");
2615 ret = -EBUSY;
2616 goto out;
2617 }
2618
2619 card->iobase = pci_resource_start(pci_dev, 0);
2620
2621 if(alloc_dsp_suspendmem(card)) {
2622 printk(KERN_WARNING PFX "couldn't alloc %d bytes for saving dsp state on suspend\n",
2623 REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2624 ret = -ENOMEM;
2625 goto out;
2626 }
2627
2628 card->card_type = card_type;
2629 card->irq = pci_dev->irq;
2630 card->next = devs;
2631 card->magic = M3_CARD_MAGIC;
2632 spin_lock_init(&card->lock);
2633 spin_lock_init(&card->ac97_lock);
2634 devs = card;
2635 for(i = 0; i<NR_DSPS; i++) {
2636 struct m3_state *s = &(card->channels[i]);
2637 s->dev_audio = -1;
2638 }
2639
2640 printk(KERN_INFO PFX "Configuring ESS %s found at IO 0x%04X IRQ %d\n",
2641 card_names[card->card_type], card->iobase, card->irq);
2642
2643 pci_read_config_dword(pci_dev, PCI_SUBSYSTEM_VENDOR_ID, &n);
2644 printk(KERN_INFO PFX " subvendor id: 0x%08x\n",n);
2645
2646 maestro_config(card);
2647 m3_assp_halt(card);
2648
2649 m3_codec_reset(card, 0);
2650
2651 if(m3_codec_install(card)) {
2652 ret = -EIO;
2653 goto out;
2654 }
2655
2656 m3_assp_init(card);
2657 m3_amp_enable(card, 1);
2658
2659 for(i=0;i<NR_DSPS;i++) {
2660 struct m3_state *s=&card->channels[i];
2661
2662 s->index = i;
2663
2664 s->card = card;
2665 init_waitqueue_head(&s->dma_adc.wait);
2666 init_waitqueue_head(&s->dma_dac.wait);
2667 init_waitqueue_head(&s->open_wait);
2668 spin_lock_init(&s->lock);
2669 init_MUTEX(&(s->open_sem));
2670 s->magic = M3_STATE_MAGIC;
2671
2672 m3_assp_client_init(s);
2673
2674 if(s->dma_adc.ready || s->dma_dac.ready || s->dma_adc.rawbuf)
2675 printk(KERN_WARNING PFX "initing a dsp device that is already in use?\n");
2676 /* register devices */
2677 if ((s->dev_audio = register_sound_dsp(&m3_audio_fops, -1)) < 0) {
2678 break;
2679 }
2680
2681 if( allocate_dmabuf(card->pcidev, &(s->dma_adc)) ||
2682 allocate_dmabuf(card->pcidev, &(s->dma_dac))) {
2683 ret = -ENOMEM;
2684 goto out;
2685 }
2686 }
2687
2688 if(request_irq(card->irq, m3_interrupt, SA_SHIRQ, card_names[card->card_type], card)) {
2689
2690 printk(KERN_ERR PFX "unable to allocate irq %d,\n", card->irq);
2691
2692 ret = -EIO;
2693 goto out;
2694 }
2695
2696 pci_dev->driver_data = card;
2697
2698 m3_enable_ints(card);
2699 m3_assp_continue(card);
2700
2701 out:
2702 if(ret) {
2703 if(card->iobase)
2704 release_region(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
2705 free_dsp_suspendmem(card);
2706 if(card->ac97) {
2707 unregister_sound_mixer(card->ac97->dev_mixer);
2708 kfree(card->ac97);
2709 }
2710 for(i=0;i<NR_DSPS;i++)
2711 {
2712 struct m3_state *s = &card->channels[i];
2713 if(s->dev_audio != -1)
2714 unregister_sound_dsp(s->dev_audio);
2715 }
2716 kfree(card);
2717 }
2718
2719 return ret;
2720 }
2721
2722 static void m3_remove(struct pci_dev *pci_dev)
2723 {
2724 struct m3_card *card;
2725
2726 unregister_reboot_notifier(&m3_reboot_nb);
2727
2728 while ((card = devs)) {
2729 int i;
2730 devs = devs->next;
2731
2732 free_irq(card->irq, card);
2733 unregister_sound_mixer(card->ac97->dev_mixer);
2734 kfree(card->ac97);
2735
2736 for(i=0;i<NR_DSPS;i++)
2737 {
2738 struct m3_state *s = &card->channels[i];
2739 if(s->dev_audio < 0)
2740 continue;
2741
2742 unregister_sound_dsp(s->dev_audio);
2743 free_dmabuf(card->pcidev, &s->dma_adc);
2744 free_dmabuf(card->pcidev, &s->dma_dac);
2745 }
2746
2747 release_region(card->iobase, 256);
2748 free_dsp_suspendmem(card);
2749 kfree(card);
2750 }
2751 devs = NULL;
2752 }
2753
2754 /*
2755 * some bioses like the sound chip to be powered down
2756 * at shutdown. We're just calling _suspend to
2757 * achieve that..
2758 */
2759 static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf)
2760 {
2761 struct m3_card *card;
2762
2763 DPRINTK(DPMOD, "notifier suspending all cards\n");
2764
2765 for(card = devs; card != NULL; card = card->next) {
2766 if(!card->in_suspend)
2767 m3_suspend(card->pcidev, 3); /* XXX legal? */
2768 }
2769 return 0;
2770 }
2771
2772 static int m3_suspend(struct pci_dev *pci_dev, u32 state)
2773 {
2774 unsigned long flags;
2775 int i;
2776 struct m3_card *card = pci_dev->driver_data;
2777
2778 /* must be a better way.. */
2779 save_flags(flags);
2780 cli();
2781
2782 DPRINTK(DPMOD, "pm in dev %p\n",card);
2783
2784 for(i=0;i<NR_DSPS;i++) {
2785 struct m3_state *s = &card->channels[i];
2786
2787 if(s->dev_audio == -1)
2788 continue;
2789
2790 DPRINTK(DPMOD, "stop_adc/dac() device %d\n",i);
2791 stop_dac(s);
2792 stop_adc(s);
2793 }
2794
2795 mdelay(10); /* give the assp a chance to idle.. */
2796
2797 m3_assp_halt(card);
2798
2799 if(card->suspend_mem) {
2800 int index = 0;
2801
2802 DPRINTK(DPMOD, "saving code\n");
2803 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2804 card->suspend_mem[index++] =
2805 m3_assp_read(card, MEMTYPE_INTERNAL_CODE, i);
2806 DPRINTK(DPMOD, "saving data\n");
2807 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2808 card->suspend_mem[index++] =
2809 m3_assp_read(card, MEMTYPE_INTERNAL_DATA, i);
2810 }
2811
2812 DPRINTK(DPMOD, "powering down apci regs\n");
2813 m3_outw(card, 0xffff, 0x54);
2814 m3_outw(card, 0xffff, 0x56);
2815
2816 card->in_suspend = 1;
2817
2818 restore_flags(flags);
2819
2820 return 0;
2821 }
2822
2823 static int m3_resume(struct pci_dev *pci_dev)
2824 {
2825 unsigned long flags;
2826 int index;
2827 int i;
2828 struct m3_card *card = pci_dev->driver_data;
2829
2830 save_flags(flags); /* paranoia */
2831 cli();
2832 card->in_suspend = 0;
2833
2834 DPRINTK(DPMOD, "resuming\n");
2835
2836 /* first lets just bring everything back. .*/
2837
2838 DPRINTK(DPMOD, "bringing power back on card 0x%p\n",card);
2839 m3_outw(card, 0, 0x54);
2840 m3_outw(card, 0, 0x56);
2841
2842 DPRINTK(DPMOD, "restoring pci configs and reseting codec\n");
2843 maestro_config(card);
2844 m3_assp_halt(card);
2845 m3_codec_reset(card, 1);
2846
2847 DPRINTK(DPMOD, "restoring dsp code card\n");
2848 index = 0;
2849 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2850 m3_assp_write(card, MEMTYPE_INTERNAL_CODE, i,
2851 card->suspend_mem[index++]);
2852 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2853 m3_assp_write(card, MEMTYPE_INTERNAL_DATA, i,
2854 card->suspend_mem[index++]);
2855
2856 /* tell the dma engine to restart itself */
2857 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2858 KDATA_DMA_ACTIVE, 0);
2859
2860 DPRINTK(DPMOD, "resuming dsp\n");
2861 m3_assp_continue(card);
2862
2863 DPRINTK(DPMOD, "enabling ints\n");
2864 m3_enable_ints(card);
2865
2866 /* bring back the old school flavor */
2867 for(i = 0; i < SOUND_MIXER_NRDEVICES ; i++) {
2868 int state = card->ac97->mixer_state[i];
2869 if (!supported_mixer(card->ac97, i))
2870 continue;
2871
2872 card->ac97->write_mixer(card->ac97, i,
2873 state & 0xff, (state >> 8) & 0xff);
2874 }
2875
2876 m3_amp_enable(card, 1);
2877
2878 /*
2879 * now we flip on the music
2880 */
2881 for(i=0;i<NR_DSPS;i++) {
2882 struct m3_state *s = &card->channels[i];
2883 if(s->dev_audio == -1)
2884 continue;
2885 /*
2886 * db->ready makes it so these guys can be
2887 * called unconditionally..
2888 */
2889 DPRINTK(DPMOD, "turning on dacs ind %d\n",i);
2890 start_dac(s);
2891 start_adc(s);
2892 }
2893
2894 restore_flags(flags);
2895
2896 /*
2897 * all right, we think things are ready,
2898 * wake up people who were using the device
2899 * when we suspended
2900 */
2901 wake_up(&card->suspend_queue);
2902
2903 return 0;
2904 }
2905
2906 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>");
2907 MODULE_DESCRIPTION("ESS Maestro3/Allegro Driver");
2908 #ifdef M_DEBUG
2909 MODULE_PARM(debug,"i");
2910 #endif
2911 MODULE_PARM(external_amp,"i");
2912
2913 static struct pci_driver m3_pci_driver = {
2914 name: "ess_m3_audio",
2915 id_table: m3_id_table,
2916 probe: m3_probe,
2917 remove: m3_remove,
2918 suspend: m3_suspend,
2919 resume: m3_resume,
2920 };
2921
2922 static int __init m3_init_module(void)
2923 {
2924 if (!pci_present()) /* No PCI bus in this machine! */
2925 return -ENODEV;
2926
2927 printk(KERN_INFO PFX "version " DRIVER_VERSION " built at " __TIME__ " " __DATE__ "\n");
2928
2929 if (register_reboot_notifier(&m3_reboot_nb)) {
2930 printk(KERN_WARNING PFX "reboot notifier registration failed\n");
2931 return -ENODEV; /* ? */
2932 }
2933
2934 if (!pci_register_driver(&m3_pci_driver)) {
2935 pci_unregister_driver(&m3_pci_driver);
2936 unregister_reboot_notifier(&m3_reboot_nb);
2937 return -ENODEV;
2938 }
2939 return 0;
2940 }
2941
2942 static void __exit m3_cleanup_module(void)
2943 {
2944 pci_unregister_driver(&m3_pci_driver);
2945 }
2946
2947 module_init(m3_init_module);
2948 module_exit(m3_cleanup_module);
2949
2950 void check_suspend(struct m3_card *card)
2951 {
2952 DECLARE_WAITQUEUE(wait, current);
2953
2954 if(!card->in_suspend)
2955 return;
2956
2957 card->in_suspend++;
2958 add_wait_queue(&card->suspend_queue, &wait);
2959 current->state = TASK_UNINTERRUPTIBLE;
2960 schedule();
2961 remove_wait_queue(&card->suspend_queue, &wait);
2962 current->state = TASK_RUNNING;
2963 }
2964