File: /usr/src/linux/drivers/sound/vwsnd.c
1 /*
2 * Sound driver for Silicon Graphics 320 and 540 Visual Workstations'
3 * onboard audio. See notes in ../../Documentation/sound/vwsnd .
4 *
5 * Copyright 1999 Silicon Graphics, Inc. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #undef VWSND_DEBUG /* define for debugging */
23
24 /*
25 * XXX to do -
26 *
27 * External sync.
28 * Rename swbuf, hwbuf, u&i, hwptr&swptr to something rational.
29 * Bug - if select() called before read(), pcm_setup() not called.
30 * Bug - output doesn't stop soon enough if process killed.
31 */
32
33 /*
34 * Things to test -
35 *
36 * Will readv/writev work? Write a test.
37 *
38 * insmod/rmmod 100 million times.
39 *
40 * Run I/O until int ptrs wrap around (roughly 6.2 hours @ DAT
41 * rate).
42 *
43 * Concurrent threads banging on mixer simultaneously, both UP
44 * and SMP kernels. Especially, watch for thread A changing
45 * OUTSRC while thread B changes gain -- both write to the same
46 * ad1843 register.
47 *
48 * What happens if a client opens /dev/audio then forks?
49 * Do two procs have /dev/audio open? Test.
50 *
51 * Pump audio through the CD, MIC and line inputs and verify that
52 * they mix/mute into the output.
53 *
54 * Apps:
55 * amp
56 * mpg123
57 * x11amp
58 * mxv
59 * kmedia
60 * esound
61 * need more input apps
62 *
63 * Run tests while bombarding with signals. setitimer(2) will do it... */
64
65 /*
66 * This driver is organized in nine sections.
67 * The nine sections are:
68 *
69 * debug stuff
70 * low level lithium access
71 * high level lithium access
72 * AD1843 access
73 * PCM I/O
74 * audio driver
75 * mixer driver
76 * probe/attach/unload
77 * initialization and loadable kernel module interface
78 *
79 * That is roughly the order of increasing abstraction, so forward
80 * dependencies are minimal.
81 */
82
83 /*
84 * Locking Notes
85 *
86 * INC_USE_COUNT and DEC_USE_COUNT keep track of the number of
87 * open descriptors to this driver. They store it in vwsnd_use_count.
88 * The global device list, vwsnd_dev_list, is immutable when the IN_USE
89 * is true.
90 *
91 * devc->open_lock is a semaphore that is used to enforce the
92 * single reader/single writer rule for /dev/audio. The rule is
93 * that each device may have at most one reader and one writer.
94 * Open will block until the previous client has closed the
95 * device, unless O_NONBLOCK is specified.
96 *
97 * The semaphore devc->io_sema serializes PCM I/O syscalls. This
98 * is unnecessary in Linux 2.2, because the kernel lock
99 * serializes read, write, and ioctl globally, but it's there,
100 * ready for the brave, new post-kernel-lock world.
101 *
102 * Locking between interrupt and baselevel is handled by the
103 * "lock" spinlock in vwsnd_port (one lock each for read and
104 * write). Each half holds the lock just long enough to see what
105 * area it owns and update its pointers. See pcm_output() and
106 * pcm_input() for most of the gory stuff.
107 *
108 * devc->mix_sema serializes all mixer ioctls. This is also
109 * redundant because of the kernel lock.
110 *
111 * The lowest level lock is lith->lithium_lock. It is a
112 * spinlock which is held during the two-register tango of
113 * reading/writing an AD1843 register. See
114 * li_{read,write}_ad1843_reg().
115 */
116
117 /*
118 * Sample Format Notes
119 *
120 * Lithium's DMA engine has two formats: 16-bit 2's complement
121 * and 8-bit unsigned . 16-bit transfers the data unmodified, 2
122 * bytes per sample. 8-bit unsigned transfers 1 byte per sample
123 * and XORs each byte with 0x80. Lithium can input or output
124 * either mono or stereo in either format.
125 *
126 * The AD1843 has four formats: 16-bit 2's complement, 8-bit
127 * unsigned, 8-bit mu-Law and 8-bit A-Law.
128 *
129 * This driver supports five formats: AFMT_S8, AFMT_U8,
130 * AFMT_MU_LAW, AFMT_A_LAW, and AFMT_S16_LE.
131 *
132 * For AFMT_U8 output, we keep the AD1843 in 16-bit mode, and
133 * rely on Lithium's XOR to translate between U8 and S8.
134 *
135 * For AFMT_S8, AFMT_MU_LAW and AFMT_A_LAW output, we have to XOR
136 * the 0x80 bit in software to compensate for Lithium's XOR.
137 * This happens in pcm_copy_{in,out}().
138 *
139 * Changes:
140 * 11-10-2000 Bartlomiej Zolnierkiewicz <bkz@linux-ide.org>
141 * Added some __init/__exit
142 */
143
144 #include <linux/module.h>
145 #include <linux/init.h>
146
147 #include <linux/sched.h>
148 #include <linux/semaphore.h>
149 #include <linux/stddef.h>
150 #include <linux/spinlock.h>
151 #include <linux/smp_lock.h>
152 #include <asm/fixmap.h>
153 #include <asm/cobalt.h>
154 #include <asm/semaphore.h>
155
156 #include "sound_config.h"
157
158 /*****************************************************************************/
159 /* debug stuff */
160
161 #ifdef VWSND_DEBUG
162
163 #include <linux/interrupt.h> /* for in_interrupt() */
164
165 static int shut_up = 1;
166
167 /*
168 * dbgassert - called when an assertion fails.
169 */
170
171 static void dbgassert(const char *fcn, int line, const char *expr)
172 {
173 if (in_interrupt())
174 panic("ASSERTION FAILED IN INTERRUPT, %s:%s:%d %s\n",
175 __FILE__, fcn, line, expr);
176 else {
177 int x;
178 printk(KERN_ERR "ASSERTION FAILED, %s:%s:%d %s\n",
179 __FILE__, fcn, line, expr);
180 x = * (volatile int *) 0; /* force proc to exit */
181 }
182 }
183
184 /*
185 * Bunch of useful debug macros:
186 *
187 * ASSERT - print unless e nonzero (panic if in interrupt)
188 * DBGDO - include arbitrary code if debugging
189 * DBGX - debug print raw (w/o function name)
190 * DBGP - debug print w/ function name
191 * DBGE - debug print function entry
192 * DBGC - debug print function call
193 * DBGR - debug print function return
194 * DBGXV - debug print raw when verbose
195 * DBGPV - debug print when verbose
196 * DBGEV - debug print function entry when verbose
197 * DBGRV - debug print function return when verbose
198 */
199
200 #define ASSERT(e) ((e) ? (void) 0 : dbgassert(__FUNCTION__, __LINE__, #e))
201 #define DBGDO(x) x
202 #define DBGX(fmt, args...) (in_interrupt() ? 0 : printk(KERN_ERR fmt, ##args))
203 #define DBGP(fmt, args...) (DBGX(__FUNCTION__ ": " fmt, ##args))
204 #define DBGE(fmt, args...) (DBGX(__FUNCTION__ fmt, ##args))
205 #define DBGC(rtn) (DBGP("calling %s\n", rtn))
206 #define DBGR() (DBGP("returning\n"))
207 #define DBGXV(fmt, args...) (shut_up ? 0 : DBGX(fmt, ##args))
208 #define DBGPV(fmt, args...) (shut_up ? 0 : DBGP(fmt, ##args))
209 #define DBGEV(fmt, args...) (shut_up ? 0 : DBGE(fmt, ##args))
210 #define DBGCV(rtn) (shut_up ? 0 : DBGC(rtn))
211 #define DBGRV() (shut_up ? 0 : DBGR())
212
213 #else /* !VWSND_DEBUG */
214
215 #define ASSERT(e) ((void) 0)
216 #define DBGDO(x) /* don't */
217 #define DBGX(fmt, args...) ((void) 0)
218 #define DBGP(fmt, args...) ((void) 0)
219 #define DBGE(fmt, args...) ((void) 0)
220 #define DBGC(rtn) ((void) 0)
221 #define DBGR() ((void) 0)
222 #define DBGPV(fmt, args...) ((void) 0)
223 #define DBGXV(fmt, args...) ((void) 0)
224 #define DBGEV(fmt, args...) ((void) 0)
225 #define DBGCV(rtn) ((void) 0)
226 #define DBGRV() ((void) 0)
227
228 #endif /* !VWSND_DEBUG */
229
230 /*****************************************************************************/
231 /* low level lithium access */
232
233 /*
234 * We need to talk to Lithium registers on three pages. Here are
235 * the pages' offsets from the base address (0xFF001000).
236 */
237
238 enum {
239 LI_PAGE0_OFFSET = 0x01000 - 0x1000, /* FF001000 */
240 LI_PAGE1_OFFSET = 0x0F000 - 0x1000, /* FF00F000 */
241 LI_PAGE2_OFFSET = 0x10000 - 0x1000, /* FF010000 */
242 };
243
244 /* low-level lithium data */
245
246 typedef struct lithium {
247 caddr_t page0; /* virtual addresses */
248 caddr_t page1;
249 caddr_t page2;
250 spinlock_t lock; /* protects codec and UST/MSC access */
251 } lithium_t;
252
253 /*
254 * li_create initializes the lithium_t structure and sets up vm mappings
255 * to access the registers.
256 * Returns 0 on success, -errno on failure.
257 */
258
259 static int li_create(lithium_t *lith, unsigned long baseaddr)
260 {
261 static void li_destroy(lithium_t *);
262
263 lith->lock = SPIN_LOCK_UNLOCKED;
264 lith->page0 = ioremap_nocache(baseaddr + LI_PAGE0_OFFSET, PAGE_SIZE);
265 lith->page1 = ioremap_nocache(baseaddr + LI_PAGE1_OFFSET, PAGE_SIZE);
266 lith->page2 = ioremap_nocache(baseaddr + LI_PAGE2_OFFSET, PAGE_SIZE);
267 if (!lith->page0 || !lith->page1 || !lith->page2) {
268 li_destroy(lith);
269 return -ENOMEM;
270 }
271 return 0;
272 }
273
274 /*
275 * li_destroy destroys the lithium_t structure and vm mappings.
276 */
277
278 static void li_destroy(lithium_t *lith)
279 {
280 if (lith->page0) {
281 iounmap(lith->page0);
282 lith->page0 = NULL;
283 }
284 if (lith->page1) {
285 iounmap(lith->page1);
286 lith->page1 = NULL;
287 }
288 if (lith->page2) {
289 iounmap(lith->page2);
290 lith->page2 = NULL;
291 }
292 }
293
294 /*
295 * basic register accessors - read/write long/byte
296 */
297
298 static __inline__ unsigned long li_readl(lithium_t *lith, int off)
299 {
300 return * (volatile unsigned long *) (lith->page0 + off);
301 }
302
303 static __inline__ unsigned char li_readb(lithium_t *lith, int off)
304 {
305 return * (volatile unsigned char *) (lith->page0 + off);
306 }
307
308 static __inline__ void li_writel(lithium_t *lith, int off, unsigned long val)
309 {
310 * (volatile unsigned long *) (lith->page0 + off) = val;
311 }
312
313 static __inline__ void li_writeb(lithium_t *lith, int off, unsigned char val)
314 {
315 * (volatile unsigned char *) (lith->page0 + off) = val;
316 }
317
318 /*****************************************************************************/
319 /* High Level Lithium Access */
320
321 /*
322 * Lithium DMA Notes
323 *
324 * Lithium has two dedicated DMA channels for audio. They are known
325 * as comm1 and comm2 (communication areas 1 and 2). Comm1 is for
326 * input, and comm2 is for output. Each is controlled by three
327 * registers: BASE (base address), CFG (config) and CCTL
328 * (config/control).
329 *
330 * Each DMA channel points to a physically contiguous ring buffer in
331 * main memory of up to 8 Kbytes. (This driver always uses 8 Kb.)
332 * There are three pointers into the ring buffer: read, write, and
333 * trigger. The pointers are 8 bits each. Each pointer points to
334 * 32-byte "chunks" of data. The DMA engine moves 32 bytes at a time,
335 * so there is no finer-granularity control.
336 *
337 * In comm1, the hardware updates the write ptr, and software updates
338 * the read ptr. In comm2, it's the opposite: hardware updates the
339 * read ptr, and software updates the write ptr. I designate the
340 * hardware-updated ptr as the hwptr, and the software-updated ptr as
341 * the swptr.
342 *
343 * The trigger ptr and trigger mask are used to trigger interrupts.
344 * From the Lithium spec, section 5.6.8, revision of 12/15/1998:
345 *
346 * Trigger Mask Value
347 *
348 * A three bit wide field that represents a power of two mask
349 * that is used whenever the trigger pointer is compared to its
350 * respective read or write pointer. A value of zero here
351 * implies a mask of 0xFF and a value of seven implies a mask
352 * 0x01. This value can be used to sub-divide the ring buffer
353 * into pie sections so that interrupts monitor the progress of
354 * hardware from section to section.
355 *
356 * My interpretation of that is, whenever the hw ptr is updated, it is
357 * compared with the trigger ptr, and the result is masked by the
358 * trigger mask. (Actually, by the complement of the trigger mask.)
359 * If the result is zero, an interrupt is triggered. I.e., interrupt
360 * if ((hwptr & ~mask) == (trptr & ~mask)). The mask is formed from
361 * the trigger register value as mask = (1 << (8 - tmreg)) - 1.
362 *
363 * In yet different words, setting tmreg to 0 causes an interrupt after
364 * every 256 DMA chunks (8192 bytes) or once per traversal of the
365 * ring buffer. Setting it to 7 caues an interrupt every 2 DMA chunks
366 * (64 bytes) or 128 times per traversal of the ring buffer.
367 */
368
369 /* Lithium register offsets and bit definitions */
370
371 #define LI_HOST_CONTROLLER 0x000
372 # define LI_HC_RESET 0x00008000
373 # define LI_HC_LINK_ENABLE 0x00004000
374 # define LI_HC_LINK_FAILURE 0x00000004
375 # define LI_HC_LINK_CODEC 0x00000002
376 # define LI_HC_LINK_READY 0x00000001
377
378 #define LI_INTR_STATUS 0x010
379 #define LI_INTR_MASK 0x014
380 # define LI_INTR_LINK_ERR 0x00008000
381 # define LI_INTR_COMM2_TRIG 0x00000008
382 # define LI_INTR_COMM2_UNDERFLOW 0x00000004
383 # define LI_INTR_COMM1_TRIG 0x00000002
384 # define LI_INTR_COMM1_OVERFLOW 0x00000001
385
386 #define LI_CODEC_COMMAND 0x018
387 # define LI_CC_BUSY 0x00008000
388 # define LI_CC_DIR 0x00000080
389 # define LI_CC_DIR_RD LI_CC_DIR
390 # define LI_CC_DIR_WR (!LI_CC_DIR)
391 # define LI_CC_ADDR_MASK 0x0000007F
392
393 #define LI_CODEC_DATA 0x01C
394
395 #define LI_COMM1_BASE 0x100
396 #define LI_COMM1_CTL 0x104
397 # define LI_CCTL_RESET 0x80000000
398 # define LI_CCTL_SIZE 0x70000000
399 # define LI_CCTL_DMA_ENABLE 0x08000000
400 # define LI_CCTL_TMASK 0x07000000 /* trigger mask */
401 # define LI_CCTL_TPTR 0x00FF0000 /* trigger pointer */
402 # define LI_CCTL_RPTR 0x0000FF00
403 # define LI_CCTL_WPTR 0x000000FF
404 #define LI_COMM1_CFG 0x108
405 # define LI_CCFG_LOCK 0x00008000
406 # define LI_CCFG_SLOT 0x00000070
407 # define LI_CCFG_DIRECTION 0x00000008
408 # define LI_CCFG_DIR_IN (!LI_CCFG_DIRECTION)
409 # define LI_CCFG_DIR_OUT LI_CCFG_DIRECTION
410 # define LI_CCFG_MODE 0x00000004
411 # define LI_CCFG_MODE_MONO (!LI_CCFG_MODE)
412 # define LI_CCFG_MODE_STEREO LI_CCFG_MODE
413 # define LI_CCFG_FORMAT 0x00000003
414 # define LI_CCFG_FMT_8BIT 0x00000000
415 # define LI_CCFG_FMT_16BIT 0x00000001
416 #define LI_COMM2_BASE 0x10C
417 #define LI_COMM2_CTL 0x110
418 /* bit definitions are the same as LI_COMM1_CTL */
419 #define LI_COMM2_CFG 0x114
420 /* bit definitions are the same as LI_COMM1_CFG */
421
422 #define LI_UST_LOW 0x200 /* 64-bit Unadjusted System Time is */
423 #define LI_UST_HIGH 0x204 /* microseconds since boot */
424
425 #define LI_AUDIO1_UST 0x300 /* UST-MSC pairs */
426 #define LI_AUDIO1_MSC 0x304 /* MSC (Media Stream Counter) */
427 #define LI_AUDIO2_UST 0x308 /* counts samples actually */
428 #define LI_AUDIO2_MSC 0x30C /* processed as of time UST */
429
430 /*
431 * Lithium's DMA engine operates on chunks of 32 bytes. We call that
432 * a DMACHUNK.
433 */
434
435 #define DMACHUNK_SHIFT 5
436 #define DMACHUNK_SIZE (1 << DMACHUNK_SHIFT)
437 #define BYTES_TO_CHUNKS(bytes) ((bytes) >> DMACHUNK_SHIFT)
438 #define CHUNKS_TO_BYTES(chunks) ((chunks) << DMACHUNK_SHIFT)
439
440 /*
441 * Two convenient macros to shift bitfields into/out of position.
442 *
443 * Observe that (mask & -mask) is (1 << low_set_bit_of(mask)).
444 * As long as mask is constant, we trust the compiler will change the
445 * multipy and divide into shifts.
446 */
447
448 #define SHIFT_FIELD(val, mask) (((val) * ((mask) & -(mask))) & (mask))
449 #define UNSHIFT_FIELD(val, mask) (((val) & (mask)) / ((mask) & -(mask)))
450
451 /*
452 * dma_chan_desc is invariant information about a Lithium
453 * DMA channel. There are two instances, li_comm1 and li_comm2.
454 *
455 * Note that the CCTL register fields are write ptr and read ptr, but what
456 * we care about are which pointer is updated by software and which by
457 * hardware.
458 */
459
460 typedef struct dma_chan_desc {
461 int basereg;
462 int cfgreg;
463 int ctlreg;
464 int hwptrreg;
465 int swptrreg;
466 int ustreg;
467 int mscreg;
468 unsigned long swptrmask;
469 int ad1843_slot;
470 int direction; /* LI_CCTL_DIR_IN/OUT */
471 } dma_chan_desc_t;
472
473 static const dma_chan_desc_t li_comm1 = {
474 LI_COMM1_BASE, /* base register offset */
475 LI_COMM1_CFG, /* config register offset */
476 LI_COMM1_CTL, /* control register offset */
477 LI_COMM1_CTL + 0, /* hw ptr reg offset (write ptr) */
478 LI_COMM1_CTL + 1, /* sw ptr reg offset (read ptr) */
479 LI_AUDIO1_UST, /* ust reg offset */
480 LI_AUDIO1_MSC, /* msc reg offset */
481 LI_CCTL_RPTR, /* sw ptr bitmask in ctlval */
482 2, /* ad1843 serial slot */
483 LI_CCFG_DIR_IN /* direction */
484 };
485
486 static const dma_chan_desc_t li_comm2 = {
487 LI_COMM2_BASE, /* base register offset */
488 LI_COMM2_CFG, /* config register offset */
489 LI_COMM2_CTL, /* control register offset */
490 LI_COMM2_CTL + 1, /* hw ptr reg offset (read ptr) */
491 LI_COMM2_CTL + 0, /* sw ptr reg offset (writr ptr) */
492 LI_AUDIO2_UST, /* ust reg offset */
493 LI_AUDIO2_MSC, /* msc reg offset */
494 LI_CCTL_WPTR, /* sw ptr bitmask in ctlval */
495 2, /* ad1843 serial slot */
496 LI_CCFG_DIR_OUT /* direction */
497 };
498
499 /*
500 * dma_chan is variable information about a Lithium DMA channel.
501 *
502 * The desc field points to invariant information.
503 * The lith field points to a lithium_t which is passed
504 * to li_read* and li_write* to access the registers.
505 * The *val fields shadow the lithium registers' contents.
506 */
507
508 typedef struct dma_chan {
509 const dma_chan_desc_t *desc;
510 lithium_t *lith;
511 unsigned long baseval;
512 unsigned long cfgval;
513 unsigned long ctlval;
514 } dma_chan_t;
515
516 /*
517 * ustmsc is a UST/MSC pair (Unadjusted System Time/Media Stream Counter).
518 * UST is time in microseconds since the system booted, and MSC is a
519 * counter that increments with every audio sample.
520 */
521
522 typedef struct ustmsc {
523 unsigned long long ust;
524 unsigned long msc;
525 } ustmsc_t;
526
527 /*
528 * li_ad1843_wait waits until lithium says the AD1843 register
529 * exchange is not busy. Returns 0 on success, -EBUSY on timeout.
530 *
531 * Locking: must be called with lithium_lock held.
532 */
533
534 static int li_ad1843_wait(lithium_t *lith)
535 {
536 unsigned long later = jiffies + 2;
537 while (li_readl(lith, LI_CODEC_COMMAND) & LI_CC_BUSY)
538 if (jiffies >= later)
539 return -EBUSY;
540 return 0;
541 }
542
543 /*
544 * li_read_ad1843_reg returns the current contents of a 16 bit AD1843 register.
545 *
546 * Returns unsigned register value on success, -errno on failure.
547 */
548
549 static int li_read_ad1843_reg(lithium_t *lith, int reg)
550 {
551 int val;
552
553 ASSERT(!in_interrupt());
554 spin_lock(&lith->lock);
555 {
556 val = li_ad1843_wait(lith);
557 if (val == 0) {
558 li_writel(lith, LI_CODEC_COMMAND, LI_CC_DIR_RD | reg);
559 val = li_ad1843_wait(lith);
560 }
561 if (val == 0)
562 val = li_readl(lith, LI_CODEC_DATA);
563 }
564 spin_unlock(&lith->lock);
565
566 DBGXV("li_read_ad1843_reg(lith=0x%p, reg=%d) returns 0x%04x\n",
567 lith, reg, val);
568
569 return val;
570 }
571
572 /*
573 * li_write_ad1843_reg writes the specified value to a 16 bit AD1843 register.
574 */
575
576 static void li_write_ad1843_reg(lithium_t *lith, int reg, int newval)
577 {
578 spin_lock(&lith->lock);
579 {
580 if (li_ad1843_wait(lith) == 0) {
581 li_writel(lith, LI_CODEC_DATA, newval);
582 li_writel(lith, LI_CODEC_COMMAND, LI_CC_DIR_WR | reg);
583 }
584 }
585 spin_unlock(&lith->lock);
586 }
587
588 /*
589 * li_setup_dma calculates all the register settings for DMA in a particular
590 * mode. It takes too many arguments.
591 */
592
593 static void li_setup_dma(dma_chan_t *chan,
594 const dma_chan_desc_t *desc,
595 lithium_t *lith,
596 unsigned long buffer_paddr,
597 int bufshift,
598 int fragshift,
599 int channels,
600 int sampsize)
601 {
602 unsigned long mode, format;
603 unsigned long size, tmask;
604
605 DBGEV("(chan=0x%p, desc=0x%p, lith=0x%p, buffer_paddr=0x%lx, "
606 "bufshift=%d, fragshift=%d, channels=%d, sampsize=%d)\n",
607 chan, desc, lith, buffer_paddr,
608 bufshift, fragshift, channels, sampsize);
609
610 /* Reset the channel first. */
611
612 li_writel(lith, desc->ctlreg, LI_CCTL_RESET);
613
614 ASSERT(channels == 1 || channels == 2);
615 if (channels == 2)
616 mode = LI_CCFG_MODE_STEREO;
617 else
618 mode = LI_CCFG_MODE_MONO;
619 ASSERT(sampsize == 1 || sampsize == 2);
620 if (sampsize == 2)
621 format = LI_CCFG_FMT_16BIT;
622 else
623 format = LI_CCFG_FMT_8BIT;
624 chan->desc = desc;
625 chan->lith = lith;
626
627 /*
628 * Lithium DMA address register takes a 40-bit physical
629 * address, right-shifted by 8 so it fits in 32 bits. Bit 37
630 * must be set -- it enables cache coherence.
631 */
632
633 ASSERT(!(buffer_paddr & 0xFF));
634 chan->baseval = (buffer_paddr >> 8) | 1 << (37 - 8);
635
636 chan->cfgval = (!LI_CCFG_LOCK |
637 SHIFT_FIELD(desc->ad1843_slot, LI_CCFG_SLOT) |
638 desc->direction |
639 mode |
640 format);
641
642 size = bufshift - 6;
643 tmask = 13 - fragshift; /* See Lithium DMA Notes above. */
644 ASSERT(size >= 2 && size <= 7);
645 ASSERT(tmask >= 1 && tmask <= 7);
646 chan->ctlval = (!LI_CCTL_RESET |
647 SHIFT_FIELD(size, LI_CCTL_SIZE) |
648 !LI_CCTL_DMA_ENABLE |
649 SHIFT_FIELD(tmask, LI_CCTL_TMASK) |
650 SHIFT_FIELD(0, LI_CCTL_TPTR));
651
652 DBGPV("basereg 0x%x = 0x%lx\n", desc->basereg, chan->baseval);
653 DBGPV("cfgreg 0x%x = 0x%lx\n", desc->cfgreg, chan->cfgval);
654 DBGPV("ctlreg 0x%x = 0x%lx\n", desc->ctlreg, chan->ctlval);
655
656 li_writel(lith, desc->basereg, chan->baseval);
657 li_writel(lith, desc->cfgreg, chan->cfgval);
658 li_writel(lith, desc->ctlreg, chan->ctlval);
659
660 DBGRV();
661 }
662
663 static void li_shutdown_dma(dma_chan_t *chan)
664 {
665 lithium_t *lith = chan->lith;
666 caddr_t lith1 = lith->page1;
667
668 DBGEV("(chan=0x%p)\n", chan);
669
670 chan->ctlval &= ~LI_CCTL_DMA_ENABLE;
671 DBGPV("ctlreg 0x%x = 0x%lx\n", chan->desc->ctlreg, chan->ctlval);
672 li_writel(lith, chan->desc->ctlreg, chan->ctlval);
673
674 /*
675 * Offset 0x500 on Lithium page 1 is an undocumented,
676 * unsupported register that holds the zero sample value.
677 * Lithium is supposed to output zero samples when DMA is
678 * inactive, and repeat the last sample when DMA underflows.
679 * But it has a bug, where, after underflow occurs, the zero
680 * sample is not reset.
681 *
682 * I expect this to break in a future rev of Lithium.
683 */
684
685 if (lith1 && chan->desc->direction == LI_CCFG_DIR_OUT)
686 * (volatile unsigned long *) (lith1 + 0x500) = 0;
687 }
688
689 /*
690 * li_activate_dma always starts dma at the beginning of the buffer.
691 *
692 * N.B., these may be called from interrupt.
693 */
694
695 static __inline__ void li_activate_dma(dma_chan_t *chan)
696 {
697 chan->ctlval |= LI_CCTL_DMA_ENABLE;
698 DBGPV("ctlval = 0x%lx\n", chan->ctlval);
699 li_writel(chan->lith, chan->desc->ctlreg, chan->ctlval);
700 }
701
702 static void li_deactivate_dma(dma_chan_t *chan)
703 {
704 lithium_t *lith = chan->lith;
705 caddr_t lith2 = lith->page2;
706
707 chan->ctlval &= ~(LI_CCTL_DMA_ENABLE | LI_CCTL_RPTR | LI_CCTL_WPTR);
708 DBGPV("ctlval = 0x%lx\n", chan->ctlval);
709 DBGPV("ctlreg 0x%x = 0x%lx\n", chan->desc->ctlreg, chan->ctlval);
710 li_writel(lith, chan->desc->ctlreg, chan->ctlval);
711
712 /*
713 * Offsets 0x98 and 0x9C on Lithium page 2 are undocumented,
714 * unsupported registers that are internal copies of the DMA
715 * read and write pointers. Because of a Lithium bug, these
716 * registers aren't zeroed correctly when DMA is shut off. So
717 * we whack them directly.
718 *
719 * I expect this to break in a future rev of Lithium.
720 */
721
722 if (lith2 && chan->desc->direction == LI_CCFG_DIR_OUT) {
723 * (volatile unsigned long *) (lith2 + 0x98) = 0;
724 * (volatile unsigned long *) (lith2 + 0x9C) = 0;
725 }
726 }
727
728 /*
729 * read/write the ring buffer pointers. These routines' arguments and results
730 * are byte offsets from the beginning of the ring buffer.
731 */
732
733 static __inline__ int li_read_swptr(dma_chan_t *chan)
734 {
735 const unsigned long mask = chan->desc->swptrmask;
736
737 return CHUNKS_TO_BYTES(UNSHIFT_FIELD(chan->ctlval, mask));
738 }
739
740 static __inline__ int li_read_hwptr(dma_chan_t *chan)
741 {
742 return CHUNKS_TO_BYTES(li_readb(chan->lith, chan->desc->hwptrreg));
743 }
744
745 static __inline__ void li_write_swptr(dma_chan_t *chan, int val)
746 {
747 const unsigned long mask = chan->desc->swptrmask;
748
749 ASSERT(!(val & ~CHUNKS_TO_BYTES(0xFF)));
750 val = BYTES_TO_CHUNKS(val);
751 chan->ctlval = (chan->ctlval & ~mask) | SHIFT_FIELD(val, mask);
752 li_writeb(chan->lith, chan->desc->swptrreg, val);
753 }
754
755 /* li_read_USTMSC() returns a UST/MSC pair for the given channel. */
756
757 static void li_read_USTMSC(dma_chan_t *chan, ustmsc_t *ustmsc)
758 {
759 lithium_t *lith = chan->lith;
760 const dma_chan_desc_t *desc = chan->desc;
761 unsigned long now_low, now_high0, now_high1, chan_ust;
762
763 spin_lock(&lith->lock);
764 {
765 /*
766 * retry until we do all five reads without the
767 * high word changing. (High word increments
768 * every 2^32 microseconds, i.e., not often)
769 */
770 do {
771 now_high0 = li_readl(lith, LI_UST_HIGH);
772 now_low = li_readl(lith, LI_UST_LOW);
773
774 /*
775 * Lithium guarantees these two reads will be
776 * atomic -- ust will not increment after msc
777 * is read.
778 */
779
780 ustmsc->msc = li_readl(lith, desc->mscreg);
781 chan_ust = li_readl(lith, desc->ustreg);
782
783 now_high1 = li_readl(lith, LI_UST_HIGH);
784 } while (now_high0 != now_high1);
785 }
786 spin_unlock(&lith->lock);
787 ustmsc->ust = ((unsigned long long) now_high0 << 32 | chan_ust);
788 }
789
790 static void li_enable_interrupts(lithium_t *lith, unsigned int mask)
791 {
792 DBGEV("(lith=0x%p, mask=0x%x)\n", lith, mask);
793
794 /* clear any already-pending interrupts. */
795
796 li_writel(lith, LI_INTR_STATUS, mask);
797
798 /* enable the interrupts. */
799
800 mask |= li_readl(lith, LI_INTR_MASK);
801 li_writel(lith, LI_INTR_MASK, mask);
802 }
803
804 static void li_disable_interrupts(lithium_t *lith, unsigned int mask)
805 {
806 unsigned int keepmask;
807
808 DBGEV("(lith=0x%p, mask=0x%x)\n", lith, mask);
809
810 /* disable the interrupts */
811
812 keepmask = li_readl(lith, LI_INTR_MASK) & ~mask;
813 li_writel(lith, LI_INTR_MASK, keepmask);
814
815 /* clear any pending interrupts. */
816
817 li_writel(lith, LI_INTR_STATUS, mask);
818 }
819
820 /* Get the interrupt status and clear all pending interrupts. */
821
822 static unsigned int li_get_clear_intr_status(lithium_t *lith)
823 {
824 unsigned int status;
825
826 status = li_readl(lith, LI_INTR_STATUS);
827 li_writel(lith, LI_INTR_STATUS, ~0);
828 return status & li_readl(lith, LI_INTR_MASK);
829 }
830
831 static int li_init(lithium_t *lith)
832 {
833 /* 1. System power supplies stabilize. */
834
835 /* 2. Assert the ~RESET signal. */
836
837 li_writel(lith, LI_HOST_CONTROLLER, LI_HC_RESET);
838 udelay(1);
839
840 /* 3. Deassert the ~RESET signal and enter a wait period to allow
841 the AD1843 internal clocks and the external crystal oscillator
842 to stabilize. */
843
844 li_writel(lith, LI_HOST_CONTROLLER, LI_HC_LINK_ENABLE);
845 udelay(1);
846
847 return 0;
848 }
849
850 /*****************************************************************************/
851 /* AD1843 access */
852
853 /*
854 * AD1843 bitfield definitions. All are named as in the AD1843 data
855 * sheet, with ad1843_ prepended and individual bit numbers removed.
856 *
857 * E.g., bits LSS0 through LSS2 become ad1843_LSS.
858 *
859 * Only the bitfields we need are defined.
860 */
861
862 typedef struct ad1843_bitfield {
863 char reg;
864 char lo_bit;
865 char nbits;
866 } ad1843_bitfield_t;
867
868 static const ad1843_bitfield_t
869 ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */
870 ad1843_INIT = { 0, 15, 1 }, /* Clock Initialization Flag */
871 ad1843_RIG = { 2, 0, 4 }, /* Right ADC Input Gain */
872 ad1843_RMGE = { 2, 4, 1 }, /* Right ADC Mic Gain Enable */
873 ad1843_RSS = { 2, 5, 3 }, /* Right ADC Source Select */
874 ad1843_LIG = { 2, 8, 4 }, /* Left ADC Input Gain */
875 ad1843_LMGE = { 2, 12, 1 }, /* Left ADC Mic Gain Enable */
876 ad1843_LSS = { 2, 13, 3 }, /* Left ADC Source Select */
877 ad1843_RX1M = { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
878 ad1843_RX1MM = { 4, 7, 1 }, /* Right Aux 1 Mix Mute */
879 ad1843_LX1M = { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
880 ad1843_LX1MM = { 4, 15, 1 }, /* Left Aux 1 Mix Mute */
881 ad1843_RX2M = { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
882 ad1843_RX2MM = { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
883 ad1843_LX2M = { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
884 ad1843_LX2MM = { 5, 15, 1 }, /* Left Aux 2 Mix Mute */
885 ad1843_RMCM = { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */
886 ad1843_RMCMM = { 7, 7, 1 }, /* Right Mic Mix Mute */
887 ad1843_LMCM = { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */
888 ad1843_LMCMM = { 7, 15, 1 }, /* Left Mic Mix Mute */
889 ad1843_HPOS = { 8, 4, 1 }, /* Headphone Output Voltage Swing */
890 ad1843_HPOM = { 8, 5, 1 }, /* Headphone Output Mute */
891 ad1843_RDA1G = { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */
892 ad1843_RDA1GM = { 9, 7, 1 }, /* Right DAC1 Analog Mute */
893 ad1843_LDA1G = { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */
894 ad1843_LDA1GM = { 9, 15, 1 }, /* Left DAC1 Analog Mute */
895 ad1843_RDA1AM = { 11, 7, 1 }, /* Right DAC1 Digital Mute */
896 ad1843_LDA1AM = { 11, 15, 1 }, /* Left DAC1 Digital Mute */
897 ad1843_ADLC = { 15, 0, 2 }, /* ADC Left Sample Rate Source */
898 ad1843_ADRC = { 15, 2, 2 }, /* ADC Right Sample Rate Source */
899 ad1843_DA1C = { 15, 8, 2 }, /* DAC1 Sample Rate Source */
900 ad1843_C1C = { 17, 0, 16 }, /* Clock 1 Sample Rate Select */
901 ad1843_C2C = { 20, 0, 16 }, /* Clock 1 Sample Rate Select */
902 ad1843_DAADL = { 25, 4, 2 }, /* Digital ADC Left Source Select */
903 ad1843_DAADR = { 25, 6, 2 }, /* Digital ADC Right Source Select */
904 ad1843_DRSFLT = { 25, 15, 1 }, /* Digital Reampler Filter Mode */
905 ad1843_ADLF = { 26, 0, 2 }, /* ADC Left Channel Data Format */
906 ad1843_ADRF = { 26, 2, 2 }, /* ADC Right Channel Data Format */
907 ad1843_ADTLK = { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */
908 ad1843_SCF = { 26, 7, 1 }, /* SCLK Frequency Select */
909 ad1843_DA1F = { 26, 8, 2 }, /* DAC1 Data Format Select */
910 ad1843_DA1SM = { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */
911 ad1843_ADLEN = { 27, 0, 1 }, /* ADC Left Channel Enable */
912 ad1843_ADREN = { 27, 1, 1 }, /* ADC Right Channel Enable */
913 ad1843_AAMEN = { 27, 4, 1 }, /* Analog to Analog Mix Enable */
914 ad1843_ANAEN = { 27, 7, 1 }, /* Analog Channel Enable */
915 ad1843_DA1EN = { 27, 8, 1 }, /* DAC1 Enable */
916 ad1843_DA2EN = { 27, 9, 1 }, /* DAC2 Enable */
917 ad1843_C1EN = { 28, 11, 1 }, /* Clock Generator 1 Enable */
918 ad1843_C2EN = { 28, 12, 1 }, /* Clock Generator 2 Enable */
919 ad1843_PDNI = { 28, 15, 1 }; /* Converter Power Down */
920
921 /*
922 * The various registers of the AD1843 use three different formats for
923 * specifying gain. The ad1843_gain structure parameterizes the
924 * formats.
925 */
926
927 typedef struct ad1843_gain {
928
929 int negative; /* nonzero if gain is negative. */
930 const ad1843_bitfield_t *lfield;
931 const ad1843_bitfield_t *rfield;
932
933 } ad1843_gain_t;
934
935 static const ad1843_gain_t ad1843_gain_RECLEV
936 = { 0, &ad1843_LIG, &ad1843_RIG };
937 static const ad1843_gain_t ad1843_gain_LINE
938 = { 1, &ad1843_LX1M, &ad1843_RX1M };
939 static const ad1843_gain_t ad1843_gain_CD
940 = { 1, &ad1843_LX2M, &ad1843_RX2M };
941 static const ad1843_gain_t ad1843_gain_MIC
942 = { 1, &ad1843_LMCM, &ad1843_RMCM };
943 static const ad1843_gain_t ad1843_gain_PCM
944 = { 1, &ad1843_LDA1G, &ad1843_RDA1G };
945
946 /* read the current value of an AD1843 bitfield. */
947
948 static int ad1843_read_bits(lithium_t *lith, const ad1843_bitfield_t *field)
949 {
950 int w = li_read_ad1843_reg(lith, field->reg);
951 int val = w >> field->lo_bit & ((1 << field->nbits) - 1);
952
953 DBGXV("ad1843_read_bits(lith=0x%p, field->{%d %d %d}) returns 0x%x\n",
954 lith, field->reg, field->lo_bit, field->nbits, val);
955
956 return val;
957 }
958
959 /*
960 * write a new value to an AD1843 bitfield and return the old value.
961 */
962
963 static int ad1843_write_bits(lithium_t *lith,
964 const ad1843_bitfield_t *field,
965 int newval)
966 {
967 int w = li_read_ad1843_reg(lith, field->reg);
968 int mask = ((1 << field->nbits) - 1) << field->lo_bit;
969 int oldval = (w & mask) >> field->lo_bit;
970 int newbits = (newval << field->lo_bit) & mask;
971 w = (w & ~mask) | newbits;
972 (void) li_write_ad1843_reg(lith, field->reg, w);
973
974 DBGXV("ad1843_write_bits(lith=0x%p, field->{%d %d %d}, val=0x%x) "
975 "returns 0x%x\n",
976 lith, field->reg, field->lo_bit, field->nbits, newval,
977 oldval);
978
979 return oldval;
980 }
981
982 /*
983 * ad1843_read_multi reads multiple bitfields from the same AD1843
984 * register. It uses a single read cycle to do it. (Reading the
985 * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20
986 * microseconds.)
987 *
988 * Called ike this.
989 *
990 * ad1843_read_multi(lith, nfields,
991 * &ad1843_FIELD1, &val1,
992 * &ad1843_FIELD2, &val2, ...);
993 */
994
995 static void ad1843_read_multi(lithium_t *lith, int argcount, ...)
996 {
997 va_list ap;
998 const ad1843_bitfield_t *fp;
999 int w = 0, mask, *value, reg = -1;
1000
1001 va_start(ap, argcount);
1002 while (--argcount >= 0) {
1003 fp = va_arg(ap, const ad1843_bitfield_t *);
1004 value = va_arg(ap, int *);
1005 if (reg == -1) {
1006 reg = fp->reg;
1007 w = li_read_ad1843_reg(lith, reg);
1008 }
1009 ASSERT(reg == fp->reg);
1010 mask = (1 << fp->nbits) - 1;
1011 *value = w >> fp->lo_bit & mask;
1012 }
1013 va_end(ap);
1014 }
1015
1016 /*
1017 * ad1843_write_multi stores multiple bitfields into the same AD1843
1018 * register. It uses one read and one write cycle to do it.
1019 *
1020 * Called like this.
1021 *
1022 * ad1843_write_multi(lith, nfields,
1023 * &ad1843_FIELD1, val1,
1024 * &ad1843_FIELF2, val2, ...);
1025 */
1026
1027 static void ad1843_write_multi(lithium_t *lith, int argcount, ...)
1028 {
1029 va_list ap;
1030 int reg;
1031 const ad1843_bitfield_t *fp;
1032 int value;
1033 int w, m, mask, bits;
1034
1035 mask = 0;
1036 bits = 0;
1037 reg = -1;
1038
1039 va_start(ap, argcount);
1040 while (--argcount >= 0) {
1041 fp = va_arg(ap, const ad1843_bitfield_t *);
1042 value = va_arg(ap, int);
1043 if (reg == -1)
1044 reg = fp->reg;
1045 ASSERT(fp->reg == reg);
1046 m = ((1 << fp->nbits) - 1) << fp->lo_bit;
1047 mask |= m;
1048 bits |= (value << fp->lo_bit) & m;
1049 }
1050 va_end(ap);
1051 ASSERT(!(bits & ~mask));
1052 if (~mask & 0xFFFF)
1053 w = li_read_ad1843_reg(lith, reg);
1054 else
1055 w = 0;
1056 w = (w & ~mask) | bits;
1057 (void) li_write_ad1843_reg(lith, reg, w);
1058 }
1059
1060 /*
1061 * ad1843_get_gain reads the specified register and extracts the gain value
1062 * using the supplied gain type. It returns the gain in OSS format.
1063 */
1064
1065 static int ad1843_get_gain(lithium_t *lith, const ad1843_gain_t *gp)
1066 {
1067 int lg, rg;
1068 unsigned short mask = (1 << gp->lfield->nbits) - 1;
1069
1070 ad1843_read_multi(lith, 2, gp->lfield, &lg, gp->rfield, &rg);
1071 if (gp->negative) {
1072 lg = mask - lg;
1073 rg = mask - rg;
1074 }
1075 lg = (lg * 100 + (mask >> 1)) / mask;
1076 rg = (rg * 100 + (mask >> 1)) / mask;
1077 return lg << 0 | rg << 8;
1078 }
1079
1080 /*
1081 * Set an audio channel's gain. Converts from OSS format to AD1843's
1082 * format.
1083 *
1084 * Returns the new gain, which may be lower than the old gain.
1085 */
1086
1087 static int ad1843_set_gain(lithium_t *lith,
1088 const ad1843_gain_t *gp,
1089 int newval)
1090 {
1091 unsigned short mask = (1 << gp->lfield->nbits) - 1;
1092
1093 int lg = newval >> 0 & 0xFF;
1094 int rg = newval >> 8;
1095 if (lg < 0 || lg > 100 || rg < 0 || rg > 100)
1096 return -EINVAL;
1097 lg = (lg * mask + (mask >> 1)) / 100;
1098 rg = (rg * mask + (mask >> 1)) / 100;
1099 if (gp->negative) {
1100 lg = mask - lg;
1101 rg = mask - rg;
1102 }
1103 ad1843_write_multi(lith, 2, gp->lfield, lg, gp->rfield, rg);
1104 return ad1843_get_gain(lith, gp);
1105 }
1106
1107 /* Returns the current recording source, in OSS format. */
1108
1109 static int ad1843_get_recsrc(lithium_t *lith)
1110 {
1111 int ls = ad1843_read_bits(lith, &ad1843_LSS);
1112
1113 switch (ls) {
1114 case 1:
1115 return SOUND_MASK_MIC;
1116 case 2:
1117 return SOUND_MASK_LINE;
1118 case 3:
1119 return SOUND_MASK_CD;
1120 case 6:
1121 return SOUND_MASK_PCM;
1122 default:
1123 ASSERT(0);
1124 return -1;
1125 }
1126 }
1127
1128 /*
1129 * Enable/disable digital resample mode in the AD1843.
1130 *
1131 * The AD1843 requires that ADL, ADR, DA1 and DA2 be powered down
1132 * while switching modes. So we save DA1's state (DA2's state is not
1133 * interesting), power them down, switch into/out of resample mode,
1134 * power them up, and restore state.
1135 *
1136 * This will cause audible glitches if D/A or A/D is going on, so the
1137 * driver disallows that (in mixer_write_ioctl()).
1138 *
1139 * The open question is, is this worth doing? I'm leaving it in,
1140 * because it's written, but...
1141 */
1142
1143 static void ad1843_set_resample_mode(lithium_t *lith, int onoff)
1144 {
1145 /* Save DA1 mute and gain (addr 9 is DA1 analog gain/attenuation) */
1146 int save_da1 = li_read_ad1843_reg(lith, 9);
1147
1148 /* Power down A/D and D/A. */
1149 ad1843_write_multi(lith, 4,
1150 &ad1843_DA1EN, 0,
1151 &ad1843_DA2EN, 0,
1152 &ad1843_ADLEN, 0,
1153 &ad1843_ADREN, 0);
1154
1155 /* Switch mode */
1156 ASSERT(onoff == 0 || onoff == 1);
1157 ad1843_write_bits(lith, &ad1843_DRSFLT, onoff);
1158
1159 /* Power up A/D and D/A. */
1160 ad1843_write_multi(lith, 3,
1161 &ad1843_DA1EN, 1,
1162 &ad1843_ADLEN, 1,
1163 &ad1843_ADREN, 1);
1164
1165 /* Restore DA1 mute and gain. */
1166 li_write_ad1843_reg(lith, 9, save_da1);
1167 }
1168
1169 /*
1170 * Set recording source. Arg newsrc specifies an OSS channel mask.
1171 *
1172 * The complication is that when we switch into/out of loopback mode
1173 * (i.e., src = SOUND_MASK_PCM), we change the AD1843 into/out of
1174 * digital resampling mode.
1175 *
1176 * Returns newsrc on success, -errno on failure.
1177 */
1178
1179 static int ad1843_set_recsrc(lithium_t *lith, int newsrc)
1180 {
1181 int bits;
1182 int oldbits;
1183
1184 switch (newsrc) {
1185 case SOUND_MASK_PCM:
1186 bits = 6;
1187 break;
1188
1189 case SOUND_MASK_MIC:
1190 bits = 1;
1191 break;
1192
1193 case SOUND_MASK_LINE:
1194 bits = 2;
1195 break;
1196
1197 case SOUND_MASK_CD:
1198 bits = 3;
1199 break;
1200
1201 default:
1202 return -EINVAL;
1203 }
1204 oldbits = ad1843_read_bits(lith, &ad1843_LSS);
1205 if (newsrc == SOUND_MASK_PCM && oldbits != 6) {
1206 DBGP("enabling digital resample mode\n");
1207 ad1843_set_resample_mode(lith, 1);
1208 ad1843_write_multi(lith, 2,
1209 &ad1843_DAADL, 2,
1210 &ad1843_DAADR, 2);
1211 } else if (newsrc != SOUND_MASK_PCM && oldbits == 6) {
1212 DBGP("disabling digital resample mode\n");
1213 ad1843_set_resample_mode(lith, 0);
1214 ad1843_write_multi(lith, 2,
1215 &ad1843_DAADL, 0,
1216 &ad1843_DAADR, 0);
1217 }
1218 ad1843_write_multi(lith, 2, &ad1843_LSS, bits, &ad1843_RSS, bits);
1219 return newsrc;
1220 }
1221
1222 /*
1223 * Return current output sources, in OSS format.
1224 */
1225
1226 static int ad1843_get_outsrc(lithium_t *lith)
1227 {
1228 int pcm, line, mic, cd;
1229
1230 pcm = ad1843_read_bits(lith, &ad1843_LDA1GM) ? 0 : SOUND_MASK_PCM;
1231 line = ad1843_read_bits(lith, &ad1843_LX1MM) ? 0 : SOUND_MASK_LINE;
1232 cd = ad1843_read_bits(lith, &ad1843_LX2MM) ? 0 : SOUND_MASK_CD;
1233 mic = ad1843_read_bits(lith, &ad1843_LMCMM) ? 0 : SOUND_MASK_MIC;
1234
1235 return pcm | line | cd | mic;
1236 }
1237
1238 /*
1239 * Set output sources. Arg is a mask of active sources in OSS format.
1240 *
1241 * Returns source mask on success, -errno on failure.
1242 */
1243
1244 static int ad1843_set_outsrc(lithium_t *lith, int mask)
1245 {
1246 int pcm, line, mic, cd;
1247
1248 if (mask & ~(SOUND_MASK_PCM | SOUND_MASK_LINE |
1249 SOUND_MASK_CD | SOUND_MASK_MIC))
1250 return -EINVAL;
1251 pcm = (mask & SOUND_MASK_PCM) ? 0 : 1;
1252 line = (mask & SOUND_MASK_LINE) ? 0 : 1;
1253 mic = (mask & SOUND_MASK_MIC) ? 0 : 1;
1254 cd = (mask & SOUND_MASK_CD) ? 0 : 1;
1255
1256 ad1843_write_multi(lith, 2, &ad1843_LDA1GM, pcm, &ad1843_RDA1GM, pcm);
1257 ad1843_write_multi(lith, 2, &ad1843_LX1MM, line, &ad1843_RX1MM, line);
1258 ad1843_write_multi(lith, 2, &ad1843_LX2MM, cd, &ad1843_RX2MM, cd);
1259 ad1843_write_multi(lith, 2, &ad1843_LMCMM, mic, &ad1843_RMCMM, mic);
1260
1261 return mask;
1262 }
1263
1264 /* Setup ad1843 for D/A conversion. */
1265
1266 static void ad1843_setup_dac(lithium_t *lith,
1267 int framerate,
1268 int fmt,
1269 int channels)
1270 {
1271 int ad_fmt = 0, ad_mode = 0;
1272
1273 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1274 lith, framerate, fmt, channels);
1275
1276 switch (fmt) {
1277 case AFMT_S8: ad_fmt = 1; break;
1278 case AFMT_U8: ad_fmt = 1; break;
1279 case AFMT_S16_LE: ad_fmt = 1; break;
1280 case AFMT_MU_LAW: ad_fmt = 2; break;
1281 case AFMT_A_LAW: ad_fmt = 3; break;
1282 default: ASSERT(0);
1283 }
1284
1285 switch (channels) {
1286 case 2: ad_mode = 0; break;
1287 case 1: ad_mode = 1; break;
1288 default: ASSERT(0);
1289 }
1290
1291 DBGPV("ad_mode = %d, ad_fmt = %d\n", ad_mode, ad_fmt);
1292 ASSERT(framerate >= 4000 && framerate <= 49000);
1293 ad1843_write_bits(lith, &ad1843_C1C, framerate);
1294 ad1843_write_multi(lith, 2,
1295 &ad1843_DA1SM, ad_mode, &ad1843_DA1F, ad_fmt);
1296 }
1297
1298 static void ad1843_shutdown_dac(lithium_t *lith)
1299 {
1300 ad1843_write_bits(lith, &ad1843_DA1F, 1);
1301 }
1302
1303 static void ad1843_setup_adc(lithium_t *lith, int framerate, int fmt, int channels)
1304 {
1305 int da_fmt = 0;
1306
1307 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1308 lith, framerate, fmt, channels);
1309
1310 switch (fmt) {
1311 case AFMT_S8: da_fmt = 1; break;
1312 case AFMT_U8: da_fmt = 1; break;
1313 case AFMT_S16_LE: da_fmt = 1; break;
1314 case AFMT_MU_LAW: da_fmt = 2; break;
1315 case AFMT_A_LAW: da_fmt = 3; break;
1316 default: ASSERT(0);
1317 }
1318
1319 DBGPV("da_fmt = %d\n", da_fmt);
1320 ASSERT(framerate >= 4000 && framerate <= 49000);
1321 ad1843_write_bits(lith, &ad1843_C2C, framerate);
1322 ad1843_write_multi(lith, 2,
1323 &ad1843_ADLF, da_fmt, &ad1843_ADRF, da_fmt);
1324 }
1325
1326 static void ad1843_shutdown_adc(lithium_t *lith)
1327 {
1328 /* nothing to do */
1329 }
1330
1331 /*
1332 * Fully initialize the ad1843. As described in the AD1843 data
1333 * sheet, section "START-UP SEQUENCE". The numbered comments are
1334 * subsection headings from the data sheet. See the data sheet, pages
1335 * 52-54, for more info.
1336 *
1337 * return 0 on success, -errno on failure. */
1338
1339 static int __init ad1843_init(lithium_t *lith)
1340 {
1341 unsigned long later;
1342 int err;
1343
1344 err = li_init(lith);
1345 if (err)
1346 return err;
1347
1348 if (ad1843_read_bits(lith, &ad1843_INIT) != 0) {
1349 printk(KERN_ERR "vwsnd sound: AD1843 won't initialize\n");
1350 return -EIO;
1351 }
1352
1353 ad1843_write_bits(lith, &ad1843_SCF, 1);
1354
1355 /* 4. Put the conversion resources into standby. */
1356
1357 ad1843_write_bits(lith, &ad1843_PDNI, 0);
1358 later = jiffies + HZ / 2; /* roughly half a second */
1359 DBGDO(shut_up++);
1360 while (ad1843_read_bits(lith, &ad1843_PDNO)) {
1361 if (jiffies > later) {
1362 printk(KERN_ERR
1363 "vwsnd audio: AD1843 won't power up\n");
1364 return -EIO;
1365 }
1366 schedule();
1367 }
1368 DBGDO(shut_up--);
1369
1370 /* 5. Power up the clock generators and enable clock output pins. */
1371
1372 ad1843_write_multi(lith, 2, &ad1843_C1EN, 1, &ad1843_C2EN, 1);
1373
1374 /* 6. Configure conversion resources while they are in standby. */
1375
1376 /* DAC1 uses clock 1 as source, ADC uses clock 2. Always. */
1377
1378 ad1843_write_multi(lith, 3,
1379 &ad1843_DA1C, 1,
1380 &ad1843_ADLC, 2,
1381 &ad1843_ADRC, 2);
1382
1383 /* 7. Enable conversion resources. */
1384
1385 ad1843_write_bits(lith, &ad1843_ADTLK, 1);
1386 ad1843_write_multi(lith, 5,
1387 &ad1843_ANAEN, 1,
1388 &ad1843_AAMEN, 1,
1389 &ad1843_DA1EN, 1,
1390 &ad1843_ADLEN, 1,
1391 &ad1843_ADREN, 1);
1392
1393 /* 8. Configure conversion resources while they are enabled. */
1394
1395 ad1843_write_bits(lith, &ad1843_DA1C, 1);
1396
1397 /* Unmute all channels. */
1398
1399 ad1843_set_outsrc(lith,
1400 (SOUND_MASK_PCM | SOUND_MASK_LINE |
1401 SOUND_MASK_MIC | SOUND_MASK_CD));
1402 ad1843_write_multi(lith, 2, &ad1843_LDA1AM, 0, &ad1843_RDA1AM, 0);
1403
1404 /* Set default recording source to Line In and set
1405 * mic gain to +20 dB.
1406 */
1407
1408 ad1843_set_recsrc(lith, SOUND_MASK_LINE);
1409 ad1843_write_multi(lith, 2, &ad1843_LMGE, 1, &ad1843_RMGE, 1);
1410
1411 /* Set Speaker Out level to +/- 4V and unmute it. */
1412
1413 ad1843_write_multi(lith, 2, &ad1843_HPOS, 1, &ad1843_HPOM, 0);
1414
1415 return 0;
1416 }
1417
1418 /*****************************************************************************/
1419 /* PCM I/O */
1420
1421 #define READ_INTR_MASK (LI_INTR_COMM1_TRIG | LI_INTR_COMM1_OVERFLOW)
1422 #define WRITE_INTR_MASK (LI_INTR_COMM2_TRIG | LI_INTR_COMM2_UNDERFLOW)
1423
1424 typedef enum vwsnd_port_swstate { /* software state */
1425 SW_OFF,
1426 SW_INITIAL,
1427 SW_RUN,
1428 SW_DRAIN,
1429 } vwsnd_port_swstate_t;
1430
1431 typedef enum vwsnd_port_hwstate { /* hardware state */
1432 HW_STOPPED,
1433 HW_RUNNING,
1434 } vwsnd_port_hwstate_t;
1435
1436 /*
1437 * These flags are read by ISR, but only written at baseline.
1438 */
1439
1440 typedef enum vwsnd_port_flags {
1441 DISABLED = 1 << 0,
1442 ERFLOWN = 1 << 1, /* overflown or underflown */
1443 HW_BUSY = 1 << 2,
1444 } vwsnd_port_flags_t;
1445
1446 /*
1447 * vwsnd_port is the per-port data structure. Each device has two
1448 * ports, one for input and one for output.
1449 *
1450 * Locking:
1451 *
1452 * port->lock protects: hwstate, flags, swb_[iu]_avail.
1453 *
1454 * devc->io_sema protects: swstate, sw_*, swb_[iu]_idx.
1455 *
1456 * everything else is only written by open/release or
1457 * pcm_{setup,shutdown}(), which are serialized by a
1458 * combination of devc->open_sema and devc->io_sema.
1459 */
1460
1461 typedef struct vwsnd_port {
1462
1463 spinlock_t lock;
1464 wait_queue_head_t queue;
1465 vwsnd_port_swstate_t swstate;
1466 vwsnd_port_hwstate_t hwstate;
1467 vwsnd_port_flags_t flags;
1468
1469 int sw_channels;
1470 int sw_samplefmt;
1471 int sw_framerate;
1472 int sample_size;
1473 int frame_size;
1474 unsigned int zero_word; /* zero for the sample format */
1475
1476 int sw_fragshift;
1477 int sw_fragcount;
1478 int sw_subdivshift;
1479
1480 unsigned int hw_fragshift;
1481 unsigned int hw_fragsize;
1482 unsigned int hw_fragcount;
1483
1484 int hwbuf_size;
1485 unsigned long hwbuf_paddr;
1486 unsigned long hwbuf_vaddr;
1487 caddr_t hwbuf; /* hwbuf == hwbuf_vaddr */
1488 int hwbuf_max; /* max bytes to preload */
1489
1490 caddr_t swbuf;
1491 unsigned int swbuf_size; /* size in bytes */
1492 unsigned int swb_u_idx; /* index of next user byte */
1493 unsigned int swb_i_idx; /* index of next intr byte */
1494 unsigned int swb_u_avail; /* # bytes avail to user */
1495 unsigned int swb_i_avail; /* # bytes avail to intr */
1496
1497 dma_chan_t chan;
1498
1499 /* Accounting */
1500
1501 int byte_count;
1502 int frag_count;
1503 int MSC_offset;
1504
1505 } vwsnd_port_t;
1506
1507 /* vwsnd_dev is the per-device data structure. */
1508
1509 typedef struct vwsnd_dev {
1510 struct vwsnd_dev *next_dev;
1511 int audio_minor; /* minor number of audio device */
1512 int mixer_minor; /* minor number of mixer device */
1513
1514 struct semaphore open_sema;
1515 struct semaphore io_sema;
1516 struct semaphore mix_sema;
1517 mode_t open_mode;
1518 wait_queue_head_t open_wait;
1519
1520 lithium_t lith;
1521
1522 vwsnd_port_t rport;
1523 vwsnd_port_t wport;
1524 } vwsnd_dev_t;
1525
1526 static vwsnd_dev_t *vwsnd_dev_list; /* linked list of all devices */
1527
1528 static atomic_t vwsnd_use_count = ATOMIC_INIT(0);
1529
1530 # define INC_USE_COUNT (atomic_inc(&vwsnd_use_count))
1531 # define DEC_USE_COUNT (atomic_dec(&vwsnd_use_count))
1532 # define IN_USE (atomic_read(&vwsnd_use_count) != 0)
1533
1534 /*
1535 * Lithium can only DMA multiples of 32 bytes. Its DMA buffer may
1536 * be up to 8 Kb. This driver always uses 8 Kb.
1537 *
1538 * Memory bug workaround -- I'm not sure what's going on here, but
1539 * somehow pcm_copy_out() was triggering segv's going on to the next
1540 * page of the hw buffer. So, I make the hw buffer one size bigger
1541 * than we actually use. That way, the following page is allocated
1542 * and mapped, and no error. I suspect that something is broken
1543 * in Cobalt, but haven't really investigated. HBO is the actual
1544 * size of the buffer, and HWBUF_ORDER is what we allocate.
1545 */
1546
1547 #define HWBUF_SHIFT 13
1548 #define HWBUF_SIZE (1 << HWBUF_SHIFT)
1549 # define HBO (HWBUF_SHIFT > PAGE_SHIFT ? HWBUF_SHIFT - PAGE_SHIFT : 0)
1550 # define HWBUF_ORDER (HBO + 1) /* next size bigger */
1551 #define MIN_SPEED 4000
1552 #define MAX_SPEED 49000
1553
1554 #define MIN_FRAGSHIFT (DMACHUNK_SHIFT + 1)
1555 #define MAX_FRAGSHIFT (PAGE_SHIFT)
1556 #define MIN_FRAGSIZE (1 << MIN_FRAGSHIFT)
1557 #define MAX_FRAGSIZE (1 << MAX_FRAGSHIFT)
1558 #define MIN_FRAGCOUNT(fragsize) 3
1559 #define MAX_FRAGCOUNT(fragsize) (32 * PAGE_SIZE / (fragsize))
1560 #define DEFAULT_FRAGSHIFT 12
1561 #define DEFAULT_FRAGCOUNT 16
1562 #define DEFAULT_SUBDIVSHIFT 0
1563
1564 /*
1565 * The software buffer (swbuf) is a ring buffer shared between user
1566 * level and interrupt level. Each level owns some of the bytes in
1567 * the buffer, and may give bytes away by calling swb_inc_{u,i}().
1568 * User level calls _u for user, and interrupt level calls _i for
1569 * interrupt.
1570 *
1571 * port->swb_{u,i}_avail is the number of bytes available to that level.
1572 *
1573 * port->swb_{u,i}_idx is the index of the first available byte in the
1574 * buffer.
1575 *
1576 * Each level calls swb_inc_{u,i}() to atomically increment its index,
1577 * recalculate the number of bytes available for both sides, and
1578 * return the number of bytes available. Since each side can only
1579 * give away bytes, the other side can only increase the number of
1580 * bytes available to this side. Each side updates its own index
1581 * variable, swb_{u,i}_idx, so no lock is needed to read it.
1582 *
1583 * To query the number of bytes available, call swb_inc_{u,i} with an
1584 * increment of zero.
1585 */
1586
1587 static __inline__ unsigned int __swb_inc_u(vwsnd_port_t *port, int inc)
1588 {
1589 if (inc) {
1590 port->swb_u_idx += inc;
1591 port->swb_u_idx %= port->swbuf_size;
1592 port->swb_u_avail -= inc;
1593 port->swb_i_avail += inc;
1594 }
1595 return port->swb_u_avail;
1596 }
1597
1598 static __inline__ unsigned int swb_inc_u(vwsnd_port_t *port, int inc)
1599 {
1600 unsigned long flags;
1601 unsigned int ret;
1602
1603 spin_lock_irqsave(&port->lock, flags);
1604 {
1605 ret = __swb_inc_u(port, inc);
1606 }
1607 spin_unlock_irqrestore(&port->lock, flags);
1608 return ret;
1609 }
1610
1611 static __inline__ unsigned int __swb_inc_i(vwsnd_port_t *port, int inc)
1612 {
1613 if (inc) {
1614 port->swb_i_idx += inc;
1615 port->swb_i_idx %= port->swbuf_size;
1616 port->swb_i_avail -= inc;
1617 port->swb_u_avail += inc;
1618 }
1619 return port->swb_i_avail;
1620 }
1621
1622 static __inline__ unsigned int swb_inc_i(vwsnd_port_t *port, int inc)
1623 {
1624 unsigned long flags;
1625 unsigned int ret;
1626
1627 spin_lock_irqsave(&port->lock, flags);
1628 {
1629 ret = __swb_inc_i(port, inc);
1630 }
1631 spin_unlock_irqrestore(&port->lock, flags);
1632 return ret;
1633 }
1634
1635 /*
1636 * pcm_setup - this routine initializes all port state after
1637 * mode-setting ioctls have been done, but before the first I/O is
1638 * done.
1639 *
1640 * Locking: called with devc->io_sema held.
1641 *
1642 * Returns 0 on success, -errno on failure.
1643 */
1644
1645 static int pcm_setup(vwsnd_dev_t *devc,
1646 vwsnd_port_t *rport,
1647 vwsnd_port_t *wport)
1648 {
1649 vwsnd_port_t *aport = rport ? rport : wport;
1650 int sample_size;
1651 unsigned int zero_word;
1652
1653 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc, rport, wport);
1654
1655 ASSERT(aport != NULL);
1656 if (aport->swbuf != NULL)
1657 return 0;
1658 switch (aport->sw_samplefmt) {
1659 case AFMT_MU_LAW:
1660 sample_size = 1;
1661 zero_word = 0xFFFFFFFF ^ 0x80808080;
1662 break;
1663
1664 case AFMT_A_LAW:
1665 sample_size = 1;
1666 zero_word = 0xD5D5D5D5 ^ 0x80808080;
1667 break;
1668
1669 case AFMT_U8:
1670 sample_size = 1;
1671 zero_word = 0x80808080;
1672 break;
1673
1674 case AFMT_S8:
1675 sample_size = 1;
1676 zero_word = 0x00000000;
1677 break;
1678
1679 case AFMT_S16_LE:
1680 sample_size = 2;
1681 zero_word = 0x00000000;
1682 break;
1683
1684 default:
1685 sample_size = 0; /* prevent compiler warning */
1686 zero_word = 0;
1687 ASSERT(0);
1688 }
1689 aport->sample_size = sample_size;
1690 aport->zero_word = zero_word;
1691 aport->frame_size = aport->sw_channels * aport->sample_size;
1692 aport->hw_fragshift = aport->sw_fragshift - aport->sw_subdivshift;
1693 aport->hw_fragsize = 1 << aport->hw_fragshift;
1694 aport->hw_fragcount = aport->sw_fragcount << aport->sw_subdivshift;
1695 ASSERT(aport->hw_fragsize >= MIN_FRAGSIZE);
1696 ASSERT(aport->hw_fragsize <= MAX_FRAGSIZE);
1697 ASSERT(aport->hw_fragcount >= MIN_FRAGCOUNT(aport->hw_fragsize));
1698 ASSERT(aport->hw_fragcount <= MAX_FRAGCOUNT(aport->hw_fragsize));
1699 if (rport) {
1700 int hwfrags, swfrags;
1701 rport->hwbuf_max = aport->hwbuf_size - DMACHUNK_SIZE;
1702 hwfrags = rport->hwbuf_max >> aport->hw_fragshift;
1703 swfrags = aport->hw_fragcount - hwfrags;
1704 if (swfrags < 2)
1705 swfrags = 2;
1706 rport->swbuf_size = swfrags * aport->hw_fragsize;
1707 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags, swfrags);
1708 DBGPV("read hwbuf_max = %d, swbuf_size = %d\n",
1709 rport->hwbuf_max, rport->swbuf_size);
1710 }
1711 if (wport) {
1712 int hwfrags, swfrags;
1713 int total_bytes = aport->hw_fragcount * aport->hw_fragsize;
1714 wport->hwbuf_max = aport->hwbuf_size - DMACHUNK_SIZE;
1715 if (wport->hwbuf_max > total_bytes)
1716 wport->hwbuf_max = total_bytes;
1717 hwfrags = wport->hwbuf_max >> aport->hw_fragshift;
1718 DBGPV("hwfrags = %d\n", hwfrags);
1719 swfrags = aport->hw_fragcount - hwfrags;
1720 if (swfrags < 2)
1721 swfrags = 2;
1722 wport->swbuf_size = swfrags * aport->hw_fragsize;
1723 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags, swfrags);
1724 DBGPV("write hwbuf_max = %d, swbuf_size = %d\n",
1725 wport->hwbuf_max, wport->swbuf_size);
1726 }
1727
1728 aport->swb_u_idx = 0;
1729 aport->swb_i_idx = 0;
1730 aport->byte_count = 0;
1731
1732 /*
1733 * Is this a Cobalt bug? We need to make this buffer extend
1734 * one page further than we actually use -- somehow memcpy
1735 * causes an exceptoin otherwise. I suspect there's a bug in
1736 * Cobalt (or somewhere) where it's generating a fault on a
1737 * speculative load or something. Obviously, I haven't taken
1738 * the time to track it down.
1739 */
1740
1741 aport->swbuf = vmalloc(aport->swbuf_size + PAGE_SIZE);
1742 if (!aport->swbuf)
1743 return -ENOMEM;
1744 if (rport && wport) {
1745 ASSERT(aport == rport);
1746 ASSERT(wport->swbuf == NULL);
1747 /* One extra page - see comment above. */
1748 wport->swbuf = vmalloc(aport->swbuf_size + PAGE_SIZE);
1749 if (!wport->swbuf) {
1750 vfree(aport->swbuf);
1751 aport->swbuf = NULL;
1752 return -ENOMEM;
1753 }
1754 wport->sample_size = rport->sample_size;
1755 wport->zero_word = rport->zero_word;
1756 wport->frame_size = rport->frame_size;
1757 wport->hw_fragshift = rport->hw_fragshift;
1758 wport->hw_fragsize = rport->hw_fragsize;
1759 wport->hw_fragcount = rport->hw_fragcount;
1760 wport->swbuf_size = rport->swbuf_size;
1761 wport->hwbuf_max = rport->hwbuf_max;
1762 wport->swb_u_idx = rport->swb_u_idx;
1763 wport->swb_i_idx = rport->swb_i_idx;
1764 wport->byte_count = rport->byte_count;
1765 }
1766 if (rport) {
1767 rport->swb_u_avail = 0;
1768 rport->swb_i_avail = rport->swbuf_size;
1769 rport->swstate = SW_RUN;
1770 li_setup_dma(&rport->chan,
1771 &li_comm1,
1772 &devc->lith,
1773 rport->hwbuf_paddr,
1774 HWBUF_SHIFT,
1775 rport->hw_fragshift,
1776 rport->sw_channels,
1777 rport->sample_size);
1778 ad1843_setup_adc(&devc->lith,
1779 rport->sw_framerate,
1780 rport->sw_samplefmt,
1781 rport->sw_channels);
1782 li_enable_interrupts(&devc->lith, READ_INTR_MASK);
1783 if (!(rport->flags & DISABLED)) {
1784 ustmsc_t ustmsc;
1785 rport->hwstate = HW_RUNNING;
1786 li_activate_dma(&rport->chan);
1787 li_read_USTMSC(&rport->chan, &ustmsc);
1788 rport->MSC_offset = ustmsc.msc;
1789 }
1790 }
1791 if (wport) {
1792 if (wport->hwbuf_max > wport->swbuf_size)
1793 wport->hwbuf_max = wport->swbuf_size;
1794 wport->flags &= ~ERFLOWN;
1795 wport->swb_u_avail = wport->swbuf_size;
1796 wport->swb_i_avail = 0;
1797 wport->swstate = SW_RUN;
1798 li_setup_dma(&wport->chan,
1799 &li_comm2,
1800 &devc->lith,
1801 wport->hwbuf_paddr,
1802 HWBUF_SHIFT,
1803 wport->hw_fragshift,
1804 wport->sw_channels,
1805 wport->sample_size);
1806 ad1843_setup_dac(&devc->lith,
1807 wport->sw_framerate,
1808 wport->sw_samplefmt,
1809 wport->sw_channels);
1810 li_enable_interrupts(&devc->lith, WRITE_INTR_MASK);
1811 }
1812 DBGRV();
1813 return 0;
1814 }
1815
1816 /*
1817 * pcm_shutdown_port - shut down one port (direction) for PCM I/O.
1818 * Only called from pcm_shutdown.
1819 */
1820
1821 static void pcm_shutdown_port(vwsnd_dev_t *devc,
1822 vwsnd_port_t *aport,
1823 unsigned int mask)
1824 {
1825 unsigned long flags;
1826 vwsnd_port_hwstate_t hwstate;
1827 DECLARE_WAITQUEUE(wait, current);
1828
1829 aport->swstate = SW_INITIAL;
1830 add_wait_queue(&aport->queue, &wait);
1831 while (1) {
1832 set_current_state(TASK_UNINTERRUPTIBLE);
1833 spin_lock_irqsave(&aport->lock, flags);
1834 {
1835 hwstate = aport->hwstate;
1836 }
1837 spin_unlock_irqrestore(&aport->lock, flags);
1838 if (hwstate == HW_STOPPED)
1839 break;
1840 schedule();
1841 }
1842 current->state = TASK_RUNNING;
1843 remove_wait_queue(&aport->queue, &wait);
1844 li_disable_interrupts(&devc->lith, mask);
1845 if (aport == &devc->rport)
1846 ad1843_shutdown_adc(&devc->lith);
1847 else /* aport == &devc->wport) */
1848 ad1843_shutdown_dac(&devc->lith);
1849 li_shutdown_dma(&aport->chan);
1850 vfree(aport->swbuf);
1851 aport->swbuf = NULL;
1852 aport->byte_count = 0;
1853 }
1854
1855 /*
1856 * pcm_shutdown undoes what pcm_setup did.
1857 * Also sets the ports' swstate to newstate.
1858 */
1859
1860 static void pcm_shutdown(vwsnd_dev_t *devc,
1861 vwsnd_port_t *rport,
1862 vwsnd_port_t *wport)
1863 {
1864 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc, rport, wport);
1865
1866 if (rport && rport->swbuf) {
1867 DBGPV("shutting down rport\n");
1868 pcm_shutdown_port(devc, rport, READ_INTR_MASK);
1869 }
1870 if (wport && wport->swbuf) {
1871 DBGPV("shutting down wport\n");
1872 pcm_shutdown_port(devc, wport, WRITE_INTR_MASK);
1873 }
1874 DBGRV();
1875 }
1876
1877 static void pcm_copy_in(vwsnd_port_t *rport, int swidx, int hwidx, int nb)
1878 {
1879 char *src = rport->hwbuf + hwidx;
1880 char *dst = rport->swbuf + swidx;
1881 int fmt = rport->sw_samplefmt;
1882
1883 DBGPV("swidx = %d, hwidx = %d\n", swidx, hwidx);
1884 ASSERT(rport->hwbuf != NULL);
1885 ASSERT(rport->swbuf != NULL);
1886 ASSERT(nb > 0 && (nb % 32) == 0);
1887 ASSERT(swidx % 32 == 0 && hwidx % 32 == 0);
1888 ASSERT(swidx >= 0 && swidx + nb <= rport->swbuf_size);
1889 ASSERT(hwidx >= 0 && hwidx + nb <= rport->hwbuf_size);
1890
1891 if (fmt == AFMT_MU_LAW || fmt == AFMT_A_LAW || fmt == AFMT_S8) {
1892
1893 /* See Sample Format Notes above. */
1894
1895 char *end = src + nb;
1896 while (src < end)
1897 *dst++ = *src++ ^ 0x80;
1898 } else
1899 memcpy(dst, src, nb);
1900 }
1901
1902 static void pcm_copy_out(vwsnd_port_t *wport, int swidx, int hwidx, int nb)
1903 {
1904 char *src = wport->swbuf + swidx;
1905 char *dst = wport->hwbuf + hwidx;
1906 int fmt = wport->sw_samplefmt;
1907
1908 ASSERT(nb > 0 && (nb % 32) == 0);
1909 ASSERT(wport->hwbuf != NULL);
1910 ASSERT(wport->swbuf != NULL);
1911 ASSERT(swidx % 32 == 0 && hwidx % 32 == 0);
1912 ASSERT(swidx >= 0 && swidx + nb <= wport->swbuf_size);
1913 ASSERT(hwidx >= 0 && hwidx + nb <= wport->hwbuf_size);
1914 if (fmt == AFMT_MU_LAW || fmt == AFMT_A_LAW || fmt == AFMT_S8) {
1915
1916 /* See Sample Format Notes above. */
1917
1918 char *end = src + nb;
1919 while (src < end)
1920 *dst++ = *src++ ^ 0x80;
1921 } else
1922 memcpy(dst, src, nb);
1923 }
1924
1925 /*
1926 * pcm_output() is called both from baselevel and from interrupt level.
1927 * This is where audio frames are copied into the hardware-accessible
1928 * ring buffer.
1929 *
1930 * Locking note: The part of this routine that figures out what to do
1931 * holds wport->lock. The longer part releases wport->lock, but sets
1932 * wport->flags & HW_BUSY. Afterward, it reacquires wport->lock, and
1933 * checks for more work to do.
1934 *
1935 * If another thread calls pcm_output() while HW_BUSY is set, it
1936 * returns immediately, knowing that the thread that set HW_BUSY will
1937 * look for more work to do before returning.
1938 *
1939 * This has the advantage that port->lock is held for several short
1940 * periods instead of one long period. Also, when pcm_output is
1941 * called from base level, it reenables interrupts.
1942 */
1943
1944 static void pcm_output(vwsnd_dev_t *devc, int erflown, int nb)
1945 {
1946 vwsnd_port_t *wport = &devc->wport;
1947 const int hwmax = wport->hwbuf_max;
1948 const int hwsize = wport->hwbuf_size;
1949 const int swsize = wport->swbuf_size;
1950 const int fragsize = wport->hw_fragsize;
1951 unsigned long iflags;
1952
1953 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc, erflown, nb);
1954 spin_lock_irqsave(&wport->lock, iflags);
1955 if (erflown)
1956 wport->flags |= ERFLOWN;
1957 (void) __swb_inc_u(wport, nb);
1958 if (wport->flags & HW_BUSY) {
1959 spin_unlock_irqrestore(&wport->lock, iflags);
1960 DBGPV("returning: HW BUSY\n");
1961 return;
1962 }
1963 if (wport->flags & DISABLED) {
1964 spin_unlock_irqrestore(&wport->lock, iflags);
1965 DBGPV("returning: DISABLED\n");
1966 return;
1967 }
1968 wport->flags |= HW_BUSY;
1969 while (1) {
1970 int swptr, hwptr, hw_avail, sw_avail, swidx;
1971 vwsnd_port_hwstate_t hwstate = wport->hwstate;
1972 vwsnd_port_swstate_t swstate = wport->swstate;
1973 int hw_unavail;
1974 ustmsc_t ustmsc;
1975
1976 hwptr = li_read_hwptr(&wport->chan);
1977 swptr = li_read_swptr(&wport->chan);
1978 hw_unavail = (swptr - hwptr + hwsize) % hwsize;
1979 hw_avail = (hwmax - hw_unavail) & -fragsize;
1980 sw_avail = wport->swb_i_avail & -fragsize;
1981 if (sw_avail && swstate == SW_RUN) {
1982 if (wport->flags & ERFLOWN) {
1983 wport->flags &= ~ERFLOWN;
1984 }
1985 } else if (swstate == SW_INITIAL ||
1986 swstate == SW_OFF ||
1987 (swstate == SW_DRAIN &&
1988 !sw_avail &&
1989 (wport->flags & ERFLOWN))) {
1990 DBGP("stopping. hwstate = %d\n", hwstate);
1991 if (hwstate != HW_STOPPED) {
1992 li_deactivate_dma(&wport->chan);
1993 wport->hwstate = HW_STOPPED;
1994 }
1995 wake_up(&wport->queue);
1996 break;
1997 }
1998 if (!sw_avail || !hw_avail)
1999 break;
2000 spin_unlock_irqrestore(&wport->lock, iflags);
2001
2002 /*
2003 * We gave up the port lock, but we have the HW_BUSY flag.
2004 * Proceed without accessing any nonlocal state.
2005 * Do not exit the loop -- must check for more work.
2006 */
2007
2008 swidx = wport->swb_i_idx;
2009 nb = hw_avail;
2010 if (nb > sw_avail)
2011 nb = sw_avail;
2012 if (nb > hwsize - swptr)
2013 nb = hwsize - swptr; /* don't overflow hwbuf */
2014 if (nb > swsize - swidx)
2015 nb = swsize - swidx; /* don't overflow swbuf */
2016 ASSERT(nb > 0);
2017 if (nb % fragsize) {
2018 DBGP("nb = %d, fragsize = %d\n", nb, fragsize);
2019 DBGP("hw_avail = %d\n", hw_avail);
2020 DBGP("sw_avail = %d\n", sw_avail);
2021 DBGP("hwsize = %d, swptr = %d\n", hwsize, swptr);
2022 DBGP("swsize = %d, swidx = %d\n", swsize, swidx);
2023 }
2024 ASSERT(!(nb % fragsize));
2025 DBGPV("copying swb[%d..%d] to hwb[%d..%d]\n",
2026 swidx, swidx + nb, swptr, swptr + nb);
2027 pcm_copy_out(wport, swidx, swptr, nb);
2028 li_write_swptr(&wport->chan, (swptr + nb) % hwsize);
2029 spin_lock_irqsave(&wport->lock, iflags);
2030 if (hwstate == HW_STOPPED) {
2031 DBGPV("starting\n");
2032 li_activate_dma(&wport->chan);
2033 wport->hwstate = HW_RUNNING;
2034 li_read_USTMSC(&wport->chan, &ustmsc);
2035 ASSERT(wport->byte_count % wport->frame_size == 0);
2036 wport->MSC_offset = ustmsc.msc - wport->byte_count / wport->frame_size;
2037 }
2038 __swb_inc_i(wport, nb);
2039 wport->byte_count += nb;
2040 wport->frag_count += nb / fragsize;
2041 ASSERT(nb % fragsize == 0);
2042 wake_up(&wport->queue);
2043 }
2044 wport->flags &= ~HW_BUSY;
2045 spin_unlock_irqrestore(&wport->lock, iflags);
2046 DBGRV();
2047 }
2048
2049 /*
2050 * pcm_input() is called both from baselevel and from interrupt level.
2051 * This is where audio frames are copied out of the hardware-accessible
2052 * ring buffer.
2053 *
2054 * Locking note: The part of this routine that figures out what to do
2055 * holds rport->lock. The longer part releases rport->lock, but sets
2056 * rport->flags & HW_BUSY. Afterward, it reacquires rport->lock, and
2057 * checks for more work to do.
2058 *
2059 * If another thread calls pcm_input() while HW_BUSY is set, it
2060 * returns immediately, knowing that the thread that set HW_BUSY will
2061 * look for more work to do before returning.
2062 *
2063 * This has the advantage that port->lock is held for several short
2064 * periods instead of one long period. Also, when pcm_input is
2065 * called from base level, it reenables interrupts.
2066 */
2067
2068 static void pcm_input(vwsnd_dev_t *devc, int erflown, int nb)
2069 {
2070 vwsnd_port_t *rport = &devc->rport;
2071 const int hwmax = rport->hwbuf_max;
2072 const int hwsize = rport->hwbuf_size;
2073 const int swsize = rport->swbuf_size;
2074 const int fragsize = rport->hw_fragsize;
2075 unsigned long iflags;
2076
2077 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc, erflown, nb);
2078
2079 spin_lock_irqsave(&rport->lock, iflags);
2080 if (erflown)
2081 rport->flags |= ERFLOWN;
2082 (void) __swb_inc_u(rport, nb);
2083 if (rport->flags & HW_BUSY || !rport->swbuf) {
2084 spin_unlock_irqrestore(&rport->lock, iflags);
2085 DBGPV("returning: HW BUSY or !swbuf\n");
2086 return;
2087 }
2088 if (rport->flags & DISABLED) {
2089 spin_unlock_irqrestore(&rport->lock, iflags);
2090 DBGPV("returning: DISABLED\n");
2091 return;
2092 }
2093 rport->flags |= HW_BUSY;
2094 while (1) {
2095 int swptr, hwptr, hw_avail, sw_avail, swidx;
2096 vwsnd_port_hwstate_t hwstate = rport->hwstate;
2097 vwsnd_port_swstate_t swstate = rport->swstate;
2098
2099 hwptr = li_read_hwptr(&rport->chan);
2100 swptr = li_read_swptr(&rport->chan);
2101 hw_avail = (hwptr - swptr + hwsize) % hwsize & -fragsize;
2102 if (hw_avail > hwmax)
2103 hw_avail = hwmax;
2104 sw_avail = rport->swb_i_avail & -fragsize;
2105 if (swstate != SW_RUN) {
2106 DBGP("stopping. hwstate = %d\n", hwstate);
2107 if (hwstate != HW_STOPPED) {
2108 li_deactivate_dma(&rport->chan);
2109 rport->hwstate = HW_STOPPED;
2110 }
2111 wake_up(&rport->queue);
2112 break;
2113 }
2114 if (!sw_avail || !hw_avail)
2115 break;
2116 spin_unlock_irqrestore(&rport->lock, iflags);
2117
2118 /*
2119 * We gave up the port lock, but we have the HW_BUSY flag.
2120 * Proceed without accessing any nonlocal state.
2121 * Do not exit the loop -- must check for more work.
2122 */
2123
2124 swidx = rport->swb_i_idx;
2125 nb = hw_avail;
2126 if (nb > sw_avail)
2127 nb = sw_avail;
2128 if (nb > hwsize - swptr)
2129 nb = hwsize - swptr; /* don't overflow hwbuf */
2130 if (nb > swsize - swidx)
2131 nb = swsize - swidx; /* don't overflow swbuf */
2132 ASSERT(nb > 0);
2133 if (nb % fragsize) {
2134 DBGP("nb = %d, fragsize = %d\n", nb, fragsize);
2135 DBGP("hw_avail = %d\n", hw_avail);
2136 DBGP("sw_avail = %d\n", sw_avail);
2137 DBGP("hwsize = %d, swptr = %d\n", hwsize, swptr);
2138 DBGP("swsize = %d, swidx = %d\n", swsize, swidx);
2139 }
2140 ASSERT(!(nb % fragsize));
2141 DBGPV("copying hwb[%d..%d] to swb[%d..%d]\n",
2142 swptr, swptr + nb, swidx, swidx + nb);
2143 pcm_copy_in(rport, swidx, swptr, nb);
2144 li_write_swptr(&rport->chan, (swptr + nb) % hwsize);
2145 spin_lock_irqsave(&rport->lock, iflags);
2146 __swb_inc_i(rport, nb);
2147 rport->byte_count += nb;
2148 rport->frag_count += nb / fragsize;
2149 ASSERT(nb % fragsize == 0);
2150 wake_up(&rport->queue);
2151 }
2152 rport->flags &= ~HW_BUSY;
2153 spin_unlock_irqrestore(&rport->lock, iflags);
2154 DBGRV();
2155 }
2156
2157 /*
2158 * pcm_flush_frag() writes zero samples to fill the current fragment,
2159 * then flushes it to the hardware.
2160 *
2161 * It is only meaningful to flush output, not input.
2162 */
2163
2164 static void pcm_flush_frag(vwsnd_dev_t *devc)
2165 {
2166 vwsnd_port_t *wport = &devc->wport;
2167
2168 DBGPV("swstate = %d\n", wport->swstate);
2169 if (wport->swstate == SW_RUN) {
2170 int idx = wport->swb_u_idx;
2171 int end = (idx + wport->hw_fragsize - 1)
2172 >> wport->hw_fragshift
2173 << wport->hw_fragshift;
2174 int nb = end - idx;
2175 DBGPV("clearing %d bytes\n", nb);
2176 if (nb)
2177 memset(wport->swbuf + idx,
2178 (char) wport->zero_word,
2179 nb);
2180 wport->swstate = SW_DRAIN;
2181 pcm_output(devc, 0, nb);
2182 }
2183 DBGRV();
2184 }
2185
2186 /*
2187 * Wait for output to drain. This sleeps uninterruptibly because
2188 * there is nothing intelligent we can do if interrupted. This
2189 * means the process will be delayed in responding to the signal.
2190 */
2191
2192 static void pcm_write_sync(vwsnd_dev_t *devc)
2193 {
2194 vwsnd_port_t *wport = &devc->wport;
2195 DECLARE_WAITQUEUE(wait, current);
2196 unsigned long flags;
2197 vwsnd_port_hwstate_t hwstate;
2198
2199 DBGEV("(devc=0x%p)\n", devc);
2200 add_wait_queue(&wport->queue, &wait);
2201 while (1) {
2202 set_current_state(TASK_UNINTERRUPTIBLE);
2203 spin_lock_irqsave(&wport->lock, flags);
2204 {
2205 hwstate = wport->hwstate;
2206 }
2207 spin_unlock_irqrestore(&wport->lock, flags);
2208 if (hwstate == HW_STOPPED)
2209 break;
2210 schedule();
2211 }
2212 current->state = TASK_RUNNING;
2213 remove_wait_queue(&wport->queue, &wait);
2214 DBGPV("swstate = %d, hwstate = %d\n", wport->swstate, wport->hwstate);
2215 DBGRV();
2216 }
2217
2218 /*****************************************************************************/
2219 /* audio driver */
2220
2221 /*
2222 * seek on an audio device always fails.
2223 */
2224
2225 static void vwsnd_audio_read_intr(vwsnd_dev_t *devc, unsigned int status)
2226 {
2227 int overflown = status & LI_INTR_COMM1_OVERFLOW;
2228
2229 if (status & READ_INTR_MASK)
2230 pcm_input(devc, overflown, 0);
2231 }
2232
2233 static void vwsnd_audio_write_intr(vwsnd_dev_t *devc, unsigned int status)
2234 {
2235 int underflown = status & LI_INTR_COMM2_UNDERFLOW;
2236
2237 if (status & WRITE_INTR_MASK)
2238 pcm_output(devc, underflown, 0);
2239 }
2240
2241 static void vwsnd_audio_intr(int irq, void *dev_id, struct pt_regs *regs)
2242 {
2243 vwsnd_dev_t *devc = (vwsnd_dev_t *) dev_id;
2244 unsigned int status;
2245
2246 DBGEV("(irq=%d, dev_id=0x%p, regs=0x%p)\n", irq, dev_id, regs);
2247
2248 status = li_get_clear_intr_status(&devc->lith);
2249 vwsnd_audio_read_intr(devc, status);
2250 vwsnd_audio_write_intr(devc, status);
2251 }
2252
2253 static ssize_t vwsnd_audio_do_read(struct file *file,
2254 char *buffer,
2255 size_t count,
2256 loff_t *ppos)
2257 {
2258 vwsnd_dev_t *devc = file->private_data;
2259 vwsnd_port_t *rport = ((file->f_mode & FMODE_READ) ?
2260 &devc->rport : NULL);
2261 int ret, nb;
2262
2263 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2264 file, buffer, count, ppos);
2265
2266 if (!rport)
2267 return -EINVAL;
2268
2269 if (rport->swbuf == NULL) {
2270 vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2271 &devc->wport : NULL;
2272 ret = pcm_setup(devc, rport, wport);
2273 if (ret < 0)
2274 return ret;
2275 }
2276
2277 if (!access_ok(VERIFY_READ, buffer, count))
2278 return -EFAULT;
2279 ret = 0;
2280 while (count) {
2281 DECLARE_WAITQUEUE(wait, current);
2282 add_wait_queue(&rport->queue, &wait);
2283 while ((nb = swb_inc_u(rport, 0)) == 0) {
2284 DBGPV("blocking\n");
2285 set_current_state(TASK_INTERRUPTIBLE);
2286 if (rport->flags & DISABLED ||
2287 file->f_flags & O_NONBLOCK) {
2288 current->state = TASK_RUNNING;
2289 remove_wait_queue(&rport->queue, &wait);
2290 return ret ? ret : -EAGAIN;
2291 }
2292 schedule();
2293 if (signal_pending(current)) {
2294 current->state = TASK_RUNNING;
2295 remove_wait_queue(&rport->queue, &wait);
2296 return ret ? ret : -ERESTARTSYS;
2297 }
2298 }
2299 current->state = TASK_RUNNING;
2300 remove_wait_queue(&rport->queue, &wait);
2301 pcm_input(devc, 0, 0);
2302 /* nb bytes are available in userbuf. */
2303 if (nb > count)
2304 nb = count;
2305 DBGPV("nb = %d\n", nb);
2306 copy_to_user(buffer, rport->swbuf + rport->swb_u_idx, nb);
2307 (void) swb_inc_u(rport, nb);
2308 buffer += nb;
2309 count -= nb;
2310 ret += nb;
2311 }
2312 DBGPV("returning %d\n", ret);
2313 return ret;
2314 }
2315
2316 static ssize_t vwsnd_audio_read(struct file *file,
2317 char *buffer,
2318 size_t count,
2319 loff_t *ppos)
2320 {
2321 vwsnd_dev_t *devc = file->private_data;
2322 ssize_t ret;
2323
2324 down(&devc->io_sema);
2325 ret = vwsnd_audio_do_read(file, buffer, count, ppos);
2326 up(&devc->io_sema);
2327 return ret;
2328 }
2329
2330 static ssize_t vwsnd_audio_do_write(struct file *file,
2331 const char *buffer,
2332 size_t count,
2333 loff_t *ppos)
2334 {
2335 vwsnd_dev_t *devc = file->private_data;
2336 vwsnd_port_t *wport = ((file->f_mode & FMODE_WRITE) ?
2337 &devc->wport : NULL);
2338 int ret, nb;
2339
2340 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2341 file, buffer, count, ppos);
2342
2343 if (!wport)
2344 return -EINVAL;
2345
2346 if (wport->swbuf == NULL) {
2347 vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2348 &devc->rport : NULL;
2349 ret = pcm_setup(devc, rport, wport);
2350 if (ret < 0)
2351 return ret;
2352 }
2353 if (!access_ok(VERIFY_WRITE, buffer, count))
2354 return -EFAULT;
2355 ret = 0;
2356 while (count) {
2357 DECLARE_WAITQUEUE(wait, current);
2358 add_wait_queue(&wport->queue, &wait);
2359 while ((nb = swb_inc_u(wport, 0)) == 0) {
2360 set_current_state(TASK_INTERRUPTIBLE);
2361 if (wport->flags & DISABLED ||
2362 file->f_flags & O_NONBLOCK) {
2363 current->state = TASK_RUNNING;
2364 remove_wait_queue(&wport->queue, &wait);
2365 return ret ? ret : -EAGAIN;
2366 }
2367 schedule();
2368 if (signal_pending(current)) {
2369 current->state = TASK_RUNNING;
2370 remove_wait_queue(&wport->queue, &wait);
2371 return ret ? ret : -ERESTARTSYS;
2372 }
2373 }
2374 current->state = TASK_RUNNING;
2375 remove_wait_queue(&wport->queue, &wait);
2376 /* nb bytes are available in userbuf. */
2377 if (nb > count)
2378 nb = count;
2379 DBGPV("nb = %d\n", nb);
2380 copy_from_user(wport->swbuf + wport->swb_u_idx, buffer, nb);
2381 pcm_output(devc, 0, nb);
2382 buffer += nb;
2383 count -= nb;
2384 ret += nb;
2385 }
2386 DBGPV("returning %d\n", ret);
2387 return ret;
2388 }
2389
2390 static ssize_t vwsnd_audio_write(struct file *file,
2391 const char *buffer,
2392 size_t count,
2393 loff_t *ppos)
2394 {
2395 vwsnd_dev_t *devc = file->private_data;
2396 ssize_t ret;
2397
2398 down(&devc->io_sema);
2399 ret = vwsnd_audio_do_write(file, buffer, count, ppos);
2400 up(&devc->io_sema);
2401 return ret;
2402 }
2403
2404 /* No kernel lock - fine */
2405 static unsigned int vwsnd_audio_poll(struct file *file,
2406 struct poll_table_struct *wait)
2407 {
2408 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2409 vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2410 &devc->rport : NULL;
2411 vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2412 &devc->wport : NULL;
2413 unsigned int mask = 0;
2414
2415 DBGEV("(file=0x%p, wait=0x%p)\n", file, wait);
2416
2417 ASSERT(rport || wport);
2418 if (rport) {
2419 poll_wait(file, &rport->queue, wait);
2420 if (swb_inc_u(rport, 0))
2421 mask |= (POLLIN | POLLRDNORM);
2422 }
2423 if (wport) {
2424 poll_wait(file, &wport->queue, wait);
2425 if (wport->swbuf == NULL || swb_inc_u(wport, 0))
2426 mask |= (POLLOUT | POLLWRNORM);
2427 }
2428
2429 DBGPV("returning 0x%x\n", mask);
2430 return mask;
2431 }
2432
2433 static int vwsnd_audio_do_ioctl(struct inode *inode,
2434 struct file *file,
2435 unsigned int cmd,
2436 unsigned long arg)
2437 {
2438 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2439 vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2440 &devc->rport : NULL;
2441 vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2442 &devc->wport : NULL;
2443 vwsnd_port_t *aport = rport ? rport : wport;
2444 struct audio_buf_info buf_info;
2445 struct count_info info;
2446 unsigned long flags;
2447 int ival;
2448
2449
2450 DBGEV("(inode=0x%p, file=0x%p, cmd=0x%x, arg=0x%lx)\n",
2451 inode, file, cmd, arg);
2452 switch (cmd) {
2453 case OSS_GETVERSION: /* _SIOR ('M', 118, int) */
2454 DBGX("OSS_GETVERSION\n");
2455 ival = SOUND_VERSION;
2456 return put_user(ival, (int *) arg);
2457
2458 case SNDCTL_DSP_GETCAPS: /* _SIOR ('P',15, int) */
2459 DBGX("SNDCTL_DSP_GETCAPS\n");
2460 ival = DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER;
2461 return put_user(ival, (int *) arg);
2462
2463 case SNDCTL_DSP_GETFMTS: /* _SIOR ('P',11, int) */
2464 DBGX("SNDCTL_DSP_GETFMTS\n");
2465 ival = (AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW |
2466 AFMT_U8 | AFMT_S8);
2467 return put_user(ival, (int *) arg);
2468 break;
2469
2470 case SOUND_PCM_READ_RATE: /* _SIOR ('P', 2, int) */
2471 DBGX("SOUND_PCM_READ_RATE\n");
2472 ival = aport->sw_framerate;
2473 return put_user(ival, (int *) arg);
2474
2475 case SOUND_PCM_READ_CHANNELS: /* _SIOR ('P', 6, int) */
2476 DBGX("SOUND_PCM_READ_CHANNELS\n");
2477 ival = aport->sw_channels;
2478 return put_user(ival, (int *) arg);
2479
2480 case SNDCTL_DSP_SPEED: /* _SIOWR('P', 2, int) */
2481 if (get_user(ival, (int *) arg))
2482 return -EFAULT;
2483 DBGX("SNDCTL_DSP_SPEED %d\n", ival);
2484 if (ival) {
2485 if (aport->swstate != SW_INITIAL) {
2486 DBGX("SNDCTL_DSP_SPEED failed: swstate = %d\n",
2487 aport->swstate);
2488 return -EINVAL;
2489 }
2490 if (ival < MIN_SPEED)
2491 ival = MIN_SPEED;
2492 if (ival > MAX_SPEED)
2493 ival = MAX_SPEED;
2494 if (rport)
2495 rport->sw_framerate = ival;
2496 if (wport)
2497 wport->sw_framerate = ival;
2498 } else
2499 ival = aport->sw_framerate;
2500 return put_user(ival, (int *) arg);
2501
2502 case SNDCTL_DSP_STEREO: /* _SIOWR('P', 3, int) */
2503 if (get_user(ival, (int *) arg))
2504 return -EFAULT;
2505 DBGX("SNDCTL_DSP_STEREO %d\n", ival);
2506 if (ival != 0 && ival != 1)
2507 return -EINVAL;
2508 if (aport->swstate != SW_INITIAL)
2509 return -EINVAL;
2510 if (rport)
2511 rport->sw_channels = ival + 1;
2512 if (wport)
2513 wport->sw_channels = ival + 1;
2514 return put_user(ival, (int *) arg);
2515
2516 case SNDCTL_DSP_CHANNELS: /* _SIOWR('P', 6, int) */
2517 if (get_user(ival, (int *) arg))
2518 return -EFAULT;
2519 DBGX("SNDCTL_DSP_CHANNELS %d\n", ival);
2520 if (ival != 1 && ival != 2)
2521 return -EINVAL;
2522 if (aport->swstate != SW_INITIAL)
2523 return -EINVAL;
2524 if (rport)
2525 rport->sw_channels = ival;
2526 if (wport)
2527 wport->sw_channels = ival;
2528 return put_user(ival, (int *) arg);
2529
2530 case SNDCTL_DSP_GETBLKSIZE: /* _SIOWR('P', 4, int) */
2531 ival = pcm_setup(devc, rport, wport);
2532 if (ival < 0) {
2533 DBGX("SNDCTL_DSP_GETBLKSIZE failed, errno %d\n", ival);
2534 return ival;
2535 }
2536 ival = 1 << aport->sw_fragshift;
2537 DBGX("SNDCTL_DSP_GETBLKSIZE returning %d\n", ival);
2538 return put_user(ival, (int *) arg);
2539
2540 case SNDCTL_DSP_SETFRAGMENT: /* _SIOWR('P',10, int) */
2541 if (get_user(ival, (int *) arg))
2542 return -EFAULT;
2543 DBGX("SNDCTL_DSP_SETFRAGMENT %d:%d\n",
2544 ival >> 16, ival & 0xFFFF);
2545 if (aport->swstate != SW_INITIAL)
2546 return -EINVAL;
2547 {
2548 int sw_fragshift = ival & 0xFFFF;
2549 int sw_subdivshift = aport->sw_subdivshift;
2550 int hw_fragshift = sw_fragshift - sw_subdivshift;
2551 int sw_fragcount = (ival >> 16) & 0xFFFF;
2552 int hw_fragsize;
2553 if (hw_fragshift < MIN_FRAGSHIFT)
2554 hw_fragshift = MIN_FRAGSHIFT;
2555 if (hw_fragshift > MAX_FRAGSHIFT)
2556 hw_fragshift = MAX_FRAGSHIFT;
2557 sw_fragshift = hw_fragshift + aport->sw_subdivshift;
2558 hw_fragsize = 1 << hw_fragshift;
2559 if (sw_fragcount < MIN_FRAGCOUNT(hw_fragsize))
2560 sw_fragcount = MIN_FRAGCOUNT(hw_fragsize);
2561 if (sw_fragcount > MAX_FRAGCOUNT(hw_fragsize))
2562 sw_fragcount = MAX_FRAGCOUNT(hw_fragsize);
2563 DBGPV("sw_fragshift = %d\n", sw_fragshift);
2564 DBGPV("rport = 0x%p, wport = 0x%p\n", rport, wport);
2565 if (rport) {
2566 rport->sw_fragshift = sw_fragshift;
2567 rport->sw_fragcount = sw_fragcount;
2568 }
2569 if (wport) {
2570 wport->sw_fragshift = sw_fragshift;
2571 wport->sw_fragcount = sw_fragcount;
2572 }
2573 ival = sw_fragcount << 16 | sw_fragshift;
2574 }
2575 DBGX("SNDCTL_DSP_SETFRAGMENT returns %d:%d\n",
2576 ival >> 16, ival & 0xFFFF);
2577 return put_user(ival, (int *) arg);
2578
2579 case SNDCTL_DSP_SUBDIVIDE: /* _SIOWR('P', 9, int) */
2580 if (get_user(ival, (int *) arg))
2581 return -EFAULT;
2582 DBGX("SNDCTL_DSP_SUBDIVIDE %d\n", ival);
2583 if (aport->swstate != SW_INITIAL)
2584 return -EINVAL;
2585 {
2586 int subdivshift;
2587 int hw_fragshift, hw_fragsize, hw_fragcount;
2588 switch (ival) {
2589 case 1: subdivshift = 0; break;
2590 case 2: subdivshift = 1; break;
2591 case 4: subdivshift = 2; break;
2592 default: return -EINVAL;
2593 }
2594 hw_fragshift = aport->sw_fragshift - subdivshift;
2595 if (hw_fragshift < MIN_FRAGSHIFT ||
2596 hw_fragshift > MAX_FRAGSHIFT)
2597 return -EINVAL;
2598 hw_fragsize = 1 << hw_fragshift;
2599 hw_fragcount = aport->sw_fragcount >> subdivshift;
2600 if (hw_fragcount < MIN_FRAGCOUNT(hw_fragsize) ||
2601 hw_fragcount > MAX_FRAGCOUNT(hw_fragsize))
2602 return -EINVAL;
2603 if (rport)
2604 rport->sw_subdivshift = subdivshift;
2605 if (wport)
2606 wport->sw_subdivshift = subdivshift;
2607 }
2608 return 0;
2609
2610 case SNDCTL_DSP_SETFMT: /* _SIOWR('P',5, int) */
2611 if (get_user(ival, (int *) arg))
2612 return -EFAULT;
2613 DBGX("SNDCTL_DSP_SETFMT %d\n", ival);
2614 if (ival != AFMT_QUERY) {
2615 if (aport->swstate != SW_INITIAL) {
2616 DBGP("SETFMT failed, swstate = %d\n",
2617 aport->swstate);
2618 return -EINVAL;
2619 }
2620 switch (ival) {
2621 case AFMT_MU_LAW:
2622 case AFMT_A_LAW:
2623 case AFMT_U8:
2624 case AFMT_S8:
2625 case AFMT_S16_LE:
2626 if (rport)
2627 rport->sw_samplefmt = ival;
2628 if (wport)
2629 wport->sw_samplefmt = ival;
2630 break;
2631 default:
2632 return -EINVAL;
2633 }
2634 }
2635 ival = aport->sw_samplefmt;
2636 return put_user(ival, (int *) arg);
2637
2638 case SNDCTL_DSP_GETOSPACE: /* _SIOR ('P',12, audio_buf_info) */
2639 DBGXV("SNDCTL_DSP_GETOSPACE\n");
2640 if (!wport)
2641 return -EINVAL;
2642 ival = pcm_setup(devc, rport, wport);
2643 if (ival < 0)
2644 return ival;
2645 ival = swb_inc_u(wport, 0);
2646 buf_info.fragments = ival >> wport->sw_fragshift;
2647 buf_info.fragstotal = wport->sw_fragcount;
2648 buf_info.fragsize = 1 << wport->sw_fragshift;
2649 buf_info.bytes = ival;
2650 DBGXV("SNDCTL_DSP_GETOSPACE returns { %d %d %d %d }\n",
2651 buf_info.fragments, buf_info.fragstotal,
2652 buf_info.fragsize, buf_info.bytes);
2653 return copy_to_user((void *) arg, &buf_info, sizeof buf_info);
2654
2655 case SNDCTL_DSP_GETISPACE: /* _SIOR ('P',13, audio_buf_info) */
2656 DBGX("SNDCTL_DSP_GETISPACE\n");
2657 if (!rport)
2658 return -EINVAL;
2659 ival = pcm_setup(devc, rport, wport);
2660 if (ival < 0)
2661 return ival;
2662 ival = swb_inc_u(rport, 0);
2663 buf_info.fragments = ival >> rport->sw_fragshift;
2664 buf_info.fragstotal = rport->sw_fragcount;
2665 buf_info.fragsize = 1 << rport->sw_fragshift;
2666 buf_info.bytes = ival;
2667 DBGX("SNDCTL_DSP_GETISPACE returns { %d %d %d %d }\n",
2668 buf_info.fragments, buf_info.fragstotal,
2669 buf_info.fragsize, buf_info.bytes);
2670 return copy_to_user((void *) arg, &buf_info, sizeof buf_info);
2671
2672 case SNDCTL_DSP_NONBLOCK: /* _SIO ('P',14) */
2673 DBGX("SNDCTL_DSP_NONBLOCK\n");
2674 file->f_flags |= O_NONBLOCK;
2675 return 0;
2676
2677 case SNDCTL_DSP_RESET: /* _SIO ('P', 0) */
2678 DBGX("SNDCTL_DSP_RESET\n");
2679 /*
2680 * Nothing special needs to be done for input. Input
2681 * samples sit in swbuf, but it will be reinitialized
2682 * to empty when pcm_setup() is called.
2683 */
2684 if (wport && wport->swbuf) {
2685 wport->swstate = SW_INITIAL;
2686 pcm_output(devc, 0, 0);
2687 pcm_write_sync(devc);
2688 }
2689 pcm_shutdown(devc, rport, wport);
2690 return 0;
2691
2692 case SNDCTL_DSP_SYNC: /* _SIO ('P', 1) */
2693 DBGX("SNDCTL_DSP_SYNC\n");
2694 if (wport) {
2695 pcm_flush_frag(devc);
2696 pcm_write_sync(devc);
2697 }
2698 pcm_shutdown(devc, rport, wport);
2699 return 0;
2700
2701 case SNDCTL_DSP_POST: /* _SIO ('P', 8) */
2702 DBGX("SNDCTL_DSP_POST\n");
2703 if (!wport)
2704 return -EINVAL;
2705 pcm_flush_frag(devc);
2706 return 0;
2707
2708 case SNDCTL_DSP_GETIPTR: /* _SIOR ('P', 17, count_info) */
2709 DBGX("SNDCTL_DSP_GETIPTR\n");
2710 if (!rport)
2711 return -EINVAL;
2712 spin_lock_irqsave(&rport->lock, flags);
2713 {
2714 ustmsc_t ustmsc;
2715 if (rport->hwstate == HW_RUNNING) {
2716 ASSERT(rport->swstate == SW_RUN);
2717 li_read_USTMSC(&rport->chan, &ustmsc);
2718 info.bytes = ustmsc.msc - rport->MSC_offset;
2719 info.bytes *= rport->frame_size;
2720 } else {
2721 info.bytes = rport->byte_count;
2722 }
2723 info.blocks = rport->frag_count;
2724 info.ptr = 0; /* not implemented */
2725 rport->frag_count = 0;
2726 }
2727 spin_unlock_irqrestore(&rport->lock, flags);
2728 return copy_to_user((void *) arg, &info, sizeof info);
2729
2730 case SNDCTL_DSP_GETOPTR: /* _SIOR ('P',18, count_info) */
2731 DBGX("SNDCTL_DSP_GETOPTR\n");
2732 if (!wport)
2733 return -EINVAL;
2734 spin_lock_irqsave(&wport->lock, flags);
2735 {
2736 ustmsc_t ustmsc;
2737 if (wport->hwstate == HW_RUNNING) {
2738 ASSERT(wport->swstate == SW_RUN);
2739 li_read_USTMSC(&wport->chan, &ustmsc);
2740 info.bytes = ustmsc.msc - wport->MSC_offset;
2741 info.bytes *= wport->frame_size;
2742 } else {
2743 info.bytes = wport->byte_count;
2744 }
2745 info.blocks = wport->frag_count;
2746 info.ptr = 0; /* not implemented */
2747 wport->frag_count = 0;
2748 }
2749 spin_unlock_irqrestore(&wport->lock, flags);
2750 return copy_to_user((void *) arg, &info, sizeof info);
2751
2752 case SNDCTL_DSP_GETODELAY: /* _SIOR ('P', 23, int) */
2753 DBGX("SNDCTL_DSP_GETODELAY\n");
2754 if (!wport)
2755 return -EINVAL;
2756 spin_lock_irqsave(&wport->lock, flags);
2757 {
2758 int fsize = wport->frame_size;
2759 ival = wport->swb_i_avail / fsize;
2760 if (wport->hwstate == HW_RUNNING) {
2761 int swptr, hwptr, hwframes, hwbytes, hwsize;
2762 int totalhwbytes;
2763 ustmsc_t ustmsc;
2764
2765 hwsize = wport->hwbuf_size;
2766 swptr = li_read_swptr(&wport->chan);
2767 li_read_USTMSC(&wport->chan, &ustmsc);
2768 hwframes = ustmsc.msc - wport->MSC_offset;
2769 totalhwbytes = hwframes * fsize;
2770 hwptr = totalhwbytes % hwsize;
2771 hwbytes = (swptr - hwptr + hwsize) % hwsize;
2772 ival += hwbytes / fsize;
2773 }
2774 }
2775 spin_unlock_irqrestore(&wport->lock, flags);
2776 return put_user(ival, (int *) arg);
2777
2778 case SNDCTL_DSP_PROFILE: /* _SIOW ('P', 23, int) */
2779 DBGX("SNDCTL_DSP_PROFILE\n");
2780
2781 /*
2782 * Thomas Sailer explains SNDCTL_DSP_PROFILE
2783 * (private email, March 24, 1999):
2784 *
2785 * This gives the sound driver a hint on what it
2786 * should do with partial fragments
2787 * (i.e. fragments partially filled with write).
2788 * This can direct the driver to zero them or
2789 * leave them alone. But don't ask me what this
2790 * is good for, my driver just zeroes the last
2791 * fragment before the receiver stops, no idea
2792 * what good for any other behaviour could
2793 * be. Implementing it as NOP seems safe.
2794 */
2795
2796 break;
2797
2798 case SNDCTL_DSP_GETTRIGGER: /* _SIOR ('P',16, int) */
2799 DBGX("SNDCTL_DSP_GETTRIGGER\n");
2800 ival = 0;
2801 if (rport) {
2802 spin_lock_irqsave(&rport->lock, flags);
2803 {
2804 if (!(rport->flags & DISABLED))
2805 ival |= PCM_ENABLE_INPUT;
2806 }
2807 spin_unlock_irqrestore(&rport->lock, flags);
2808 }
2809 if (wport) {
2810 spin_lock_irqsave(&wport->lock, flags);
2811 {
2812 if (!(wport->flags & DISABLED))
2813 ival |= PCM_ENABLE_OUTPUT;
2814 }
2815 spin_unlock_irqrestore(&wport->lock, flags);
2816 }
2817 return put_user(ival, (int *) arg);
2818
2819 case SNDCTL_DSP_SETTRIGGER: /* _SIOW ('P',16, int) */
2820 if (get_user(ival, (int *) arg))
2821 return -EFAULT;
2822 DBGX("SNDCTL_DSP_SETTRIGGER %d\n", ival);
2823
2824 /*
2825 * If user is disabling I/O and port is not in initial
2826 * state, fail with EINVAL.
2827 */
2828
2829 if (((rport && !(ival & PCM_ENABLE_INPUT)) ||
2830 (wport && !(ival & PCM_ENABLE_OUTPUT))) &&
2831 aport->swstate != SW_INITIAL)
2832 return -EINVAL;
2833
2834 if (rport) {
2835 vwsnd_port_hwstate_t hwstate;
2836 spin_lock_irqsave(&rport->lock, flags);
2837 {
2838 hwstate = rport->hwstate;
2839 if (ival & PCM_ENABLE_INPUT)
2840 rport->flags &= ~DISABLED;
2841 else
2842 rport->flags |= DISABLED;
2843 }
2844 spin_unlock_irqrestore(&rport->lock, flags);
2845 if (hwstate != HW_RUNNING && ival & PCM_ENABLE_INPUT) {
2846
2847 if (rport->swstate == SW_INITIAL)
2848 pcm_setup(devc, rport, wport);
2849 else
2850 li_activate_dma(&rport->chan);
2851 }
2852 }
2853 if (wport) {
2854 vwsnd_port_flags_t pflags;
2855 spin_lock_irqsave(&wport->lock, flags);
2856 {
2857 pflags = wport->flags;
2858 if (ival & PCM_ENABLE_OUTPUT)
2859 wport->flags &= ~DISABLED;
2860 else
2861 wport->flags |= DISABLED;
2862 }
2863 spin_unlock_irqrestore(&wport->lock, flags);
2864 if (pflags & DISABLED && ival & PCM_ENABLE_OUTPUT) {
2865 if (wport->swstate == SW_RUN)
2866 pcm_output(devc, 0, 0);
2867 }
2868 }
2869 return 0;
2870
2871 default:
2872 DBGP("unknown ioctl 0x%x\n", cmd);
2873 return -EINVAL;
2874 }
2875 DBGP("unimplemented ioctl 0x%x\n", cmd);
2876 return -EINVAL;
2877 }
2878
2879 static int vwsnd_audio_ioctl(struct inode *inode,
2880 struct file *file,
2881 unsigned int cmd,
2882 unsigned long arg)
2883 {
2884 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2885 int ret;
2886
2887 down(&devc->io_sema);
2888 ret = vwsnd_audio_do_ioctl(inode, file, cmd, arg);
2889 up(&devc->io_sema);
2890 return ret;
2891 }
2892
2893 /* No mmap. */
2894
2895 static int vwsnd_audio_mmap(struct file *file, struct vm_area_struct *vma)
2896 {
2897 DBGE("(file=0x%p, vma=0x%p)\n", file, vma);
2898 return -ENODEV;
2899 }
2900
2901 /*
2902 * Open the audio device for read and/or write.
2903 *
2904 * Returns 0 on success, -errno on failure.
2905 */
2906
2907 static int vwsnd_audio_open(struct inode *inode, struct file *file)
2908 {
2909 vwsnd_dev_t *devc;
2910 dev_t minor = MINOR(inode->i_rdev);
2911 int sw_samplefmt;
2912
2913 DBGE("(inode=0x%p, file=0x%p)\n", inode, file);
2914
2915 INC_USE_COUNT;
2916 for (devc = vwsnd_dev_list; devc; devc = devc->next_dev)
2917 if ((devc->audio_minor & ~0x0F) == (minor & ~0x0F))
2918 break;
2919
2920 if (devc == NULL) {
2921 DEC_USE_COUNT;
2922 return -ENODEV;
2923 }
2924
2925 down(&devc->open_sema);
2926 while (devc->open_mode & file->f_mode) {
2927 up(&devc->open_sema);
2928 if (file->f_flags & O_NONBLOCK) {
2929 DEC_USE_COUNT;
2930 return -EBUSY;
2931 }
2932 interruptible_sleep_on(&devc->open_wait);
2933 if (signal_pending(current)) {
2934 DEC_USE_COUNT;
2935 return -ERESTARTSYS;
2936 }
2937 down(&devc->open_sema);
2938 }
2939 devc->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2940 up(&devc->open_sema);
2941
2942 /* get default sample format from minor number. */
2943
2944 sw_samplefmt = 0;
2945 if ((minor & 0xF) == SND_DEV_DSP)
2946 sw_samplefmt = AFMT_U8;
2947 else if ((minor & 0xF) == SND_DEV_AUDIO)
2948 sw_samplefmt = AFMT_MU_LAW;
2949 else if ((minor & 0xF) == SND_DEV_DSP16)
2950 sw_samplefmt = AFMT_S16_LE;
2951 else
2952 ASSERT(0);
2953
2954 /* Initialize vwsnd_ports. */
2955
2956 down(&devc->io_sema);
2957 {
2958 if (file->f_mode & FMODE_READ) {
2959 devc->rport.swstate = SW_INITIAL;
2960 devc->rport.flags = 0;
2961 devc->rport.sw_channels = 1;
2962 devc->rport.sw_samplefmt = sw_samplefmt;
2963 devc->rport.sw_framerate = 8000;
2964 devc->rport.sw_fragshift = DEFAULT_FRAGSHIFT;
2965 devc->rport.sw_fragcount = DEFAULT_FRAGCOUNT;
2966 devc->rport.sw_subdivshift = DEFAULT_SUBDIVSHIFT;
2967 devc->rport.byte_count = 0;
2968 devc->rport.frag_count = 0;
2969 }
2970 if (file->f_mode & FMODE_WRITE) {
2971 devc->wport.swstate = SW_INITIAL;
2972 devc->wport.flags = 0;
2973 devc->wport.sw_channels = 1;
2974 devc->wport.sw_samplefmt = sw_samplefmt;
2975 devc->wport.sw_framerate = 8000;
2976 devc->wport.sw_fragshift = DEFAULT_FRAGSHIFT;
2977 devc->wport.sw_fragcount = DEFAULT_FRAGCOUNT;
2978 devc->wport.sw_subdivshift = DEFAULT_SUBDIVSHIFT;
2979 devc->wport.byte_count = 0;
2980 devc->wport.frag_count = 0;
2981 }
2982 }
2983 up(&devc->io_sema);
2984
2985 file->private_data = devc;
2986 DBGRV();
2987 return 0;
2988 }
2989
2990 /*
2991 * Release (close) the audio device.
2992 */
2993
2994 static int vwsnd_audio_release(struct inode *inode, struct file *file)
2995 {
2996 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2997 vwsnd_port_t *wport = NULL, *rport = NULL;
2998 int err = 0;
2999
3000 lock_kernel();
3001 down(&devc->io_sema);
3002 {
3003 DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3004
3005 if (file->f_mode & FMODE_READ)
3006 rport = &devc->rport;
3007 if (file->f_mode & FMODE_WRITE) {
3008 wport = &devc->wport;
3009 pcm_flush_frag(devc);
3010 pcm_write_sync(devc);
3011 }
3012 pcm_shutdown(devc, rport, wport);
3013 if (rport)
3014 rport->swstate = SW_OFF;
3015 if (wport)
3016 wport->swstate = SW_OFF;
3017 }
3018 up(&devc->io_sema);
3019
3020 down(&devc->open_sema);
3021 {
3022 devc->open_mode &= ~file->f_mode;
3023 }
3024 up(&devc->open_sema);
3025 wake_up(&devc->open_wait);
3026 DEC_USE_COUNT;
3027 DBGR();
3028 unlock_kernel();
3029 return err;
3030 }
3031
3032 static struct file_operations vwsnd_audio_fops = {
3033 owner: THIS_MODULE,
3034 llseek: no_llseek,
3035 read: vwsnd_audio_read,
3036 write: vwsnd_audio_write,
3037 poll: vwsnd_audio_poll,
3038 ioctl: vwsnd_audio_ioctl,
3039 mmap: vwsnd_audio_mmap,
3040 open: vwsnd_audio_open,
3041 release: vwsnd_audio_release,
3042 };
3043
3044 /*****************************************************************************/
3045 /* mixer driver */
3046
3047 /* open the mixer device. */
3048
3049 static int vwsnd_mixer_open(struct inode *inode, struct file *file)
3050 {
3051 vwsnd_dev_t *devc;
3052
3053 DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3054
3055 INC_USE_COUNT;
3056 for (devc = vwsnd_dev_list; devc; devc = devc->next_dev)
3057 if (devc->mixer_minor == MINOR(inode->i_rdev))
3058 break;
3059
3060 if (devc == NULL) {
3061 DEC_USE_COUNT;
3062 return -ENODEV;
3063 }
3064 file->private_data = devc;
3065 return 0;
3066 }
3067
3068 /* release (close) the mixer device. */
3069
3070 static int vwsnd_mixer_release(struct inode *inode, struct file *file)
3071 {
3072 DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3073 DEC_USE_COUNT;
3074 return 0;
3075 }
3076
3077 /* mixer_read_ioctl handles all read ioctls on the mixer device. */
3078
3079 static int mixer_read_ioctl(vwsnd_dev_t *devc, unsigned int nr, caddr_t arg)
3080 {
3081 int val = -1;
3082
3083 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc, nr, arg);
3084
3085 switch (nr) {
3086 case SOUND_MIXER_CAPS:
3087 val = SOUND_CAP_EXCL_INPUT;
3088 break;
3089
3090 case SOUND_MIXER_DEVMASK:
3091 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3092 SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_RECLEV);
3093 break;
3094
3095 case SOUND_MIXER_STEREODEVS:
3096 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3097 SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_RECLEV);
3098 break;
3099
3100 case SOUND_MIXER_OUTMASK:
3101 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3102 SOUND_MASK_MIC | SOUND_MASK_CD);
3103 break;
3104
3105 case SOUND_MIXER_RECMASK:
3106 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3107 SOUND_MASK_MIC | SOUND_MASK_CD);
3108 break;
3109
3110 case SOUND_MIXER_PCM:
3111 val = ad1843_get_gain(&devc->lith, &ad1843_gain_PCM);
3112 break;
3113
3114 case SOUND_MIXER_LINE:
3115 val = ad1843_get_gain(&devc->lith, &ad1843_gain_LINE);
3116 break;
3117
3118 case SOUND_MIXER_MIC:
3119 val = ad1843_get_gain(&devc->lith, &ad1843_gain_MIC);
3120 break;
3121
3122 case SOUND_MIXER_CD:
3123 val = ad1843_get_gain(&devc->lith, &ad1843_gain_CD);
3124 break;
3125
3126 case SOUND_MIXER_RECLEV:
3127 val = ad1843_get_gain(&devc->lith, &ad1843_gain_RECLEV);
3128 break;
3129
3130 case SOUND_MIXER_RECSRC:
3131 val = ad1843_get_recsrc(&devc->lith);
3132 break;
3133
3134 case SOUND_MIXER_OUTSRC:
3135 val = ad1843_get_outsrc(&devc->lith);
3136 break;
3137
3138 default:
3139 return -EINVAL;
3140 }
3141 return put_user(val, (int *) arg);
3142 }
3143
3144 /* mixer_write_ioctl handles all write ioctls on the mixer device. */
3145
3146 static int mixer_write_ioctl(vwsnd_dev_t *devc, unsigned int nr, caddr_t arg)
3147 {
3148 int val;
3149 int err;
3150
3151 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc, nr, arg);
3152
3153 err = get_user(val, (int *) arg);
3154 if (err)
3155 return -EFAULT;
3156 switch (nr) {
3157 case SOUND_MIXER_PCM:
3158 val = ad1843_set_gain(&devc->lith, &ad1843_gain_PCM, val);
3159 break;
3160
3161 case SOUND_MIXER_LINE:
3162 val = ad1843_set_gain(&devc->lith, &ad1843_gain_LINE, val);
3163 break;
3164
3165 case SOUND_MIXER_MIC:
3166 val = ad1843_set_gain(&devc->lith, &ad1843_gain_MIC, val);
3167 break;
3168
3169 case SOUND_MIXER_CD:
3170 val = ad1843_set_gain(&devc->lith, &ad1843_gain_CD, val);
3171 break;
3172
3173 case SOUND_MIXER_RECLEV:
3174 val = ad1843_set_gain(&devc->lith, &ad1843_gain_RECLEV, val);
3175 break;
3176
3177 case SOUND_MIXER_RECSRC:
3178 if (devc->rport.swbuf || devc->wport.swbuf)
3179 return -EBUSY; /* can't change recsrc while running */
3180 val = ad1843_set_recsrc(&devc->lith, val);
3181 break;
3182
3183 case SOUND_MIXER_OUTSRC:
3184 val = ad1843_set_outsrc(&devc->lith, val);
3185 break;
3186
3187 default:
3188 return -EINVAL;
3189 }
3190 if (val < 0)
3191 return val;
3192 return put_user(val, (int *) arg);
3193 }
3194
3195 /* This is the ioctl entry to the mixer driver. */
3196
3197 static int vwsnd_mixer_ioctl(struct inode *ioctl,
3198 struct file *file,
3199 unsigned int cmd,
3200 unsigned long arg)
3201 {
3202 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
3203 const unsigned int nrmask = _IOC_NRMASK << _IOC_NRSHIFT;
3204 const unsigned int nr = (cmd & nrmask) >> _IOC_NRSHIFT;
3205 int retval;
3206
3207 DBGEV("(devc=0x%p, cmd=0x%x, arg=0x%lx)\n", devc, cmd, arg);
3208
3209 down(&devc->mix_sema);
3210 {
3211 if ((cmd & ~nrmask) == MIXER_READ(0))
3212 retval = mixer_read_ioctl(devc, nr, (caddr_t) arg);
3213 else if ((cmd & ~nrmask) == MIXER_WRITE(0))
3214 retval = mixer_write_ioctl(devc, nr, (caddr_t) arg);
3215 else
3216 retval = -EINVAL;
3217 }
3218 up(&devc->mix_sema);
3219 return retval;
3220 }
3221
3222 static struct file_operations vwsnd_mixer_fops = {
3223 owner: THIS_MODULE,
3224 llseek: no_llseek,
3225 ioctl: vwsnd_mixer_ioctl,
3226 open: vwsnd_mixer_open,
3227 release: vwsnd_mixer_release,
3228 };
3229
3230 /*****************************************************************************/
3231 /* probe/attach/unload */
3232
3233 /* driver probe routine. Return nonzero if hardware is found. */
3234
3235 static int __init probe_vwsnd(struct address_info *hw_config)
3236 {
3237 lithium_t lith;
3238 int w;
3239 unsigned long later;
3240
3241 DBGEV("(hw_config=0x%p)\n", hw_config);
3242
3243 /* XXX verify lithium present (to prevent crash on non-vw) */
3244
3245 if (li_create(&lith, hw_config->io_base) != 0) {
3246 printk(KERN_WARNING "probe_vwsnd: can't map lithium\n");
3247 return 0;
3248 }
3249 later = jiffies + 2;
3250 li_writel(&lith, LI_HOST_CONTROLLER, LI_HC_LINK_ENABLE);
3251 do {
3252 w = li_readl(&lith, LI_HOST_CONTROLLER);
3253 } while (w == LI_HC_LINK_ENABLE && jiffies < later);
3254
3255 li_destroy(&lith);
3256
3257 DBGPV("HC = 0x%04x\n", w);
3258
3259 if ((w == LI_HC_LINK_ENABLE) || (w & LI_HC_LINK_CODEC)) {
3260
3261 /* This may indicate a beta machine with no audio,
3262 * or a future machine with different audio.
3263 * On beta-release 320 w/ no audio, HC == 0x4000 */
3264
3265 printk(KERN_WARNING "probe_vwsnd: audio codec not found\n");
3266 return 0;
3267 }
3268
3269 if (w & LI_HC_LINK_FAILURE) {
3270 printk(KERN_WARNING "probe_vwsnd: can't init audio codec\n");
3271 return 0;
3272 }
3273
3274 printk(KERN_INFO "probe_vwsnd: lithium audio found\n");
3275
3276 return 1;
3277 }
3278
3279 /*
3280 * driver attach routine. Initialize driver data structures and
3281 * initialize hardware. A new vwsnd_dev_t is allocated and put
3282 * onto the global list, vwsnd_dev_list.
3283 *
3284 * Return +minor_dev on success, -errno on failure.
3285 */
3286
3287 static int __init attach_vwsnd(struct address_info *hw_config)
3288 {
3289 vwsnd_dev_t *devc = NULL;
3290 int err = -ENOMEM;
3291
3292 DBGEV("(hw_config=0x%p)\n", hw_config);
3293
3294 devc = kmalloc(sizeof (vwsnd_dev_t), GFP_KERNEL);
3295 if (devc == NULL)
3296 goto fail0;
3297
3298 err = li_create(&devc->lith, hw_config->io_base);
3299 if (err)
3300 goto fail1;
3301
3302 init_waitqueue(&devc->open_wait);
3303
3304 devc->rport.hwbuf_size = HWBUF_SIZE;
3305 devc->rport.hwbuf_vaddr = __get_free_pages(GFP_KERNEL, HWBUF_ORDER);
3306 if (!devc->rport.hwbuf_vaddr)
3307 goto fail2;
3308 devc->rport.hwbuf = (caddr_t) devc->rport.hwbuf_vaddr;
3309 devc->rport.hwbuf_paddr = virt_to_phys(devc->rport.hwbuf);
3310
3311 /*
3312 * Quote from the NT driver:
3313 *
3314 * // WARNING!!! HACK to setup output dma!!!
3315 * // This is required because even on output there is some data
3316 * // trickling into the input DMA channel. This is a bug in the
3317 * // Lithium microcode.
3318 * // --sde
3319 *
3320 * We set the input side's DMA base address here. It will remain
3321 * valid until the driver is unloaded.
3322 */
3323
3324 li_writel(&devc->lith, LI_COMM1_BASE,
3325 devc->rport.hwbuf_paddr >> 8 | 1 << (37 - 8));
3326
3327 devc->wport.hwbuf_size = HWBUF_SIZE;
3328 devc->wport.hwbuf_vaddr = __get_free_pages(GFP_KERNEL, HWBUF_ORDER);
3329 if (!devc->wport.hwbuf_vaddr)
3330 goto fail3;
3331 devc->wport.hwbuf = (caddr_t) devc->wport.hwbuf_vaddr;
3332 devc->wport.hwbuf_paddr = virt_to_phys(devc->wport.hwbuf);
3333 DBGP("wport hwbuf = 0x%p\n", devc->wport.hwbuf);
3334
3335 DBGDO(shut_up++);
3336 err = ad1843_init(&devc->lith);
3337 DBGDO(shut_up--);
3338 if (err)
3339 goto fail4;
3340
3341 /* install interrupt handler */
3342
3343 err = request_irq(hw_config->irq, vwsnd_audio_intr, 0, "vwsnd", devc);
3344 if (err)
3345 goto fail5;
3346
3347 /* register this device's drivers. */
3348
3349 devc->audio_minor = register_sound_dsp(&vwsnd_audio_fops, -1);
3350 if ((err = devc->audio_minor) < 0) {
3351 DBGDO(printk(KERN_WARNING
3352 "attach_vwsnd: register_sound_dsp error %d\n",
3353 err));
3354 goto fail6;
3355 }
3356 devc->mixer_minor = register_sound_mixer(&vwsnd_mixer_fops,
3357 devc->audio_minor >> 4);
3358 if ((err = devc->mixer_minor) < 0) {
3359 DBGDO(printk(KERN_WARNING
3360 "attach_vwsnd: register_sound_mixer error %d\n",
3361 err));
3362 goto fail7;
3363 }
3364
3365 /* Squirrel away device indices for unload routine. */
3366
3367 hw_config->slots[0] = devc->audio_minor;
3368
3369 /* Initialize as much of *devc as possible */
3370
3371 devc->open_sema = MUTEX;
3372 devc->io_sema = MUTEX;
3373 devc->mix_sema = MUTEX;
3374 devc->open_mode = 0;
3375 devc->rport.lock = SPIN_LOCK_UNLOCKED;
3376 init_waitqueue(&devc->rport.queue);
3377 devc->rport.swstate = SW_OFF;
3378 devc->rport.hwstate = HW_STOPPED;
3379 devc->rport.flags = 0;
3380 devc->rport.swbuf = NULL;
3381 devc->wport.lock = SPIN_LOCK_UNLOCKED;
3382 init_waitqueue(&devc->wport.queue);
3383 devc->wport.swstate = SW_OFF;
3384 devc->wport.hwstate = HW_STOPPED;
3385 devc->wport.flags = 0;
3386 devc->wport.swbuf = NULL;
3387
3388 /* Success. Link us onto the local device list. */
3389
3390 devc->next_dev = vwsnd_dev_list;
3391 vwsnd_dev_list = devc;
3392 return devc->audio_minor;
3393
3394 /* So many ways to fail. Undo what we did. */
3395
3396 fail7:
3397 unregister_sound_dsp(devc->audio_minor);
3398 fail6:
3399 free_irq(hw_config->irq, devc);
3400 fail5:
3401 fail4:
3402 free_pages(devc->wport.hwbuf_vaddr, HWBUF_ORDER);
3403 fail3:
3404 free_pages(devc->rport.hwbuf_vaddr, HWBUF_ORDER);
3405 fail2:
3406 li_destroy(&devc->lith);
3407 fail1:
3408 kfree(devc);
3409 fail0:
3410 return err;
3411 }
3412
3413 static int __exit unload_vwsnd(struct address_info *hw_config)
3414 {
3415 vwsnd_dev_t *devc, **devcp;
3416
3417 DBGE("()\n");
3418
3419 devcp = &vwsnd_dev_list;
3420 while ((devc = *devcp)) {
3421 if (devc->audio_minor == hw_config->slots[0]) {
3422 *devcp = devc->next_dev;
3423 break;
3424 }
3425 devcp = &devc->next_dev;
3426 }
3427
3428 if (!devc)
3429 return -ENODEV;
3430
3431 unregister_sound_mixer(devc->mixer_minor);
3432 unregister_sound_dsp(devc->audio_minor);
3433 free_irq(hw_config->irq, devc);
3434 free_pages(devc->wport.hwbuf_vaddr, HWBUF_ORDER);
3435 free_pages(devc->rport.hwbuf_vaddr, HWBUF_ORDER);
3436 li_destroy(&devc->lith);
3437 kfree(devc);
3438
3439 return 0;
3440 }
3441
3442 /*****************************************************************************/
3443 /* initialization and loadable kernel module interface */
3444
3445 static struct address_info the_hw_config = {
3446 0xFF001000, /* lithium phys addr */
3447 CO_IRQ(CO_APIC_LI_AUDIO) /* irq */
3448 };
3449
3450 MODULE_DESCRIPTION("SGI Visual Workstation sound module");
3451 MODULE_AUTHOR("Bob Miller <kbob@sgi.com>");
3452
3453 static int __init init_vwsnd(void)
3454 {
3455 int err;
3456
3457 DBGXV("\n");
3458 DBGXV("sound::vwsnd::init_module()\n");
3459
3460 if(!probe_vwsnd(&the_hw_config))
3461 return -ENODEV;
3462 err = attach_vwsnd(&the_hw_config);
3463 if (err < 0)
3464 return err;
3465 return 0;
3466 }
3467
3468 static void __exit cleanup_vwsnd(void)
3469 {
3470 DBGX("sound::vwsnd::cleanup_module()\n");
3471
3472 unload_vwsnd(&the_hw_config);
3473 }
3474
3475 module_init(init_vwsnd);
3476 module_exit(cleanup_vwsnd);
3477