File: /usr/src/linux/drivers/video/aty128.h
1 /* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $
2 * linux/drivers/video/aty128.h
3 * Register definitions for ATI Rage128 boards
4 *
5 * Anthony Tong <atong@uiuc.edu>, 1999
6 * Brad Douglas <brad@neruo.com>, 2000
7 */
8
9 #ifndef REG_RAGE128_H
10 #define REG_RAGE128_H
11
12 #define CLOCK_CNTL_INDEX 0x0008
13 #define CLOCK_CNTL_DATA 0x000c
14 #define BIOS_0_SCRATCH 0x0010
15 #define BUS_CNTL 0x0030
16 #define GEN_INT_CNTL 0x0040
17 #define CRTC_GEN_CNTL 0x0050
18 #define CRTC_EXT_CNTL 0x0054
19 #define DAC_CNTL 0x0058
20 #define I2C_CNTL_1 0x0094
21 #define PALETTE_INDEX 0x00b0
22 #define PALETTE_DATA 0x00b4
23 #define CONFIG_CNTL 0x00e0
24 #define GEN_RESET_CNTL 0x00f0
25 #define CONFIG_MEMSIZE 0x00f8
26 #define MEM_CNTL 0x0140
27 #define AGP_BASE 0x0170
28 #define AGP_CNTL 0x0174
29 #define AGP_APER_OFFSET 0x0178
30 #define PCI_GART_PAGE 0x017c
31 #define PC_NGUI_MODE 0x0180
32 #define PC_NGUI_CTLSTAT 0x0184
33 #define MPP_TB_CONFIG 0x01C0
34 #define MPP_GP_CONFIG 0x01C8
35 #define VIPH_CONTROL 0x01D0
36 #define CRTC_H_TOTAL_DISP 0x0200
37 #define CRTC_H_SYNC_STRT_WID 0x0204
38 #define CRTC_V_TOTAL_DISP 0x0208
39 #define CRTC_V_SYNC_STRT_WID 0x020c
40 #define CRTC_OFFSET 0x0224
41 #define CRTC_OFFSET_CNTL 0x0228
42 #define CRTC_PITCH 0x022c
43 #define OVR_CLR 0x0230
44 #define OVR_WID_LEFT_RIGHT 0x0234
45 #define OVR_WID_TOP_BOTTOM 0x0238
46 #define LVDS_GEN_CNTL 0x02d0
47 #define DDA_CONFIG 0x02e0
48 #define DDA_ON_OFF 0x02e4
49 #define VGA_DDA_CONFIG 0x02e8
50 #define VGA_DDA_ON_OFF 0x02ec
51 #define OV0_SCALE_CNTL 0x0420
52 #define SUBPIC_CNTL 0x0540
53 #define PM4_BUFFER_OFFSET 0x0700
54 #define PM4_BUFFER_CNTL 0x0704
55 #define PM4_BUFFER_WM_CNTL 0x0708
56 #define PM4_BUFFER_DL_RPTR_ADDR 0x070c
57 #define PM4_BUFFER_DL_RPTR 0x0710
58 #define PM4_BUFFER_DL_WPTR 0x0714
59 #define PM4_VC_FPU_SETUP 0x071c
60 #define PM4_FPU_CNTL 0x0720
61 #define PM4_VC_FORMAT 0x0724
62 #define PM4_VC_CNTL 0x0728
63 #define PM4_VC_I01 0x072c
64 #define PM4_VC_VLOFF 0x0730
65 #define PM4_VC_VLSIZE 0x0734
66 #define PM4_IW_INDOFF 0x0738
67 #define PM4_IW_INDSIZE 0x073c
68 #define PM4_FPU_FPX0 0x0740
69 #define PM4_FPU_FPY0 0x0744
70 #define PM4_FPU_FPX1 0x0748
71 #define PM4_FPU_FPY1 0x074c
72 #define PM4_FPU_FPX2 0x0750
73 #define PM4_FPU_FPY2 0x0754
74 #define PM4_FPU_FPY3 0x0758
75 #define PM4_FPU_FPY4 0x075c
76 #define PM4_FPU_FPY5 0x0760
77 #define PM4_FPU_FPY6 0x0764
78 #define PM4_FPU_FPR 0x0768
79 #define PM4_FPU_FPG 0x076c
80 #define PM4_FPU_FPB 0x0770
81 #define PM4_FPU_FPA 0x0774
82 #define PM4_FPU_INTXY0 0x0780
83 #define PM4_FPU_INTXY1 0x0784
84 #define PM4_FPU_INTXY2 0x0788
85 #define PM4_FPU_INTARGB 0x078c
86 #define PM4_FPU_FPTWICEAREA 0x0790
87 #define PM4_FPU_DMAJOR01 0x0794
88 #define PM4_FPU_DMAJOR12 0x0798
89 #define PM4_FPU_DMAJOR02 0x079c
90 #define PM4_FPU_STAT 0x07a0
91 #define PM4_STAT 0x07b8
92 #define PM4_TEST_CNTL 0x07d0
93 #define PM4_MICROCODE_ADDR 0x07d4
94 #define PM4_MICROCODE_RADDR 0x07d8
95 #define PM4_MICROCODE_DATAH 0x07dc
96 #define PM4_MICROCODE_DATAL 0x07e0
97 #define PM4_CMDFIFO_ADDR 0x07e4
98 #define PM4_CMDFIFO_DATAH 0x07e8
99 #define PM4_CMDFIFO_DATAL 0x07ec
100 #define PM4_BUFFER_ADDR 0x07f0
101 #define PM4_BUFFER_DATAH 0x07f4
102 #define PM4_BUFFER_DATAL 0x07f8
103 #define PM4_MICRO_CNTL 0x07fc
104 #define CAP0_TRIG_CNTL 0x0950
105 #define CAP1_TRIG_CNTL 0x09c0
106
107 /******************************************************************************
108 * GUI Block Memory Mapped Registers *
109 * These registers are FIFOed. *
110 *****************************************************************************/
111 #define PM4_FIFO_DATA_EVEN 0x1000
112 #define PM4_FIFO_DATA_ODD 0x1004
113
114 #define DST_OFFSET 0x1404
115 #define DST_PITCH 0x1408
116 #define DST_WIDTH 0x140c
117 #define DST_HEIGHT 0x1410
118 #define SRC_X 0x1414
119 #define SRC_Y 0x1418
120 #define DST_X 0x141c
121 #define DST_Y 0x1420
122 #define SRC_PITCH_OFFSET 0x1428
123 #define DST_PITCH_OFFSET 0x142c
124 #define SRC_Y_X 0x1434
125 #define DST_Y_X 0x1438
126 #define DST_HEIGHT_WIDTH 0x143c
127 #define DP_GUI_MASTER_CNTL 0x146c
128 #define BRUSH_SCALE 0x1470
129 #define BRUSH_Y_X 0x1474
130 #define DP_BRUSH_BKGD_CLR 0x1478
131 #define DP_BRUSH_FRGD_CLR 0x147c
132 #define DST_WIDTH_X 0x1588
133 #define DST_HEIGHT_WIDTH_8 0x158c
134 #define SRC_X_Y 0x1590
135 #define DST_X_Y 0x1594
136 #define DST_WIDTH_HEIGHT 0x1598
137 #define DST_WIDTH_X_INCY 0x159c
138 #define DST_HEIGHT_Y 0x15a0
139 #define DST_X_SUB 0x15a4
140 #define DST_Y_SUB 0x15a8
141 #define SRC_OFFSET 0x15ac
142 #define SRC_PITCH 0x15b0
143 #define DST_HEIGHT_WIDTH_BW 0x15b4
144 #define CLR_CMP_CNTL 0x15c0
145 #define CLR_CMP_CLR_SRC 0x15c4
146 #define CLR_CMP_CLR_DST 0x15c8
147 #define CLR_CMP_MASK 0x15cc
148 #define DP_SRC_FRGD_CLR 0x15d8
149 #define DP_SRC_BKGD_CLR 0x15dc
150 #define DST_BRES_ERR 0x1628
151 #define DST_BRES_INC 0x162c
152 #define DST_BRES_DEC 0x1630
153 #define DST_BRES_LNTH 0x1634
154 #define DST_BRES_LNTH_SUB 0x1638
155 #define SC_LEFT 0x1640
156 #define SC_RIGHT 0x1644
157 #define SC_TOP 0x1648
158 #define SC_BOTTOM 0x164c
159 #define SRC_SC_RIGHT 0x1654
160 #define SRC_SC_BOTTOM 0x165c
161 #define GUI_DEBUG0 0x16a0
162 #define GUI_DEBUG1 0x16a4
163 #define GUI_TIMEOUT 0x16b0
164 #define GUI_TIMEOUT0 0x16b4
165 #define GUI_TIMEOUT1 0x16b8
166 #define GUI_PROBE 0x16bc
167 #define DP_CNTL 0x16c0
168 #define DP_DATATYPE 0x16c4
169 #define DP_MIX 0x16c8
170 #define DP_WRITE_MASK 0x16cc
171 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
172 #define DEFAULT_OFFSET 0x16e0
173 #define DEFAULT_PITCH 0x16e4
174 #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8
175 #define SC_TOP_LEFT 0x16ec
176 #define SC_BOTTOM_RIGHT 0x16f0
177 #define SRC_SC_BOTTOM_RIGHT 0x16f4
178 #define WAIT_UNTIL 0x1720
179 #define CACHE_CNTL 0x1724
180 #define GUI_STAT 0x1740
181 #define PC_GUI_MODE 0x1744
182 #define PC_GUI_CTLSTAT 0x1748
183 #define PC_DEBUG_MODE 0x1760
184 #define BRES_DST_ERR_DEC 0x1780
185 #define TRAIL_BRES_T12_ERR_DEC 0x1784
186 #define TRAIL_BRES_T12_INC 0x1788
187 #define DP_T12_CNTL 0x178c
188 #define DST_BRES_T1_LNTH 0x1790
189 #define DST_BRES_T2_LNTH 0x1794
190 #define SCALE_SRC_HEIGHT_WIDTH 0x1994
191 #define SCALE_OFFSET_0 0x1998
192 #define SCALE_PITCH 0x199c
193 #define SCALE_X_INC 0x19a0
194 #define SCALE_Y_INC 0x19a4
195 #define SCALE_HACC 0x19a8
196 #define SCALE_VACC 0x19ac
197 #define SCALE_DST_X_Y 0x19b0
198 #define SCALE_DST_HEIGHT_WIDTH 0x19b4
199 #define SCALE_3D_CNTL 0x1a00
200 #define SCALE_3D_DATATYPE 0x1a20
201 #define SETUP_CNTL 0x1bc4
202 #define SOLID_COLOR 0x1bc8
203 #define WINDOW_XY_OFFSET 0x1bcc
204 #define DRAW_LINE_POINT 0x1bd0
205 #define SETUP_CNTL_PM4 0x1bd4
206 #define DST_PITCH_OFFSET_C 0x1c80
207 #define DP_GUI_MASTER_CNTL_C 0x1c84
208 #define SC_TOP_LEFT_C 0x1c88
209 #define SC_BOTTOM_RIGHT_C 0x1c8c
210
211 #define CLR_CMP_MASK_3D 0x1A28
212 #define MISC_3D_STATE_CNTL_REG 0x1CA0
213 #define MC_SRC1_CNTL 0x19D8
214 #define TEX_CNTL 0x1800
215
216 /* CONSTANTS */
217 #define GUI_ACTIVE 0x80000000
218 #define ENGINE_IDLE 0x0
219
220 #define PLL_WR_EN 0x00000080
221
222 #define CLK_PIN_CNTL 0x0001
223 #define PPLL_CNTL 0x0002
224 #define PPLL_REF_DIV 0x0003
225 #define PPLL_DIV_0 0x0004
226 #define PPLL_DIV_1 0x0005
227 #define PPLL_DIV_2 0x0006
228 #define PPLL_DIV_3 0x0007
229 #define VCLK_ECP_CNTL 0x0008
230 #define HTOTAL_CNTL 0x0009
231 #define X_MPLL_REF_FB_DIV 0x000a
232 #define XPLL_CNTL 0x000b
233 #define XDLL_CNTL 0x000c
234 #define XCLK_CNTL 0x000d
235 #define MPLL_CNTL 0x000e
236 #define MCLK_CNTL 0x000f
237 #define AGP_PLL_CNTL 0x0010
238 #define FCP_CNTL 0x0012
239 #define PLL_TEST_CNTL 0x0013
240
241 #define PPLL_RESET 0x01
242 #define PPLL_ATOMIC_UPDATE_EN 0x10000
243 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000
244 #define PPLL_REF_DIV_MASK 0x3FF
245 #define PPLL_FB3_DIV_MASK 0x7FF
246 #define PPLL_POST3_DIV_MASK 0x70000
247 #define PPLL_ATOMIC_UPDATE_R 0x8000
248 #define PPLL_ATOMIC_UPDATE_W 0x8000
249 #define MEM_CFG_TYPE_MASK 0x3
250 #define XCLK_SRC_SEL_MASK 0x7
251 #define XPLL_FB_DIV_MASK 0xFF00
252 #define X_MPLL_REF_DIV_MASK 0xFF
253
254 /* CRTC control values (CRTC_GEN_CNTL) */
255 #define CRTC_CSYNC_EN 0x00000010
256
257 #define CRTC_PIX_WIDTH_MASK 0x00000700
258 #define CRTC_PIX_WIDTH_4BPP 0x00000100
259 #define CRTC_PIX_WIDTH_8BPP 0x00000200
260 #define CRTC_PIX_WIDTH_15BPP 0x00000300
261 #define CRTC_PIX_WIDTH_16BPP 0x00000400
262 #define CRTC_PIX_WIDTH_24BPP 0x00000500
263 #define CRTC_PIX_WIDTH_32BPP 0x00000600
264
265 /* DAC_CNTL bit constants */
266 #define DAC_8BIT_EN 0x00000100
267 #define DAC_MASK 0xFF000000
268 #define DAC_BLANKING 0x00000004
269 #define DAC_RANGE_CNTL 0x00000003
270 #define DAC_RANGE_CNTL 0x00000003
271 #define DAC_PALETTE_ACCESS_CNTL 0x00000020
272 #define DAC_PDWN 0x00008000
273
274 /* GEN_RESET_CNTL bit constants */
275 #define SOFT_RESET_GUI 0x00000001
276 #define SOFT_RESET_VCLK 0x00000100
277 #define SOFT_RESET_PCLK 0x00000200
278 #define SOFT_RESET_ECP 0x00000400
279 #define SOFT_RESET_DISPENG_XCLK 0x00000800
280
281 /* PC_GUI_CTLSTAT bit constants */
282 #define PC_BUSY_INIT 0x10000000
283 #define PC_BUSY_GUI 0x20000000
284 #define PC_BUSY_NGUI 0x40000000
285 #define PC_BUSY 0x80000000
286
287 #define BUS_MASTER_DIS 0x00000040
288 #define PM4_BUFFER_CNTL_NONPM4 0x00000000
289
290 /* DP_DATATYPE bit constants */
291 #define DST_8BPP 0x00000002
292 #define DST_15BPP 0x00000003
293 #define DST_16BPP 0x00000004
294 #define DST_24BPP 0x00000005
295 #define DST_32BPP 0x00000006
296
297 #define BRUSH_SOLIDCOLOR 0x00000d00
298
299 /* DP_GUI_MASTER_CNTL bit constants */
300 #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
301 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
302 #define GMC_SRC_CLIP_DEFAULT 0x00000000
303 #define GMC_DST_CLIP_DEFAULT 0x00000000
304 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0
305 #define GMC_SRC_DSTCOLOR 0x00003000
306 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
307 #define GMC_DP_SRC_RECT 0x02000000
308 #define GMC_3D_FCN_EN_CLR 0x00000000
309 #define GMC_AUX_CLIP_CLEAR 0x20000000
310 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
311 #define GMC_WRITE_MASK_SET 0x40000000
312 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000
313
314 /* DP_GUI_MASTER_CNTL ROP3 named constants */
315 #define ROP3_PATCOPY 0x00f00000
316 #define ROP3_SRCCOPY 0x00cc0000
317
318 #define SRC_DSTCOLOR 0x00030000
319
320 /* DP_CNTL bit constants */
321 #define DST_X_RIGHT_TO_LEFT 0x00000000
322 #define DST_X_LEFT_TO_RIGHT 0x00000001
323 #define DST_Y_BOTTOM_TO_TOP 0x00000000
324 #define DST_Y_TOP_TO_BOTTOM 0x00000002
325 #define DST_X_MAJOR 0x00000000
326 #define DST_Y_MAJOR 0x00000004
327 #define DST_X_TILE 0x00000008
328 #define DST_Y_TILE 0x00000010
329 #define DST_LAST_PEL 0x00000020
330 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
331 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
332 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
333 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
334 #define DST_BRES_SIGN 0x00000100
335 #define DST_HOST_BIG_ENDIAN_EN 0x00000200
336 #define DST_POLYLINE_NONLAST 0x00008000
337 #define DST_RASTER_STALL 0x00010000
338 #define DST_POLY_EDGE 0x00040000
339
340 /* DP_MIX bit constants */
341 #define DP_SRC_RECT 0x00000200
342 #define DP_SRC_HOST 0x00000300
343 #define DP_SRC_HOST_BYTEALIGN 0x00000400
344
345 /* LVDS_GEN_CNTL constants */
346 #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
347 #define LVDS_BL_MOD_LEVEL_SHIFT 8
348 #define LVDS_BL_MOD_EN 0x00010000
349 #define LVDS_DIGION 0x00040000
350 #define LVDS_BLON 0x00080000
351
352 #endif /* REG_RAGE128_H */
353