File: /usr/src/linux/drivers/video/cyberfb.h
1 /*
2 * linux/arch/m68k/console/cvision.h -- CyberVision64 definitions for the
3 * text console driver.
4 *
5 * Copyright (c) 1998 Alan Bair
6 *
7 * This file is based on the initial port to Linux of grf_cvreg.h:
8 *
9 * Copyright (c) 1997 Antonio Santos
10 *
11 * The original work is from the NetBSD CyberVision 64 framebuffer driver
12 * and support files (grf_cv.c, grf_cvreg.h, ite_cv.c):
13 * Permission to use the source of this driver was obtained from the
14 * author Michael Teske by Alan Bair.
15 *
16 * Copyright (c) 1995 Michael Teske
17 *
18 * History:
19 *
20 *
21 *
22 * This file is subject to the terms and conditions of the GNU General Public
23 * License. See the file COPYING in the main directory of this archive
24 * for more details.
25 */
26
27 /* s3 commands */
28 #define S3_BITBLT 0xc011
29 #define S3_TWOPOINTLINE 0x2811
30 #define S3_FILLEDRECT 0x40b1
31
32 #define S3_FIFO_EMPTY 0x0400
33 #define S3_HDW_BUSY 0x0200
34
35 /* Enhanced register mapping (MMIO mode) */
36
37 #define S3_READ_SEL 0xbee8 /* offset f */
38 #define S3_MULT_MISC 0xbee8 /* offset e */
39 #define S3_ERR_TERM 0x92e8
40 #define S3_FRGD_COLOR 0xa6e8
41 #define S3_BKGD_COLOR 0xa2e8
42 #define S3_PIXEL_CNTL 0xbee8 /* offset a */
43 #define S3_FRGD_MIX 0xbae8
44 #define S3_BKGD_MIX 0xb6e8
45 #define S3_CUR_Y 0x82e8
46 #define S3_CUR_X 0x86e8
47 #define S3_DESTY_AXSTP 0x8ae8
48 #define S3_DESTX_DIASTP 0x8ee8
49 #define S3_MIN_AXIS_PCNT 0xbee8 /* offset 0 */
50 #define S3_MAJ_AXIS_PCNT 0x96e8
51 #define S3_CMD 0x9ae8
52 #define S3_GP_STAT 0x9ae8
53 #define S3_ADVFUNC_CNTL 0x4ae8
54 #define S3_WRT_MASK 0xaae8
55 #define S3_RD_MASK 0xaee8
56
57 /* Enhanced register mapping (Packed MMIO mode, write only) */
58 #define S3_ALT_CURXY 0x8100
59 #define S3_ALT_CURXY2 0x8104
60 #define S3_ALT_STEP 0x8108
61 #define S3_ALT_STEP2 0x810c
62 #define S3_ALT_ERR 0x8110
63 #define S3_ALT_CMD 0x8118
64 #define S3_ALT_MIX 0x8134
65 #define S3_ALT_PCNT 0x8148
66 #define S3_ALT_PAT 0x8168
67
68 /* Drawing modes */
69 #define S3_NOTCUR 0x0000
70 #define S3_LOGICALZERO 0x0001
71 #define S3_LOGICALONE 0x0002
72 #define S3_LEAVEASIS 0x0003
73 #define S3_NOTNEW 0x0004
74 #define S3_CURXORNEW 0x0005
75 #define S3_NOT_CURXORNEW 0x0006
76 #define S3_NEW 0x0007
77 #define S3_NOTCURORNOTNEW 0x0008
78 #define S3_CURORNOTNEW 0x0009
79 #define S3_NOTCURORNEW 0x000a
80 #define S3_CURORNEW 0x000b
81 #define S3_CURANDNEW 0x000c
82 #define S3_NOTCURANDNEW 0x000d
83 #define S3_CURANDNOTNEW 0x000e
84 #define S3_NOTCURANDNOTNEW 0x000f
85
86 #define S3_CRTC_ADR 0x03d4
87 #define S3_CRTC_DATA 0x03d5
88
89 #define S3_REG_LOCK2 0x39
90 #define S3_HGC_MODE 0x45
91
92 #define S3_HWGC_ORGX_H 0x46
93 #define S3_HWGC_ORGX_L 0x47
94 #define S3_HWGC_ORGY_H 0x48
95 #define S3_HWGC_ORGY_L 0x49
96 #define S3_HWGC_DX 0x4e
97 #define S3_HWGC_DY 0x4f
98
99 #define S3_LAW_CTL 0x58
100
101 /**************************************************/
102
103 /* support for a BitBlt operation. The op-codes are identical
104 to X11 GCs */
105 #define GRFBBOPclear 0x0 /* 0 */
106 #define GRFBBOPand 0x1 /* src AND dst */
107 #define GRFBBOPandReverse 0x2 /* src AND NOT dst */
108 #define GRFBBOPcopy 0x3 /* src */
109 #define GRFBBOPandInverted 0x4 /* NOT src AND dst */
110 #define GRFBBOPnoop 0x5 /* dst */
111 #define GRFBBOPxor 0x6 /* src XOR dst */
112 #define GRFBBOPor 0x7 /* src OR dst */
113 #define GRFBBOPnor 0x8 /* NOT src AND NOT dst */
114 #define GRFBBOPequiv 0x9 /* NOT src XOR dst */
115 #define GRFBBOPinvert 0xa /* NOT dst */
116 #define GRFBBOPorReverse 0xb /* src OR NOT dst */
117 #define GRFBBOPcopyInverted 0xc /* NOT src */
118 #define GRFBBOPorInverted 0xd /* NOT src OR dst */
119 #define GRFBBOPnand 0xe /* NOT src OR NOT dst */
120 #define GRFBBOPset 0xf /* 1 */
121
122
123 /* Write 16 Bit VGA register */
124 #define vgaw16(ba, reg, val) \
125 *((unsigned short *) (((volatile unsigned char *)ba)+reg)) = val
126
127 /*
128 * Defines for the used register addresses (mw)
129 *
130 * NOTE: There are some registers that have different addresses when
131 * in mono or color mode. We only support color mode, and thus
132 * some addresses won't work in mono-mode!
133 *
134 * General and VGA-registers taken from retina driver. Fixed a few
135 * bugs in it. (SR and GR read address is Port + 1, NOT Port)
136 *
137 */
138
139 /* General Registers: */
140 #define GREG_MISC_OUTPUT_R 0x03CC
141 #define GREG_MISC_OUTPUT_W 0x03C2
142 #define GREG_FEATURE_CONTROL_R 0x03CA
143 #define GREG_FEATURE_CONTROL_W 0x03DA
144 #define GREG_INPUT_STATUS0_R 0x03C2
145 #define GREG_INPUT_STATUS1_R 0x03DA
146
147 /* Setup Registers: */
148 #define SREG_OPTION_SELECT 0x0102
149 #define SREG_VIDEO_SUBS_ENABLE 0x46E8
150
151 /* Attribute Controller: */
152 #define ACT_ADDRESS 0x03C0
153 #define ACT_ADDRESS_R 0x03C1
154 #define ACT_ADDRESS_W 0x03C0
155 #define ACT_ADDRESS_RESET 0x03DA
156 #define ACT_ID_PALETTE0 0x00
157 #define ACT_ID_PALETTE1 0x01
158 #define ACT_ID_PALETTE2 0x02
159 #define ACT_ID_PALETTE3 0x03
160 #define ACT_ID_PALETTE4 0x04
161 #define ACT_ID_PALETTE5 0x05
162 #define ACT_ID_PALETTE6 0x06
163 #define ACT_ID_PALETTE7 0x07
164 #define ACT_ID_PALETTE8 0x08
165 #define ACT_ID_PALETTE9 0x09
166 #define ACT_ID_PALETTE10 0x0A
167 #define ACT_ID_PALETTE11 0x0B
168 #define ACT_ID_PALETTE12 0x0C
169 #define ACT_ID_PALETTE13 0x0D
170 #define ACT_ID_PALETTE14 0x0E
171 #define ACT_ID_PALETTE15 0x0F
172 #define ACT_ID_ATTR_MODE_CNTL 0x10
173 #define ACT_ID_OVERSCAN_COLOR 0x11
174 #define ACT_ID_COLOR_PLANE_ENA 0x12
175 #define ACT_ID_HOR_PEL_PANNING 0x13
176 #define ACT_ID_COLOR_SELECT 0x14
177
178 /* Graphics Controller: */
179 #define GCT_ADDRESS 0x03CE
180 #define GCT_ADDRESS_R 0x03CF
181 #define GCT_ADDRESS_W 0x03CF
182 #define GCT_ID_SET_RESET 0x00
183 #define GCT_ID_ENABLE_SET_RESET 0x01
184 #define GCT_ID_COLOR_COMPARE 0x02
185 #define GCT_ID_DATA_ROTATE 0x03
186 #define GCT_ID_READ_MAP_SELECT 0x04
187 #define GCT_ID_GRAPHICS_MODE 0x05
188 #define GCT_ID_MISC 0x06
189 #define GCT_ID_COLOR_XCARE 0x07
190 #define GCT_ID_BITMASK 0x08
191
192 /* Sequencer: */
193 #define SEQ_ADDRESS 0x03C4
194 #define SEQ_ADDRESS_R 0x03C5
195 #define SEQ_ADDRESS_W 0x03C5
196 #define SEQ_ID_RESET 0x00
197 #define SEQ_ID_CLOCKING_MODE 0x01
198 #define SEQ_ID_MAP_MASK 0x02
199 #define SEQ_ID_CHAR_MAP_SELECT 0x03
200 #define SEQ_ID_MEMORY_MODE 0x04
201 #define SEQ_ID_UNKNOWN1 0x05
202 #define SEQ_ID_UNKNOWN2 0x06
203 #define SEQ_ID_UNKNOWN3 0x07
204 /* S3 extensions */
205 #define SEQ_ID_UNLOCK_EXT 0x08
206 #define SEQ_ID_EXT_SEQ_REG9 0x09
207 #define SEQ_ID_BUS_REQ_CNTL 0x0A
208 #define SEQ_ID_EXT_MISC_SEQ 0x0B
209 #define SEQ_ID_UNKNOWN4 0x0C
210 #define SEQ_ID_EXT_SEQ 0x0D
211 #define SEQ_ID_UNKNOWN5 0x0E
212 #define SEQ_ID_UNKNOWN6 0x0F
213 #define SEQ_ID_MCLK_LO 0x10
214 #define SEQ_ID_MCLK_HI 0x11
215 #define SEQ_ID_DCLK_LO 0x12
216 #define SEQ_ID_DCLK_HI 0x13
217 #define SEQ_ID_CLKSYN_CNTL_1 0x14
218 #define SEQ_ID_CLKSYN_CNTL_2 0x15
219 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */
220 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */
221 #define SEQ_ID_RAMDAC_CNTL 0x18
222 #define SEQ_ID_MORE_MAGIC 0x1A
223
224 /* CRT Controller: */
225 #define CRT_ADDRESS 0x03D4
226 #define CRT_ADDRESS_R 0x03D5
227 #define CRT_ADDRESS_W 0x03D5
228 #define CRT_ID_HOR_TOTAL 0x00
229 #define CRT_ID_HOR_DISP_ENA_END 0x01
230 #define CRT_ID_START_HOR_BLANK 0x02
231 #define CRT_ID_END_HOR_BLANK 0x03
232 #define CRT_ID_START_HOR_RETR 0x04
233 #define CRT_ID_END_HOR_RETR 0x05
234 #define CRT_ID_VER_TOTAL 0x06
235 #define CRT_ID_OVERFLOW 0x07
236 #define CRT_ID_PRESET_ROW_SCAN 0x08
237 #define CRT_ID_MAX_SCAN_LINE 0x09
238 #define CRT_ID_CURSOR_START 0x0A
239 #define CRT_ID_CURSOR_END 0x0B
240 #define CRT_ID_START_ADDR_HIGH 0x0C
241 #define CRT_ID_START_ADDR_LOW 0x0D
242 #define CRT_ID_CURSOR_LOC_HIGH 0x0E
243 #define CRT_ID_CURSOR_LOC_LOW 0x0F
244 #define CRT_ID_START_VER_RETR 0x10
245 #define CRT_ID_END_VER_RETR 0x11
246 #define CRT_ID_VER_DISP_ENA_END 0x12
247 #define CRT_ID_SCREEN_OFFSET 0x13
248 #define CRT_ID_UNDERLINE_LOC 0x14
249 #define CRT_ID_START_VER_BLANK 0x15
250 #define CRT_ID_END_VER_BLANK 0x16
251 #define CRT_ID_MODE_CONTROL 0x17
252 #define CRT_ID_LINE_COMPARE 0x18
253 #define CRT_ID_GD_LATCH_RBACK 0x22
254 #define CRT_ID_ACT_TOGGLE_RBACK 0x24
255 #define CRT_ID_ACT_INDEX_RBACK 0x26
256 /* S3 extensions: S3 VGA Registers */
257 #define CRT_ID_DEVICE_HIGH 0x2D
258 #define CRT_ID_DEVICE_LOW 0x2E
259 #define CRT_ID_REVISION 0x2F
260 #define CRT_ID_CHIP_ID_REV 0x30
261 #define CRT_ID_MEMORY_CONF 0x31
262 #define CRT_ID_BACKWAD_COMP_1 0x32
263 #define CRT_ID_BACKWAD_COMP_2 0x33
264 #define CRT_ID_BACKWAD_COMP_3 0x34
265 #define CRT_ID_REGISTER_LOCK 0x35
266 #define CRT_ID_CONFIG_1 0x36
267 #define CRT_ID_CONFIG_2 0x37
268 #define CRT_ID_REGISTER_LOCK_1 0x38
269 #define CRT_ID_REGISTER_LOCK_2 0x39
270 #define CRT_ID_MISC_1 0x3A
271 #define CRT_ID_DISPLAY_FIFO 0x3B
272 #define CRT_ID_LACE_RETR_START 0x3C
273 /* S3 extensions: System Control Registers */
274 #define CRT_ID_SYSTEM_CONFIG 0x40
275 #define CRT_ID_BIOS_FLAG 0x41
276 #define CRT_ID_LACE_CONTROL 0x42
277 #define CRT_ID_EXT_MODE 0x43
278 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */
279 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46
280 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47
281 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
282 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
283 #define CRT_ID_HWGC_FG_STACK 0x4A
284 #define CRT_ID_HWGC_BG_STACK 0x4B
285 #define CRT_ID_HWGC_START_AD_HI 0x4C
286 #define CRT_ID_HWGC_START_AD_LO 0x4D
287 #define CRT_ID_HWGC_DSTART_X 0x4E
288 #define CRT_ID_HWGC_DSTART_Y 0x4F
289 /* S3 extensions: System Extension Registers */
290 #define CRT_ID_EXT_SYS_CNTL_1 0x50
291 #define CRT_ID_EXT_SYS_CNTL_2 0x51
292 #define CRT_ID_EXT_BIOS_FLAG_1 0x52
293 #define CRT_ID_EXT_MEM_CNTL_1 0x53
294 #define CRT_ID_EXT_MEM_CNTL_2 0x54
295 #define CRT_ID_EXT_DAC_CNTL 0x55
296 #define CRT_ID_EX_SYNC_1 0x56
297 #define CRT_ID_EX_SYNC_2 0x57
298 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */
299 #define CRT_ID_LAW_POS_HI 0x59
300 #define CRT_ID_LAW_POS_LO 0x5A
301 #define CRT_ID_GOUT_PORT 0x5C
302 #define CRT_ID_EXT_HOR_OVF 0x5D
303 #define CRT_ID_EXT_VER_OVF 0x5E
304 #define CRT_ID_EXT_MEM_CNTL_3 0x60
305 #define CRT_ID_EX_SYNC_3 0x63
306 #define CRT_ID_EXT_MISC_CNTL 0x65
307 #define CRT_ID_EXT_MISC_CNTL_1 0x66
308 #define CRT_ID_EXT_MISC_CNTL_2 0x67
309 #define CRT_ID_CONFIG_3 0x68
310 #define CRT_ID_EXT_SYS_CNTL_3 0x69
311 #define CRT_ID_EXT_SYS_CNTL_4 0x6A
312 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B
313 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C
314
315 /* Enhanced Commands Registers: */
316 #define ECR_SUBSYSTEM_STAT 0x42E8
317 #define ECR_SUBSYSTEM_CNTL 0x42E8
318 #define ECR_ADV_FUNC_CNTL 0x4AE8
319 #define ECR_CURRENT_Y_POS 0x82E8
320 #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */
321 #define ECR_CURRENT_X_POS 0x86E8
322 #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */
323 #define ECR_DEST_Y__AX_STEP 0x8AE8
324 #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */
325 #define ECR_DEST_X__DIA_STEP 0x8EE8
326 #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */
327 #define ECR_ERR_TERM 0x92E8
328 #define ECR_ERR_TERM2 0x92EA /* Trio64 only */
329 #define ECR_MAJ_AXIS_PIX_CNT 0x96E8
330 #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */
331 #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */
332 #define ECR_DRAW_CMD 0x9AE8
333 #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */
334 #define ECR_SHORT_STROKE 0x9EE8
335 #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */
336 #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */
337 #define ECR_BITPLANE_WRITE_MASK 0xAAE8
338 #define ECR_BITPLANE_READ_MASK 0xAEE8
339 #define ECR_COLOR_COMPARE 0xB2E8
340 #define ECR_BKGD_MIX 0xB6E8
341 #define ECR_FRGD_MIX 0xBAE8
342 #define ECR_READ_REG_DATA 0xBEE8
343 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00
344 #define ECR_ID_SCISSORS_TOP 0x01
345 #define ECR_ID_SCISSORS_LEFT 0x02
346 #define ECR_ID_SCISSORS_BUTTOM 0x03
347 #define ECR_ID_SCISSORS_RIGHT 0x04
348 #define ECR_ID_PIX_CNTL 0x0A
349 #define ECR_ID_MULT_CNTL_MISC_2 0x0D
350 #define ECR_ID_MULT_CNTL_MISC 0x0E
351 #define ECR_ID_READ_SEL 0x0F
352 #define ECR_PIX_TRANS 0xE2E8
353 #define ECR_PIX_TRANS_EXT 0xE2EA
354 #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */
355 #define ECR_PATTERN_X 0xEAEA /* Trio64 only */
356
357
358 /* Pass-through */
359 #define PASS_ADDRESS 0x40001
360 #define PASS_ADDRESS_W 0x40001
361
362 /* Video DAC */
363 #define VDAC_ADDRESS 0x03c8
364 #define VDAC_ADDRESS_W 0x03c8
365 #define VDAC_ADDRESS_R 0x03c7
366 #define VDAC_STATE 0x03c7
367 #define VDAC_DATA 0x03c9
368 #define VDAC_MASK 0x03c6
369
370
371 #define WGfx(ba, idx, val) \
372 do { wb_64(ba, GCT_ADDRESS, idx); wb_64(ba, GCT_ADDRESS_W , val); } while (0)
373
374 #define WSeq(ba, idx, val) \
375 do { wb_64(ba, SEQ_ADDRESS, idx); wb_64(ba, SEQ_ADDRESS_W , val); } while (0)
376
377 #define WCrt(ba, idx, val) \
378 do { wb_64(ba, CRT_ADDRESS, idx); wb_64(ba, CRT_ADDRESS_W , val); } while (0)
379
380 #define WAttr(ba, idx, val) \
381 do { \
382 unsigned char tmp;\
383 tmp = rb_64(ba, ACT_ADDRESS_RESET);\
384 wb_64(ba, ACT_ADDRESS_W, idx);\
385 wb_64(ba, ACT_ADDRESS_W, val);\
386 } while (0)
387
388 #define SetTextPlane(ba, m) \
389 do { \
390 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
391 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\
392 } while (0)
393
394 /* --------------------------------- */
395 /* prototypes */
396 /* --------------------------------- */
397
398 inline unsigned char RAttr(volatile unsigned char * board, short idx);
399 inline unsigned char RSeq(volatile unsigned char * board, short idx);
400 inline unsigned char RCrt(volatile unsigned char * board, short idx);
401 inline unsigned char RGfx(volatile unsigned char * board, short idx);
402 inline void cv64_write_port(unsigned short bits,
403 volatile unsigned char *board);
404 inline void cvscreen(int toggle, volatile unsigned char *board);
405 inline void gfx_on_off(int toggle, volatile unsigned char *board);
406 #if 0
407 unsigned short cv64_compute_clock(unsigned long freq);
408 int cv_has_4mb(volatile unsigned char * fb);
409 void cv64_board_init(void);
410 void cv64_load_video_mode(struct fb_var_screeninfo *video_mode);
411 #endif
412
413 void cvision_bitblt(u_short sx, u_short sy, u_short dx, u_short dy, u_short w,
414 u_short h);
415 void cvision_clear(u_short dx, u_short dy, u_short w, u_short h, u_short bg);
416