File: /usr/src/linux/drivers/video/matrox/matroxfb_base.h
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998,1999,2000 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 */
8 #ifndef __MATROXFB_H__
9 #define __MATROXFB_H__
10
11 /* general, but fairly heavy, debugging */
12 #undef MATROXFB_DEBUG
13
14 /* heavy debugging: */
15 /* -- logs putc[s], so everytime a char is displayed, it's logged */
16 #undef MATROXFB_DEBUG_HEAVY
17
18 /* This one _could_ cause infinite loops */
19 /* It _does_ cause lots and lots of messages during idle loops */
20 #undef MATROXFB_DEBUG_LOOP
21
22 /* Debug register calls, too? */
23 #undef MATROXFB_DEBUG_REG
24
25 /* Guard accelerator accesses with spin_lock_irqsave... */
26 #undef MATROXFB_USE_SPINLOCKS
27
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/errno.h>
32 #include <linux/string.h>
33 #include <linux/mm.h>
34 #include <linux/tty.h>
35 #include <linux/slab.h>
36 #include <linux/delay.h>
37 #include <linux/fb.h>
38 #include <linux/console.h>
39 #include <linux/selection.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/timer.h>
43 #include <linux/pci.h>
44 #include <linux/spinlock.h>
45
46 #include <asm/io.h>
47 #include <asm/unaligned.h>
48 #ifdef CONFIG_MTRR
49 #include <asm/mtrr.h>
50 #endif
51
52 #include <video/fbcon.h>
53 #include <video/fbcon-cfb4.h>
54 #include <video/fbcon-cfb8.h>
55 #include <video/fbcon-cfb16.h>
56 #include <video/fbcon-cfb24.h>
57 #include <video/fbcon-cfb32.h>
58
59 #if defined(CONFIG_FB_COMPAT_XPMAC)
60 #include <asm/vc_ioctl.h>
61 #endif
62 #if defined(CONFIG_PPC)
63 #include <asm/prom.h>
64 #include <asm/pci-bridge.h>
65 #include <video/macmodes.h>
66 #endif
67
68 /* always compile support for 32MB... It cost almost nothing */
69 #define CONFIG_FB_MATROX_32MB
70
71 #define FBCON_HAS_VGATEXT
72
73 #ifdef MATROXFB_DEBUG
74
75 #define DEBUG
76 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
77
78 #ifdef MATROXFB_DEBUG_HEAVY
79 #define DBG_HEAVY(x) DBG(x)
80 #else /* MATROXFB_DEBUG_HEAVY */
81 #define DBG_HEAVY(x) /* DBG_HEAVY */
82 #endif /* MATROXFB_DEBUG_HEAVY */
83
84 #ifdef MATROXFB_DEBUG_LOOP
85 #define DBG_LOOP(x) DBG(x)
86 #else /* MATROXFB_DEBUG_LOOP */
87 #define DBG_LOOP(x) /* DBG_LOOP */
88 #endif /* MATROXFB_DEBUG_LOOP */
89
90 #ifdef MATROXFB_DEBUG_REG
91 #define DBG_REG(x) DBG(x)
92 #else /* MATROXFB_DEBUG_REG */
93 #define DBG_REG(x) /* DBG_REG */
94 #endif /* MATROXFB_DEBUG_REG */
95
96 #else /* MATROXFB_DEBUG */
97
98 #define DBG(x) /* DBG */
99 #define DBG_HEAVY(x) /* DBG_HEAVY */
100 #define DBG_REG(x) /* DBG_REG */
101 #define DBG_LOOP(x) /* DBG_LOOP */
102
103 #endif /* MATROXFB_DEBUG */
104
105 #if !defined(__i386__) && !defined(__x86_64__)
106 #ifndef ioremap_nocache
107 #define ioremap_nocache(X,Y) ioremap(X,Y)
108 #endif
109 #endif
110
111 #if defined(__alpha__) || defined(__m68k__)
112 #define READx_WORKS
113 #define MEMCPYTOIO_WORKS
114 #else
115 #define READx_FAILS
116 /* recheck __ppc__, maybe that __ppc__ needs MEMCPYTOIO_WRITEL */
117 /* I benchmarked PII/350MHz with G200... MEMCPY, MEMCPYTOIO and WRITEL are on same speed ( <2% diff) */
118 /* so that means that G200 speed (or AGP speed?) is our limit... I do not have benchmark to test, how */
119 /* much of PCI bandwidth is used during transfers... */
120 #if defined(__i386__) || defined(__x86_64__)
121 #define MEMCPYTOIO_MEMCPY
122 #else
123 #define MEMCPYTOIO_WRITEL
124 #endif
125 #endif
126
127 #ifdef __sparc__
128 #error "Sorry, I have no idea how to do this on sparc... There is mapioaddr... With bus_type parameter..."
129 #endif
130
131 #if defined(__m68k__)
132 #define MAP_BUSTOVIRT
133 #else
134 #define MAP_IOREMAP
135 #endif
136
137 #ifdef DEBUG
138 #define dprintk(X...) printk(X)
139 #else
140 #define dprintk(X...)
141 #endif
142
143 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
144 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
145 #endif
146 #ifndef PCI_SS_VENDOR_ID_MATROX
147 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
148 #endif
149 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI
150 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520
151 #endif
152 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP
153 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521
154 #endif
155 #ifndef PCI_DEVICE_ID_MATROX_G100
156 #define PCI_DEVICE_ID_MATROX_G100 0x1000
157 #endif
158 #ifndef PCI_DEVICE_ID_MATROX_G100_AGP
159 #define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001
160 #endif
161 #ifndef PCI_DEVICE_ID_MATROX_G400_AGP
162 #define PCI_DEVICE_ID_MATROX_G400_AGP 0x0525
163 #endif
164
165 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
166 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
167 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
168 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
169 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
170 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
171 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
172 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
173 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
174 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
175 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
176 #endif
177
178 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
179 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
180 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
181
182 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
183
184 /* G100, G200 and Mystique have (almost) same DAC */
185 #undef NEED_DAC1064
186 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G100)
187 #define NEED_DAC1064 1
188 #endif
189
190 typedef struct {
191 u_int8_t* vaddr;
192 } vaddr_t;
193
194 #ifdef READx_WORKS
195 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
196 return readb(va.vaddr + offs);
197 }
198
199 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
200 return readw(va.vaddr + offs);
201 }
202
203 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
204 return readl(va.vaddr + offs);
205 }
206
207 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
208 writeb(value, va.vaddr + offs);
209 }
210
211 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
212 writew(value, va.vaddr + offs);
213 }
214
215 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
216 writel(value, va.vaddr + offs);
217 }
218 #else
219 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
220 return *(volatile u_int8_t*)(va.vaddr + offs);
221 }
222
223 static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) {
224 return *(volatile u_int16_t*)(va.vaddr + offs);
225 }
226
227 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
228 return *(volatile u_int32_t*)(va.vaddr + offs);
229 }
230
231 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
232 *(volatile u_int8_t*)(va.vaddr + offs) = value;
233 }
234
235 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
236 *(volatile u_int16_t*)(va.vaddr + offs) = value;
237 }
238
239 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
240 *(volatile u_int32_t*)(va.vaddr + offs) = value;
241 }
242 #endif
243
244 static inline void mga_memcpy_toio(vaddr_t va, unsigned int offs, const void* src, int len) {
245 #ifdef MEMCPYTOIO_WORKS
246 memcpy_toio(va.vaddr + offs, src, len);
247 #elif defined(MEMCPYTOIO_WRITEL)
248 #define srcd ((const u_int32_t*)src)
249 if (offs & 3) {
250 while (len >= 4) {
251 mga_writel(va, offs, get_unaligned(srcd++));
252 offs += 4;
253 len -= 4;
254 }
255 } else {
256 while (len >= 4) {
257 mga_writel(va, offs, *srcd++);
258 offs += 4;
259 len -= 4;
260 }
261 }
262 #undef srcd
263 if (len) {
264 u_int32_t tmp;
265
266 memcpy(&tmp, src, len);
267 mga_writel(va, offs, tmp);
268 }
269 #elif defined(MEMCPYTOIO_MEMCPY)
270 memcpy(va.vaddr + offs, src, len);
271 #else
272 #error "Sorry, do not know how to write block of data to device"
273 #endif
274 }
275
276 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
277 va->vaddr += offs;
278 }
279
280 static inline void* vaddr_va(vaddr_t va) {
281 return va.vaddr;
282 }
283
284 #define MGA_IOREMAP_NORMAL 0
285 #define MGA_IOREMAP_NOCACHE 1
286
287 #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
288 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
289 static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
290 #ifdef MAP_IOREMAP
291 if (flags & MGA_IOREMAP_NOCACHE)
292 virt->vaddr = ioremap_nocache(phys, size);
293 else
294 virt->vaddr = ioremap(phys, size);
295 #else
296 #ifdef MAP_BUSTOVIRT
297 virt->vaddr = bus_to_virt(phys);
298 #else
299 #error "Your architecture does not have neither ioremap nor bus_to_virt... Giving up"
300 #endif
301 #endif
302 return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
303 }
304
305 static inline void mga_iounmap(vaddr_t va) {
306 #ifdef MAP_IOREMAP
307 iounmap(va.vaddr);
308 #endif
309 }
310
311 struct my_timming {
312 unsigned int pixclock;
313 unsigned int HDisplay;
314 unsigned int HSyncStart;
315 unsigned int HSyncEnd;
316 unsigned int HTotal;
317 unsigned int VDisplay;
318 unsigned int VSyncStart;
319 unsigned int VSyncEnd;
320 unsigned int VTotal;
321 unsigned int sync;
322 int dblscan;
323 int interlaced;
324 unsigned int delay; /* CRTC delay */
325 };
326
327 struct matrox_pll_features {
328 unsigned int vco_freq_min;
329 unsigned int ref_freq;
330 unsigned int feed_div_min;
331 unsigned int feed_div_max;
332 unsigned int in_div_min;
333 unsigned int in_div_max;
334 unsigned int post_shift_max;
335 };
336
337 struct matroxfb_par
338 {
339 unsigned int final_bppShift;
340 unsigned int cmap_len;
341 struct {
342 unsigned int bytes;
343 unsigned int pixels;
344 unsigned int chunks;
345 } ydstorg;
346 void (*putc)(u_int32_t, u_int32_t, struct display*, int, int, int);
347 void (*putcs)(u_int32_t, u_int32_t, struct display*, const unsigned short*, int, int, int);
348 };
349
350 struct matrox_fb_info;
351
352 struct matrox_DAC1064_features {
353 u_int8_t xvrefctrl;
354 u_int8_t xmiscctrl;
355 unsigned int cursorimage;
356 };
357
358 struct matrox_accel_features {
359 int has_cacheflush;
360 };
361
362 /* current hardware status */
363 struct mavenregs {
364 u_int8_t regs[256];
365 int mode;
366 int vlines;
367 int xtal;
368 int fv;
369
370 u_int16_t htotal;
371 u_int16_t hcorr;
372 };
373
374 struct matrox_hw_state {
375 u_int32_t MXoptionReg;
376 unsigned char DACclk[6];
377 unsigned char DACreg[80];
378 unsigned char MiscOutReg;
379 unsigned char DACpal[768];
380 unsigned char CRTC[25];
381 unsigned char CRTCEXT[9];
382 unsigned char SEQ[5];
383 /* unused for MGA mode, but who knows... */
384 unsigned char GCTL[9];
385 /* unused for MGA mode, but who knows... */
386 unsigned char ATTR[21];
387
388 /* TVOut only */
389 struct mavenregs maven;
390
391 /* CRTC2 only */
392 /* u_int32_t TBD */
393 };
394
395 struct matrox_accel_data {
396 #ifdef CONFIG_FB_MATROX_MILLENIUM
397 unsigned char ramdac_rev;
398 #endif
399 u_int32_t m_dwg_rect;
400 u_int32_t m_opmode;
401 };
402
403 struct matrox_altout {
404 int (*compute)(void* altout_dev, struct my_timming* input, struct matrox_hw_state* state);
405 int (*program)(void* altout_dev, const struct matrox_hw_state* state);
406 int (*start)(void* altout_dev);
407 void (*incuse)(void* altout_dev);
408 void (*decuse)(void* altout_dev);
409 int (*setmode)(void* altout_dev, u_int32_t mode);
410 int (*getmode)(void* altout_dev, u_int32_t* mode);
411 };
412
413 struct matrox_switch;
414 struct matroxfb_driver;
415
416 struct matrox_fb_info {
417 /* fb_info must be first */
418 struct fb_info fbcon;
419
420 struct list_head next_fb;
421
422 int dead;
423 unsigned int usecount;
424
425 struct matroxfb_par curr;
426 struct matrox_hw_state hw1;
427 struct matrox_hw_state hw2;
428 struct matrox_hw_state* newhw;
429 struct matrox_hw_state* currenthw;
430
431 struct matrox_accel_data accel;
432
433 struct pci_dev* pcidev;
434
435 struct {
436 u_int32_t all;
437 u_int32_t ph;
438 u_int32_t sh;
439 } output;
440 struct matrox_altout* primout;
441 struct {
442 struct fb_info* info;
443 struct rw_semaphore lock;
444 } crtc2;
445 struct {
446 struct matrox_altout* output;
447 void* device;
448 struct rw_semaphore lock;
449 } altout;
450
451 #define MATROXFB_MAX_FB_DRIVERS 5
452 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
453 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
454 unsigned int drivers_count;
455
456 struct {
457 unsigned long base; /* physical */
458 vaddr_t vbase; /* CPU view */
459 unsigned int len;
460 unsigned int len_usable;
461 unsigned int len_maximum;
462 } video;
463
464 struct {
465 unsigned long base; /* physical */
466 vaddr_t vbase; /* CPU view */
467 unsigned int len;
468 } mmio;
469
470 unsigned int max_pixel_clock;
471
472 struct matrox_switch* hw_switch;
473 int currcon;
474 struct display* currcon_display;
475
476 struct {
477 struct matrox_pll_features pll;
478 struct matrox_DAC1064_features DAC1064;
479 struct matrox_accel_features accel;
480 } features;
481 struct {
482 spinlock_t DAC;
483 spinlock_t accel;
484 } lock;
485
486 int interleave;
487 int millenium;
488 int milleniumII;
489 struct {
490 int cfb4;
491 const int* vxres;
492 int cross4MB;
493 int text;
494 int plnwt;
495 int srcorg;
496 } capable;
497 struct {
498 unsigned int size;
499 unsigned int mgabase;
500 vaddr_t vbase;
501 } fastfont;
502 #ifdef CONFIG_MTRR
503 struct {
504 int vram;
505 int vram_valid;
506 } mtrr;
507 #endif
508 struct {
509 int precise_width;
510 int mga_24bpp_fix;
511 int novga;
512 int nobios;
513 int nopciretry;
514 int noinit;
515 int inverse;
516 int hwcursor;
517 int blink;
518 int sgram;
519 #ifdef CONFIG_FB_MATROX_32MB
520 int support32MB;
521 #endif
522
523 int accelerator;
524 int text_type_aux;
525 int video64bits;
526 int crtc2;
527 int maven_capable;
528 unsigned int vgastep;
529 unsigned int textmode;
530 unsigned int textstep;
531 unsigned int textvram; /* character cells */
532 unsigned int ydstorg; /* offset in bytes from video start to usable memory */
533 /* 0 except for 6MB Millenium */
534 int memtype;
535 int g450dac;
536 } devflags;
537 struct display_switch dispsw;
538 struct {
539 int x;
540 int y;
541 unsigned int w;
542 unsigned int u;
543 unsigned int d;
544 unsigned int type;
545 int state;
546 int redraw;
547 struct timer_list timer;
548 } cursor;
549 struct { unsigned red, green, blue, transp; } palette[256];
550 #if defined(CONFIG_FB_COMPAT_XPMAC)
551 char matrox_name[32];
552 #endif
553 /* These ifdefs must be last! They differ for module & non-module compiles */
554 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB24) || defined(FBCON_HAS_CFB32)
555 union {
556 #ifdef FBCON_HAS_CFB16
557 u_int16_t cfb16[16];
558 #endif
559 #ifdef FBCON_HAS_CFB24
560 u_int32_t cfb24[16];
561 #endif
562 #ifdef FBCON_HAS_CFB32
563 u_int32_t cfb32[16];
564 #endif
565 } cmap;
566 #endif
567 };
568
569 #ifdef CONFIG_FB_MATROX_MULTIHEAD
570 #define ACCESS_FBINFO2(info, x) (info->x)
571 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
572
573 #define MINFO minfo
574
575 #define WPMINFO2 struct matrox_fb_info* minfo
576 #define WPMINFO WPMINFO2 ,
577 #define CPMINFO2 const struct matrox_fb_info* minfo
578 #define CPMINFO CPMINFO2 ,
579 #define PMINFO2 minfo
580 #define PMINFO PMINFO2 ,
581
582 static inline struct matrox_fb_info* mxinfo(const struct display* p) {
583 return (struct matrox_fb_info*)p->fb_info;
584 }
585
586 #define PMXINFO(p) mxinfo(p),
587 #define MINFO_FROM(x) struct matrox_fb_info* minfo = x
588 #define MINFO_FROM_DISP(x) MINFO_FROM(mxinfo(x))
589
590 #else
591
592 extern struct matrox_fb_info matroxfb_global_mxinfo;
593
594 #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
595 #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
596
597 #define MINFO (&matroxfb_global_mxinfo)
598
599 #define WPMINFO2 void
600 #define WPMINFO
601 #define CPMINFO2 void
602 #define CPMINFO
603 #define PMINFO2
604 #define PMINFO
605
606 #if 0
607 static inline struct matrox_fb_info* mxinfo(const struct display* p) {
608 return &matroxfb_global_mxinfo;
609 }
610 #endif
611
612 #define PMXINFO(p)
613 #define MINFO_FROM(x)
614 #define MINFO_FROM_DISP(x)
615
616 #endif
617
618 struct matrox_switch {
619 int (*preinit)(WPMINFO struct matrox_hw_state*);
620 void (*reset)(WPMINFO struct matrox_hw_state*);
621 int (*init)(CPMINFO struct matrox_hw_state*, struct my_timming*, struct display*);
622 void (*restore)(WPMINFO struct matrox_hw_state*, struct matrox_hw_state*, struct display*);
623 int (*selhwcursor)(WPMINFO struct display*);
624 };
625
626 struct matroxfb_driver {
627 struct list_head node;
628 char* name;
629 void* (*probe)(struct matrox_fb_info* info);
630 void (*remove)(struct matrox_fb_info* info, void* data);
631 };
632
633 int matroxfb_register_driver(struct matroxfb_driver* drv);
634 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
635
636 #define PCI_OPTION_REG 0x40
637 #define PCI_MGA_INDEX 0x44
638 #define PCI_MGA_DATA 0x48
639
640 #define M_DWGCTL 0x1C00
641 #define M_MACCESS 0x1C04
642 #define M_CTLWTST 0x1C08
643
644 #define M_PLNWT 0x1C1C
645
646 #define M_BCOL 0x1C20
647 #define M_FCOL 0x1C24
648
649 #define M_SGN 0x1C58
650 #define M_LEN 0x1C5C
651 #define M_AR0 0x1C60
652 #define M_AR1 0x1C64
653 #define M_AR2 0x1C68
654 #define M_AR3 0x1C6C
655 #define M_AR4 0x1C70
656 #define M_AR5 0x1C74
657 #define M_AR6 0x1C78
658
659 #define M_CXBNDRY 0x1C80
660 #define M_FXBNDRY 0x1C84
661 #define M_YDSTLEN 0x1C88
662 #define M_PITCH 0x1C8C
663 #define M_YDST 0x1C90
664 #define M_YDSTORG 0x1C94
665 #define M_YTOP 0x1C98
666 #define M_YBOT 0x1C9C
667
668 /* mystique only */
669 #define M_CACHEFLUSH 0x1FFF
670
671 #define M_EXEC 0x0100
672
673 #define M_DWG_TRAP 0x04
674 #define M_DWG_BITBLT 0x08
675 #define M_DWG_ILOAD 0x09
676
677 #define M_DWG_LINEAR 0x0080
678 #define M_DWG_SOLID 0x0800
679 #define M_DWG_ARZERO 0x1000
680 #define M_DWG_SGNZERO 0x2000
681 #define M_DWG_SHIFTZERO 0x4000
682
683 #define M_DWG_REPLACE 0x000C0000
684 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
685 #define M_DWG_XOR 0x00060010
686
687 #define M_DWG_BFCOL 0x04000000
688 #define M_DWG_BMONOWF 0x08000000
689
690 #define M_DWG_TRANSC 0x40000000
691
692 #define M_FIFOSTATUS 0x1E10
693 #define M_STATUS 0x1E14
694
695 #define M_IEN 0x1E1C
696
697 #define M_VCOUNT 0x1E20
698
699 #define M_RESET 0x1E40
700 #define M_MEMRDBK 0x1E44
701
702 #define M_AGP2PLL 0x1E4C
703
704 #define M_OPMODE 0x1E54
705 #define M_OPMODE_DMA_GEN_WRITE 0x00
706 #define M_OPMODE_DMA_BLIT 0x04
707 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
708 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
709 #define M_OPMODE_DMA_BE_8BPP 0x0000
710 #define M_OPMODE_DMA_BE_16BPP 0x0100
711 #define M_OPMODE_DMA_BE_32BPP 0x0200
712 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
713 #define M_OPMODE_DIR_BE_8BPP 0x000000
714 #define M_OPMODE_DIR_BE_16BPP 0x010000
715 #define M_OPMODE_DIR_BE_32BPP 0x020000
716
717 #define M_ATTR_INDEX 0x1FC0
718 #define M_ATTR_DATA 0x1FC1
719
720 #define M_MISC_REG 0x1FC2
721 #define M_3C2_RD 0x1FC2
722
723 #define M_SEQ_INDEX 0x1FC4
724 #define M_SEQ_DATA 0x1FC5
725
726 #define M_MISC_REG_READ 0x1FCC
727
728 #define M_GRAPHICS_INDEX 0x1FCE
729 #define M_GRAPHICS_DATA 0x1FCF
730
731 #define M_CRTC_INDEX 0x1FD4
732
733 #define M_ATTR_RESET 0x1FDA
734 #define M_3DA_WR 0x1FDA
735 #define M_INSTS1 0x1FDA
736
737 #define M_EXTVGA_INDEX 0x1FDE
738 #define M_EXTVGA_DATA 0x1FDF
739
740 /* G200 only */
741 #define M_SRCORG 0x2CB4
742 #define M_DSTORG 0x2CB8
743
744 #define M_RAMDAC_BASE 0x3C00
745
746 /* fortunately, same on TVP3026 and MGA1064 */
747 #define M_DAC_REG (M_RAMDAC_BASE+0)
748 #define M_DAC_VAL (M_RAMDAC_BASE+1)
749 #define M_PALETTE_MASK (M_RAMDAC_BASE+2)
750
751 #define M_X_INDEX 0x00
752 #define M_X_DATAREG 0x0A
753
754 #define DAC_XGENIOCTRL 0x2A
755 #define DAC_XGENIODATA 0x2B
756
757 #ifdef __LITTLE_ENDIAN
758 #define MX_OPTION_BSWAP 0x00000000
759
760 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
761 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
762 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
763 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
764 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
765 #else
766 #ifdef __BIG_ENDIAN
767 #define MX_OPTION_BSWAP 0x80000000
768
769 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
770 #define M_OPMODE_8BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
771 #define M_OPMODE_16BPP (M_OPMODE_DMA_BE_16BPP | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
772 #define M_OPMODE_24BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
773 #define M_OPMODE_32BPP (M_OPMODE_DMA_BE_32BPP | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
774 #else
775 #error "Byte ordering have to be defined. Cannot continue."
776 #endif
777 #endif
778
779 #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
780 #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
781 #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
782 #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
783 #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
784 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
785 #ifdef __LITTLE_ENDIAN
786 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
787 #else
788 #define mga_setr(addr,port,val) do { mga_outb(addr, port); mga_outb((addr)+1, val); } while (0)
789 #endif
790
791 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
792
793 #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
794
795 /* code speedup */
796 #ifdef CONFIG_FB_MATROX_MILLENIUM
797 #define isInterleave(x) (x->interleave)
798 #define isMillenium(x) (x->millenium)
799 #define isMilleniumII(x) (x->milleniumII)
800 #else
801 #define isInterleave(x) (0)
802 #define isMillenium(x) (0)
803 #define isMilleniumII(x) (0)
804 #endif
805
806 #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
807 #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
808 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
809 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
810 extern void matroxfb_DAC_out(CPMINFO int reg, int val);
811 extern int matroxfb_DAC_in(CPMINFO int reg);
812 extern struct list_head matroxfb_list;
813 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
814
815 #ifdef MATROXFB_USE_SPINLOCKS
816 #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
817 #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
818 #define CRITFLAGS unsigned long critflags;
819 #else
820 #define CRITBEGIN
821 #define CRITEND
822 #define CRITFLAGS
823 #endif
824
825 #endif /* __MATROXFB_H__ */
826