File: /usr/src/linux/arch/ia64/kernel/brl_emu.c
1 /*
2 * Emulation of the "brl" instruction for IA64 processors that
3 * don't support it in hardware.
4 * Author: Stephan Zeisset, Intel Corp. <Stephan.Zeisset@intel.com>
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <asm/uaccess.h>
10 #include <asm/processor.h>
11
12 extern char ia64_set_b1, ia64_set_b2, ia64_set_b3, ia64_set_b4, ia64_set_b5;
13
14 struct illegal_op_return {
15 unsigned long fkt, arg1, arg2, arg3;
16 };
17
18 /*
19 * The unimplemented bits of a virtual address must be set
20 * to the value of the most significant implemented bit.
21 * unimpl_va_mask includes all unimplemented bits and
22 * the most significant implemented bit, so the result
23 * of an and operation with the mask must be all 0's
24 * or all 1's for the address to be valid.
25 */
26 #define unimplemented_virtual_address(va) ( \
27 ((va) & local_cpu_data->unimpl_va_mask) != 0 && \
28 ((va) & local_cpu_data->unimpl_va_mask) != local_cpu_data->unimpl_va_mask \
29 )
30
31 /*
32 * The unimplemented bits of a physical address must be 0.
33 * unimpl_pa_mask includes all unimplemented bits, so the result
34 * of an and operation with the mask must be all 0's for the
35 * address to be valid.
36 */
37 #define unimplemented_physical_address(pa) ( \
38 ((pa) & local_cpu_data->unimpl_pa_mask) != 0 \
39 )
40
41 /*
42 * Handle an illegal operation fault that was caused by an
43 * unimplemented "brl" instruction.
44 * If we are not successful (e.g because the illegal operation
45 * wasn't caused by a "brl" after all), we return -1.
46 * If we are successful, we return either 0 or the address
47 * of a "fixup" function for manipulating preserved register
48 * state.
49 */
50
51 struct illegal_op_return
52 ia64_emulate_brl (struct pt_regs *regs, unsigned long ar_ec)
53 {
54 unsigned long bundle[2];
55 unsigned long opcode, btype, qp, offset;
56 unsigned long next_ip;
57 struct siginfo siginfo;
58 struct illegal_op_return rv;
59 int tmp_taken, unimplemented_address;
60
61 rv.fkt = (unsigned long) -1;
62
63 /*
64 * Decode the instruction bundle.
65 */
66
67 if (copy_from_user(bundle, (void *) (regs->cr_iip), sizeof(bundle)))
68 return rv;
69
70 next_ip = (unsigned long) regs->cr_iip + 16;
71
72 /* "brl" must be in slot 2. */
73 if (ia64_psr(regs)->ri != 1) return rv;
74
75 /* Must be "mlx" template */
76 if ((bundle[0] & 0x1e) != 0x4) return rv;
77
78 opcode = (bundle[1] >> 60);
79 btype = ((bundle[1] >> 29) & 0x7);
80 qp = ((bundle[1] >> 23) & 0x3f);
81 offset = ((bundle[1] & 0x0800000000000000L) << 4)
82 | ((bundle[1] & 0x00fffff000000000L) >> 32)
83 | ((bundle[1] & 0x00000000007fffffL) << 40)
84 | ((bundle[0] & 0xffff000000000000L) >> 24);
85
86 tmp_taken = regs->pr & (1L << qp);
87
88 switch(opcode) {
89
90 case 0xC:
91 /*
92 * Long Branch.
93 */
94 if (btype != 0) return rv;
95 rv.fkt = 0;
96 if (!(tmp_taken)) {
97 /*
98 * Qualifying predicate is 0.
99 * Skip instruction.
100 */
101 regs->cr_iip = next_ip;
102 ia64_psr(regs)->ri = 0;
103 return rv;
104 }
105 break;
106
107 case 0xD:
108 /*
109 * Long Call.
110 */
111 rv.fkt = 0;
112 if (!(tmp_taken)) {
113 /*
114 * Qualifying predicate is 0.
115 * Skip instruction.
116 */
117 regs->cr_iip = next_ip;
118 ia64_psr(regs)->ri = 0;
119 return rv;
120 }
121
122 /*
123 * BR[btype] = IP+16
124 */
125 switch(btype) {
126 case 0:
127 regs->b0 = next_ip;
128 break;
129 case 1:
130 rv.fkt = (unsigned long) &ia64_set_b1;
131 break;
132 case 2:
133 rv.fkt = (unsigned long) &ia64_set_b2;
134 break;
135 case 3:
136 rv.fkt = (unsigned long) &ia64_set_b3;
137 break;
138 case 4:
139 rv.fkt = (unsigned long) &ia64_set_b4;
140 break;
141 case 5:
142 rv.fkt = (unsigned long) &ia64_set_b5;
143 break;
144 case 6:
145 regs->b6 = next_ip;
146 break;
147 case 7:
148 regs->b7 = next_ip;
149 break;
150 }
151 rv.arg1 = next_ip;
152
153 /*
154 * AR[PFS].pfm = CFM
155 * AR[PFS].pec = AR[EC]
156 * AR[PFS].ppl = PSR.cpl
157 */
158 regs->ar_pfs = ((regs->cr_ifs & 0x3fffffffff)
159 | (ar_ec << 52)
160 | ((unsigned long) ia64_psr(regs)->cpl << 62));
161
162 /*
163 * CFM.sof -= CFM.sol
164 * CFM.sol = 0
165 * CFM.sor = 0
166 * CFM.rrb.gr = 0
167 * CFM.rrb.fr = 0
168 * CFM.rrb.pr = 0
169 */
170 regs->cr_ifs = ((regs->cr_ifs & 0xffffffc00000007f)
171 - ((regs->cr_ifs >> 7) & 0x7f));
172
173 break;
174
175 default:
176 /*
177 * Unknown opcode.
178 */
179 return rv;
180
181 }
182
183 regs->cr_iip += offset;
184 ia64_psr(regs)->ri = 0;
185
186 if (ia64_psr(regs)->it == 0)
187 unimplemented_address = unimplemented_physical_address(regs->cr_iip);
188 else
189 unimplemented_address = unimplemented_virtual_address(regs->cr_iip);
190
191 if (unimplemented_address) {
192 /*
193 * The target address contains unimplemented bits.
194 */
195 printk("Woah! Unimplemented Instruction Address Trap!\n");
196 siginfo.si_signo = SIGILL;
197 siginfo.si_errno = 0;
198 siginfo.si_code = ILL_BADIADDR;
199 force_sig_info(SIGILL, &siginfo, current);
200 } else if (ia64_psr(regs)->tb) {
201 /*
202 * Branch Tracing is enabled.
203 * Force a taken branch signal.
204 */
205 siginfo.si_signo = SIGTRAP;
206 siginfo.si_errno = 0;
207 siginfo.si_code = TRAP_BRANCH;
208 force_sig_info(SIGTRAP, &siginfo, current);
209 } else if (ia64_psr(regs)->ss) {
210 /*
211 * Single Step is enabled.
212 * Force a trace signal.
213 */
214 siginfo.si_signo = SIGTRAP;
215 siginfo.si_errno = 0;
216 siginfo.si_code = TRAP_TRACE;
217 force_sig_info(SIGTRAP, &siginfo, current);
218 }
219 return rv;
220 }
221