File: /usr/src/linux/arch/ia64/kernel/iosapic.c
1 /*
2 * I/O SAPIC support.
3 *
4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 1999-2000 Hewlett-Packard Co.
7 * Copyright (C) 1999-2000 David Mosberger-Tang <davidm@hpl.hp.com>
8 * Copyright (C) 1999 VA Linux Systems
9 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
10 *
11 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
12 * In particular, we now have separate handlers for edge
13 * and level triggered interrupts.
14 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
15 * PCI to vector mapping, shared PCI interrupts.
16 * 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
17 * Clean up much of the old IOSAPIC cruft.
18 */
19 /*
20 * Here is what the interrupt logic between a PCI device and the CPU looks like:
21 *
22 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
23 * device is uniquely identified by its bus--, and slot-number (the function
24 * number does not matter here because all functions share the same interrupt
25 * lines).
26 *
27 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
28 * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
29 * triggered and use the same polarity). Each interrupt line has a unique IOSAPIC
30 * irq number which can be calculated as the sum of the controller's base irq number
31 * and the IOSAPIC pin number to which the line connects.
32 *
33 * (3) The IOSAPIC uses an internal table to map the IOSAPIC pin into the IA-64 interrupt
34 * vector. This interrupt vector is then sent to the CPU.
35 *
36 * In other words, there are two levels of indirections involved:
37 *
38 * pci pin -> iosapic irq -> IA-64 vector
39 *
40 * Note: outside this module, IA-64 vectors are called "irqs". This is because that's
41 * the traditional name Linux uses for interrupt vectors.
42 */
43 #include <linux/config.h>
44
45 #include <linux/kernel.h>
46 #include <linux/init.h>
47 #include <linux/pci.h>
48 #include <linux/smp.h>
49 #include <linux/smp_lock.h>
50 #include <linux/string.h>
51 #include <linux/irq.h>
52
53 #include <asm/acpi-ext.h>
54 #include <asm/acpikcfg.h>
55 #include <asm/delay.h>
56 #include <asm/io.h>
57 #include <asm/iosapic.h>
58 #include <asm/machvec.h>
59 #include <asm/processor.h>
60 #include <asm/ptrace.h>
61 #include <asm/system.h>
62
63
64 #undef DEBUG_IRQ_ROUTING
65
66 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
67
68 /* PCI pin to IOSAPIC irq routing information. This info typically comes from ACPI. */
69
70 static struct {
71 int num_routes;
72 struct pci_vector_struct *route;
73 } pci_irq;
74
75 /* This tables maps IA-64 vectors to the IOSAPIC pin that generates this vector. */
76
77 static struct iosapic_irq {
78 char *addr; /* base address of IOSAPIC */
79 unsigned char base_irq; /* first irq assigned to this IOSAPIC */
80 char pin; /* IOSAPIC pin (-1 => not an IOSAPIC irq) */
81 unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
82 unsigned char polarity : 1; /* interrupt polarity (see iosapic.h) */
83 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
84 } iosapic_irq[IA64_NUM_VECTORS];
85
86 /*
87 * Translate IOSAPIC irq number to the corresponding IA-64 interrupt vector. If no
88 * entry exists, return -1.
89 */
90 static int
91 iosapic_irq_to_vector (int irq)
92 {
93 int vector;
94
95 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
96 if (iosapic_irq[vector].base_irq + iosapic_irq[vector].pin == irq)
97 return vector;
98 return -1;
99 }
100
101 /*
102 * Map PCI pin to the corresponding IA-64 interrupt vector. If no such mapping exists,
103 * return -1.
104 */
105 static int
106 pci_pin_to_vector (int bus, int slot, int pci_pin)
107 {
108 struct pci_vector_struct *r;
109
110 for (r = pci_irq.route; r < pci_irq.route + pci_irq.num_routes; ++r)
111 if (r->bus == bus && (r->pci_id >> 16) == slot && r->pin == pci_pin)
112 return iosapic_irq_to_vector(r->irq);
113 return -1;
114 }
115
116 static void
117 set_rte (unsigned int vector, unsigned long dest)
118 {
119 unsigned long pol, trigger, dmode;
120 u32 low32, high32;
121 char *addr;
122 int pin;
123
124 pin = iosapic_irq[vector].pin;
125 if (pin < 0)
126 return; /* not an IOSAPIC interrupt */
127
128 addr = iosapic_irq[vector].addr;
129 pol = iosapic_irq[vector].polarity;
130 trigger = iosapic_irq[vector].trigger;
131 dmode = iosapic_irq[vector].dmode;
132
133 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
134 (trigger << IOSAPIC_TRIGGER_SHIFT) |
135 (dmode << IOSAPIC_DELIVERY_SHIFT) |
136 vector);
137
138 /* dest contains both id and eid */
139 high32 = (dest << IOSAPIC_DEST_SHIFT);
140
141 writel(IOSAPIC_RTE_HIGH(pin), addr + IOSAPIC_REG_SELECT);
142 writel(high32, addr + IOSAPIC_WINDOW);
143 writel(IOSAPIC_RTE_LOW(pin), addr + IOSAPIC_REG_SELECT);
144 writel(low32, addr + IOSAPIC_WINDOW);
145 }
146
147 static void
148 nop (unsigned int vector)
149 {
150 /* do nothing... */
151 }
152
153 static void
154 mask_irq (unsigned int irq)
155 {
156 unsigned long flags;
157 char *addr;
158 u32 low32;
159 int pin;
160 ia64_vector vec = irq_to_vector(irq);
161
162 addr = iosapic_irq[vec].addr;
163 pin = iosapic_irq[vec].pin;
164
165 if (pin < 0)
166 return; /* not an IOSAPIC interrupt! */
167
168 spin_lock_irqsave(&iosapic_lock, flags);
169 {
170 writel(IOSAPIC_RTE_LOW(pin), addr + IOSAPIC_REG_SELECT);
171 low32 = readl(addr + IOSAPIC_WINDOW);
172
173 low32 |= (1 << IOSAPIC_MASK_SHIFT); /* set only the mask bit */
174 writel(low32, addr + IOSAPIC_WINDOW);
175 }
176 spin_unlock_irqrestore(&iosapic_lock, flags);
177 }
178
179 static void
180 unmask_irq (unsigned int irq)
181 {
182 unsigned long flags;
183 char *addr;
184 u32 low32;
185 int pin;
186 ia64_vector vec = irq_to_vector(irq);
187
188 addr = iosapic_irq[vec].addr;
189 pin = iosapic_irq[vec].pin;
190 if (pin < 0)
191 return; /* not an IOSAPIC interrupt! */
192
193 spin_lock_irqsave(&iosapic_lock, flags);
194 {
195 writel(IOSAPIC_RTE_LOW(pin), addr + IOSAPIC_REG_SELECT);
196 low32 = readl(addr + IOSAPIC_WINDOW);
197
198 low32 &= ~(1 << IOSAPIC_MASK_SHIFT); /* clear only the mask bit */
199 writel(low32, addr + IOSAPIC_WINDOW);
200 }
201 spin_unlock_irqrestore(&iosapic_lock, flags);
202 }
203
204
205 static void
206 iosapic_set_affinity (unsigned int irq, unsigned long mask)
207 {
208 #ifdef CONFIG_SMP
209 unsigned long flags;
210 u32 high32, low32;
211 int dest, pin;
212 char *addr;
213
214 mask &= (1UL << smp_num_cpus) - 1;
215
216 if (!mask || irq >= IA64_NUM_VECTORS)
217 return;
218
219 dest = cpu_physical_id(ffz(~mask));
220
221 pin = iosapic_irq[irq].pin;
222 addr = iosapic_irq[irq].addr;
223
224 if (pin < 0)
225 return; /* not an IOSAPIC interrupt */
226
227 /* dest contains both id and eid */
228 high32 = dest << IOSAPIC_DEST_SHIFT;
229
230 spin_lock_irqsave(&iosapic_lock, flags);
231 {
232 /* get current delivery mode by reading the low32 */
233 writel(IOSAPIC_RTE_LOW(pin), addr + IOSAPIC_REG_SELECT);
234 low32 = readl(addr + IOSAPIC_WINDOW);
235
236 /* change delivery mode to fixed */
237 low32 &= ~(7 << IOSAPIC_DELIVERY_SHIFT);
238 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
239
240 writel(IOSAPIC_RTE_HIGH(pin), addr + IOSAPIC_REG_SELECT);
241 writel(high32, addr + IOSAPIC_WINDOW);
242 writel(IOSAPIC_RTE_LOW(pin), addr + IOSAPIC_REG_SELECT);
243 writel(low32, addr + IOSAPIC_WINDOW);
244 }
245 spin_unlock_irqrestore(&iosapic_lock, flags);
246 #endif
247 }
248
249 /*
250 * Handlers for level-triggered interrupts.
251 */
252
253 static unsigned int
254 iosapic_startup_level_irq (unsigned int irq)
255 {
256 unmask_irq(irq);
257 return 0;
258 }
259
260 static void
261 iosapic_end_level_irq (unsigned int irq)
262 {
263 ia64_vector vec = irq_to_vector(irq);
264
265 writel(vec, iosapic_irq[vec].addr + IOSAPIC_EOI);
266 }
267
268 #define iosapic_shutdown_level_irq mask_irq
269 #define iosapic_enable_level_irq unmask_irq
270 #define iosapic_disable_level_irq mask_irq
271 #define iosapic_ack_level_irq nop
272
273 struct hw_interrupt_type irq_type_iosapic_level = {
274 typename: "IO-SAPIC-level",
275 startup: iosapic_startup_level_irq,
276 shutdown: iosapic_shutdown_level_irq,
277 enable: iosapic_enable_level_irq,
278 disable: iosapic_disable_level_irq,
279 ack: iosapic_ack_level_irq,
280 end: iosapic_end_level_irq,
281 set_affinity: iosapic_set_affinity
282 };
283
284 /*
285 * Handlers for edge-triggered interrupts.
286 */
287
288 static unsigned int
289 iosapic_startup_edge_irq (unsigned int irq)
290 {
291 unmask_irq(irq);
292 /*
293 * IOSAPIC simply drops interrupts pended while the
294 * corresponding pin was masked, so we can't know if an
295 * interrupt is pending already. Let's hope not...
296 */
297 return 0;
298 }
299
300 static void
301 iosapic_ack_edge_irq (unsigned int irq)
302 {
303 irq_desc_t *idesc = irq_desc(irq);
304 /*
305 * Once we have recorded IRQ_PENDING already, we can mask the
306 * interrupt for real. This prevents IRQ storms from unhandled
307 * devices.
308 */
309 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
310 mask_irq(irq);
311 }
312
313 #define iosapic_enable_edge_irq unmask_irq
314 #define iosapic_disable_edge_irq nop
315 #define iosapic_end_edge_irq nop
316
317 struct hw_interrupt_type irq_type_iosapic_edge = {
318 typename: "IO-SAPIC-edge",
319 startup: iosapic_startup_edge_irq,
320 shutdown: iosapic_disable_edge_irq,
321 enable: iosapic_enable_edge_irq,
322 disable: iosapic_disable_edge_irq,
323 ack: iosapic_ack_edge_irq,
324 end: iosapic_end_edge_irq,
325 set_affinity: iosapic_set_affinity
326 };
327
328 static unsigned int
329 iosapic_version (char *addr)
330 {
331 /*
332 * IOSAPIC Version Register return 32 bit structure like:
333 * {
334 * unsigned int version : 8;
335 * unsigned int reserved1 : 8;
336 * unsigned int pins : 8;
337 * unsigned int reserved2 : 8;
338 * }
339 */
340 writel(IOSAPIC_VERSION, addr + IOSAPIC_REG_SELECT);
341 return readl(IOSAPIC_WINDOW + addr);
342 }
343
344 /*
345 * ACPI calls this when it finds an entry for a legacy ISA interrupt. Note that the
346 * irq_base and IOSAPIC address must be set in iosapic_init().
347 */
348 void
349 iosapic_register_legacy_irq (unsigned long irq,
350 unsigned long pin, unsigned long polarity,
351 unsigned long edge_triggered)
352 {
353 unsigned int vector = isa_irq_to_vector(irq);
354
355 #ifdef DEBUG_IRQ_ROUTING
356 printk("ISA: IRQ %u -> IOSAPIC irq 0x%02x (%s, %s) -> vector %02x\n",
357 (unsigned) irq, (unsigned) pin,
358 polarity ? "high" : "low", edge_triggered ? "edge" : "level",
359 vector);
360 #endif
361
362 iosapic_irq[vector].pin = pin;
363 iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
364 iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW;
365 iosapic_irq[vector].trigger = edge_triggered ? IOSAPIC_EDGE : IOSAPIC_LEVEL;
366 }
367
368 void __init
369 iosapic_init (unsigned long phys_addr, unsigned int base_irq, int pcat_compat)
370 {
371 struct hw_interrupt_type *irq_type;
372 int i, irq, max_pin, vector;
373 irq_desc_t *idesc;
374 unsigned int ver;
375 char *addr;
376 static int first_time = 1;
377
378 if (first_time) {
379 first_time = 0;
380
381 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
382 iosapic_irq[vector].pin = -1; /* mark as unused */
383
384 /*
385 * Fetch the PCI interrupt routing table:
386 */
387 acpi_cf_get_pci_vectors(&pci_irq.route, &pci_irq.num_routes);
388 }
389
390 addr = ioremap(phys_addr, 0);
391
392 ver = iosapic_version(addr);
393 max_pin = (ver >> 16) & 0xff;
394
395 printk("IOSAPIC: version %x.%x, address 0x%lx, IRQs 0x%02x-0x%02x\n",
396 (ver & 0xf0) >> 4, (ver & 0x0f), phys_addr, base_irq, base_irq + max_pin);
397
398 if ((base_irq == 0) && pcat_compat)
399 /*
400 * Map the legacy ISA devices into the IOSAPIC data. Some of these may
401 * get reprogrammed later on with data from the ACPI Interrupt Source
402 * Override table.
403 */
404 for (irq = 0; irq < 16; ++irq) {
405 vector = isa_irq_to_vector(irq);
406 iosapic_irq[vector].addr = addr;
407 iosapic_irq[vector].base_irq = 0;
408 if (iosapic_irq[vector].pin == -1)
409 iosapic_irq[vector].pin = irq;
410 iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
411 iosapic_irq[vector].trigger = IOSAPIC_EDGE;
412 iosapic_irq[vector].polarity = IOSAPIC_POL_HIGH;
413 #ifdef DEBUG_IRQ_ROUTING
414 printk("ISA: IRQ %u -> IOSAPIC irq 0x%02x (high, edge) -> vector 0x%02x\n",
415 irq, iosapic_irq[vector].base_irq + iosapic_irq[vector].pin,
416 vector);
417 #endif
418 irq_type = &irq_type_iosapic_edge;
419 idesc = irq_desc(vector);
420 if (idesc->handler != irq_type) {
421 if (idesc->handler != &no_irq_type)
422 printk("iosapic_init: changing vector 0x%02x from %s to "
423 "%s\n", irq, idesc->handler->typename,
424 irq_type->typename);
425 idesc->handler = irq_type;
426 }
427
428 /* program the IOSAPIC routing table: */
429 set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
430 }
431
432 for (i = 0; i < pci_irq.num_routes; i++) {
433 irq = pci_irq.route[i].irq;
434
435 if ((unsigned) (irq - base_irq) > max_pin)
436 /* the interrupt route is for another controller... */
437 continue;
438
439 if (irq < 16)
440 vector = isa_irq_to_vector(irq);
441 else {
442 vector = iosapic_irq_to_vector(irq);
443 if (vector < 0)
444 /* new iosapic irq: allocate a vector for it */
445 vector = ia64_alloc_irq();
446 }
447
448 iosapic_irq[vector].addr = addr;
449 iosapic_irq[vector].base_irq = base_irq;
450 iosapic_irq[vector].pin = (irq - base_irq);
451 iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
452 iosapic_irq[vector].trigger = IOSAPIC_LEVEL;
453 iosapic_irq[vector].polarity = IOSAPIC_POL_LOW;
454
455 # ifdef DEBUG_IRQ_ROUTING
456 printk("PCI: (B%d,I%d,P%d) -> IOSAPIC irq 0x%02x -> vector 0x%02x\n",
457 pci_irq.route[i].bus, pci_irq.route[i].pci_id>>16, pci_irq.route[i].pin,
458 iosapic_irq[vector].base_irq + iosapic_irq[vector].pin, vector);
459 # endif
460 irq_type = &irq_type_iosapic_level;
461 idesc = irq_desc(vector);
462 if (idesc->handler != irq_type){
463 if (idesc->handler != &no_irq_type)
464 printk("iosapic_init: changing vector 0x%02x from %s to %s\n",
465 vector, idesc->handler->typename, irq_type->typename);
466 idesc->handler = irq_type;
467 }
468
469 /* program the IOSAPIC routing table: */
470 set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
471 }
472 }
473
474 void
475 iosapic_pci_fixup (int phase)
476 {
477 struct pci_dev *dev;
478 unsigned char pin;
479 int vector;
480
481 if (phase != 1)
482 return;
483
484 pci_for_each_dev(dev) {
485 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
486 if (pin) {
487 pin--; /* interrupt pins are numbered starting from 1 */
488 vector = pci_pin_to_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
489 if (vector < 0 && dev->bus->parent) {
490 /* go back to the bridge */
491 struct pci_dev *bridge = dev->bus->self;
492
493 if (bridge) {
494 /* allow for multiple bridges on an adapter */
495 do {
496 /* do the bridge swizzle... */
497 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
498 vector = pci_pin_to_vector(bridge->bus->number,
499 PCI_SLOT(bridge->devfn),
500 pin);
501 } while (vector < 0 && (bridge = bridge->bus->self));
502 }
503 if (vector >= 0)
504 printk(KERN_WARNING
505 "PCI: using PPB(B%d,I%d,P%d) to get vector %02x\n",
506 bridge->bus->number, PCI_SLOT(bridge->devfn),
507 pin, vector);
508 else
509 printk(KERN_WARNING
510 "PCI: Couldn't map irq for (B%d,I%d,P%d)o\n",
511 bridge->bus->number, PCI_SLOT(bridge->devfn),
512 pin);
513 }
514 if (vector >= 0) {
515 printk("PCI->APIC IRQ transform: (B%d,I%d,P%d) -> 0x%02x\n",
516 dev->bus->number, PCI_SLOT(dev->devfn), pin, vector);
517 dev->irq = vector;
518 }
519 }
520 /*
521 * Nothing to fixup
522 * Fix out-of-range IRQ numbers
523 */
524 if (dev->irq >= IA64_NUM_VECTORS)
525 dev->irq = 15; /* Spurious interrupts */
526 }
527 }
528