File: /usr/include/asm/apicdef.h
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
3
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
10
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0x0F<<24)
15 #define GET_APIC_ID(x) (((x)>>24)&0x0F)
16 #define APIC_LVR 0x30
17 #define APIC_LVR_MASK 0xFF00FF
18 #define GET_APIC_VERSION(x) ((x)&0xFF)
19 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
20 #define APIC_INTEGRATED(x) ((x)&0xF0)
21 #define APIC_TASKPRI 0x80
22 #define APIC_TPRI_MASK 0xFF
23 #define APIC_ARBPRI 0x90
24 #define APIC_ARBPRI_MASK 0xFF
25 #define APIC_PROCPRI 0xA0
26 #define APIC_EOI 0xB0
27 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
28 #define APIC_RRR 0xC0
29 #define APIC_LDR 0xD0
30 #define APIC_LDR_MASK (0xFF<<24)
31 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
32 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
33 #define APIC_ALL_CPUS 0xFF
34 #define APIC_DFR 0xE0
35 #define APIC_SPIV 0xF0
36 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
37 #define APIC_SPIV_APIC_ENABLED (1<<8)
38 #define APIC_ISR 0x100
39 #define APIC_TMR 0x180
40 #define APIC_IRR 0x200
41 #define APIC_ESR 0x280
42 #define APIC_ESR_SEND_CS 0x00001
43 #define APIC_ESR_RECV_CS 0x00002
44 #define APIC_ESR_SEND_ACC 0x00004
45 #define APIC_ESR_RECV_ACC 0x00008
46 #define APIC_ESR_SENDILL 0x00020
47 #define APIC_ESR_RECVILL 0x00040
48 #define APIC_ESR_ILLREGA 0x00080
49 #define APIC_ICR 0x300
50 #define APIC_DEST_SELF 0x40000
51 #define APIC_DEST_ALLINC 0x80000
52 #define APIC_DEST_ALLBUT 0xC0000
53 #define APIC_ICR_RR_MASK 0x30000
54 #define APIC_ICR_RR_INVALID 0x00000
55 #define APIC_ICR_RR_INPROG 0x10000
56 #define APIC_ICR_RR_VALID 0x20000
57 #define APIC_INT_LEVELTRIG 0x08000
58 #define APIC_INT_ASSERT 0x04000
59 #define APIC_ICR_BUSY 0x01000
60 #define APIC_DEST_LOGICAL 0x00800
61 #define APIC_DM_FIXED 0x00000
62 #define APIC_DM_LOWEST 0x00100
63 #define APIC_DM_SMI 0x00200
64 #define APIC_DM_REMRD 0x00300
65 #define APIC_DM_NMI 0x00400
66 #define APIC_DM_INIT 0x00500
67 #define APIC_DM_STARTUP 0x00600
68 #define APIC_DM_EXTINT 0x00700
69 #define APIC_VECTOR_MASK 0x000FF
70 #define APIC_ICR2 0x310
71 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
72 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
73 #define APIC_LVTT 0x320
74 #define APIC_LVTPC 0x340
75 #define APIC_LVT0 0x350
76 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
77 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
78 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
79 #define APIC_TIMER_BASE_CLKIN 0x0
80 #define APIC_TIMER_BASE_TMBASE 0x1
81 #define APIC_TIMER_BASE_DIV 0x2
82 #define APIC_LVT_TIMER_PERIODIC (1<<17)
83 #define APIC_LVT_MASKED (1<<16)
84 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
85 #define APIC_LVT_REMOTE_IRR (1<<14)
86 #define APIC_INPUT_POLARITY (1<<13)
87 #define APIC_SEND_PENDING (1<<12)
88 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
89 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
90 #define APIC_MODE_FIXED 0x0
91 #define APIC_MODE_NMI 0x4
92 #define APIC_MODE_EXINT 0x7
93 #define APIC_LVT1 0x360
94 #define APIC_LVTERR 0x370
95 #define APIC_TMICT 0x380
96 #define APIC_TMCCT 0x390
97 #define APIC_TDCR 0x3E0
98 #define APIC_TDR_DIV_TMBASE (1<<2)
99 #define APIC_TDR_DIV_1 0xB
100 #define APIC_TDR_DIV_2 0x0
101 #define APIC_TDR_DIV_4 0x1
102 #define APIC_TDR_DIV_8 0x2
103 #define APIC_TDR_DIV_16 0x3
104 #define APIC_TDR_DIV_32 0x8
105 #define APIC_TDR_DIV_64 0x9
106 #define APIC_TDR_DIV_128 0xA
107
108 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
109
110 #define MAX_IO_APICS 8
111
112 /*
113 * the local APIC register structure, memory mapped. Not terribly well
114 * tested, but we might eventually use this one in the future - the
115 * problem why we cannot use it right now is the P5 APIC, it has an
116 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
117 */
118 #define u32 unsigned int
119
120 #define lapic ((volatile struct local_apic *)APIC_BASE)
121
122 struct local_apic {
123
124 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
125
126 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
127
128 /*020*/ struct { /* APIC ID Register */
129 u32 __reserved_1 : 24,
130 phys_apic_id : 4,
131 __reserved_2 : 4;
132 u32 __reserved[3];
133 } id;
134
135 /*030*/ const
136 struct { /* APIC Version Register */
137 u32 version : 8,
138 __reserved_1 : 8,
139 max_lvt : 8,
140 __reserved_2 : 8;
141 u32 __reserved[3];
142 } version;
143
144 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
145
146 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
147
148 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
149
150 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
151
152 /*080*/ struct { /* Task Priority Register */
153 u32 priority : 8,
154 __reserved_1 : 24;
155 u32 __reserved_2[3];
156 } tpr;
157
158 /*090*/ const
159 struct { /* Arbitration Priority Register */
160 u32 priority : 8,
161 __reserved_1 : 24;
162 u32 __reserved_2[3];
163 } apr;
164
165 /*0A0*/ const
166 struct { /* Processor Priority Register */
167 u32 priority : 8,
168 __reserved_1 : 24;
169 u32 __reserved_2[3];
170 } ppr;
171
172 /*0B0*/ struct { /* End Of Interrupt Register */
173 u32 eoi;
174 u32 __reserved[3];
175 } eoi;
176
177 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
178
179 /*0D0*/ struct { /* Logical Destination Register */
180 u32 __reserved_1 : 24,
181 logical_dest : 8;
182 u32 __reserved_2[3];
183 } ldr;
184
185 /*0E0*/ struct { /* Destination Format Register */
186 u32 __reserved_1 : 28,
187 model : 4;
188 u32 __reserved_2[3];
189 } dfr;
190
191 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
192 u32 spurious_vector : 8,
193 apic_enabled : 1,
194 focus_cpu : 1,
195 __reserved_2 : 22;
196 u32 __reserved_3[3];
197 } svr;
198
199 /*100*/ struct { /* In Service Register */
200 /*170*/ u32 bitfield;
201 u32 __reserved[3];
202 } isr [8];
203
204 /*180*/ struct { /* Trigger Mode Register */
205 /*1F0*/ u32 bitfield;
206 u32 __reserved[3];
207 } tmr [8];
208
209 /*200*/ struct { /* Interrupt Request Register */
210 /*270*/ u32 bitfield;
211 u32 __reserved[3];
212 } irr [8];
213
214 /*280*/ union { /* Error Status Register */
215 struct {
216 u32 send_cs_error : 1,
217 receive_cs_error : 1,
218 send_accept_error : 1,
219 receive_accept_error : 1,
220 __reserved_1 : 1,
221 send_illegal_vector : 1,
222 receive_illegal_vector : 1,
223 illegal_register_address : 1,
224 __reserved_2 : 24;
225 u32 __reserved_3[3];
226 } error_bits;
227 struct {
228 u32 errors;
229 u32 __reserved_3[3];
230 } all_errors;
231 } esr;
232
233 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
234
235 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
236
237 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
238
239 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
240
241 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
242
243 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
244
245 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
246
247 /*300*/ struct { /* Interrupt Command Register 1 */
248 u32 vector : 8,
249 delivery_mode : 3,
250 destination_mode : 1,
251 delivery_status : 1,
252 __reserved_1 : 1,
253 level : 1,
254 trigger : 1,
255 __reserved_2 : 2,
256 shorthand : 2,
257 __reserved_3 : 12;
258 u32 __reserved_4[3];
259 } icr1;
260
261 /*310*/ struct { /* Interrupt Command Register 2 */
262 union {
263 u32 __reserved_1 : 24,
264 phys_dest : 4,
265 __reserved_2 : 4;
266 u32 __reserved_3 : 24,
267 logical_dest : 8;
268 } dest;
269 u32 __reserved_4[3];
270 } icr2;
271
272 /*320*/ struct { /* LVT - Timer */
273 u32 vector : 8,
274 __reserved_1 : 4,
275 delivery_status : 1,
276 __reserved_2 : 3,
277 mask : 1,
278 timer_mode : 1,
279 __reserved_3 : 14;
280 u32 __reserved_4[3];
281 } lvt_timer;
282
283 /*330*/ struct { u32 __reserved[4]; } __reserved_15;
284
285 /*340*/ struct { /* LVT - Performance Counter */
286 u32 vector : 8,
287 delivery_mode : 3,
288 __reserved_1 : 1,
289 delivery_status : 1,
290 __reserved_2 : 3,
291 mask : 1,
292 __reserved_3 : 15;
293 u32 __reserved_4[3];
294 } lvt_pc;
295
296 /*350*/ struct { /* LVT - LINT0 */
297 u32 vector : 8,
298 delivery_mode : 3,
299 __reserved_1 : 1,
300 delivery_status : 1,
301 polarity : 1,
302 remote_irr : 1,
303 trigger : 1,
304 mask : 1,
305 __reserved_2 : 15;
306 u32 __reserved_3[3];
307 } lvt_lint0;
308
309 /*360*/ struct { /* LVT - LINT1 */
310 u32 vector : 8,
311 delivery_mode : 3,
312 __reserved_1 : 1,
313 delivery_status : 1,
314 polarity : 1,
315 remote_irr : 1,
316 trigger : 1,
317 mask : 1,
318 __reserved_2 : 15;
319 u32 __reserved_3[3];
320 } lvt_lint1;
321
322 /*370*/ struct { /* LVT - Error */
323 u32 vector : 8,
324 __reserved_1 : 4,
325 delivery_status : 1,
326 __reserved_2 : 3,
327 mask : 1,
328 __reserved_3 : 15;
329 u32 __reserved_4[3];
330 } lvt_error;
331
332 /*380*/ struct { /* Timer Initial Count Register */
333 u32 initial_count;
334 u32 __reserved_2[3];
335 } timer_icr;
336
337 /*390*/ const
338 struct { /* Timer Current Count Register */
339 u32 curr_count;
340 u32 __reserved_2[3];
341 } timer_ccr;
342
343 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
344
345 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
346
347 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
348
349 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
350
351 /*3E0*/ struct { /* Timer Divide Configuration Register */
352 u32 divisor : 4,
353 __reserved_1 : 28;
354 u32 __reserved_2[3];
355 } timer_dcr;
356
357 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
358
359 } __attribute__ ((packed));
360
361 #undef u32
362
363 #endif
364