File: /usr/src/linux/include/asm-ia64/sn/mmzone_sn1.h
1 #ifndef _ASM_IA64_MMZONE_SN1_H
2 #define _ASM_IA64_MMZONE_SN1_H
3
4 #include <linux/config.h>
5
6 /*
7 * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
8 */
9 /* Maximum configuration supported by SNIA hardware. There are other
10 * restrictions that may limit us to a smaller max configuration.
11 */
12 #define MAXNODES 128
13 #define MAXNASIDS 128
14
15 #define CHUNKSZ (64*1024*1024)
16 #define CHUNKSHIFT 26 /* 2 ^^ CHUNKSHIFT == CHUNKSZ */
17
18 extern int cnodeid_map[] ;
19 extern int nasid_map[] ;
20
21 #define CNODEID_TO_NASID(n) (cnodeid_map[(n)])
22 #define NASID_TO_CNODEID(n) (nasid_map[(n)])
23
24 #define MAX_CHUNKS_PER_NODE 128
25
26
27 /*
28 * These are a bunch of sn1 hw specific defines. For now, keep it
29 * in this file. If it gets too diverse we may want to create a
30 * mmhwdefs_sn1.h
31 */
32
33 /*
34 * Structure of the mem config of the node as a SN1 MI reg
35 * Medusa supports this reg config.
36 */
37
38 typedef struct node_memmap_s
39 {
40 unsigned int b0 :1, /* 0 bank 0 present */
41 b1 :1, /* 1 bank 1 present */
42 r01 :2, /* 2-3 reserved */
43 b01size :4, /* 4-7 Size of bank 0 and 1 */
44 b2 :1, /* 8 bank 2 present */
45 b3 :1, /* 9 bank 3 present */
46 r23 :2, /* 10-11 reserved */
47 b23size :4, /* 12-15 Size of bank 2 and 3 */
48 b4 :1, /* 16 bank 4 present */
49 b5 :1, /* 17 bank 5 present */
50 r45 :2, /* 18-19 reserved */
51 b45size :4, /* 20-23 Size of bank 4 and 5 */
52 b6 :1, /* 24 bank 6 present */
53 b7 :1, /* 25 bank 7 present */
54 r67 :2, /* 26-27 reserved */
55 b67size :4; /* 28-31 Size of bank 6 and 7 */
56 } node_memmap_t ;
57
58 #define GBSHIFT 30
59 #define MBSHIFT 20
60
61 /*
62 * SN1 Arch defined values
63 */
64 #define SN1_MAX_BANK_PER_NODE 8
65 #define SN1_BANK_PER_NODE_SHIFT 3 /* derived from SN1_MAX_BANK_PER_NODE */
66 #define SN1_NODE_ADDR_SHIFT (GBSHIFT+3) /* 8GB */
67 #define SN1_BANK_ADDR_SHIFT (SN1_NODE_ADDR_SHIFT-SN1_BANK_PER_NODE_SHIFT)
68
69 #define SN1_BANK_SIZE_SHIFT (MBSHIFT+6) /* 64 MB */
70 #define SN1_MIN_BANK_SIZE_SHIFT SN1_BANK_SIZE_SHIFT
71
72 /*
73 * BankSize nibble to bank size mapping
74 *
75 * 1 - 64 MB
76 * 2 - 128 MB
77 * 3 - 256 MB
78 * 4 - 512 MB
79 * 5 - 1024 MB (1GB)
80 */
81
82 /* fixme - this macro breaks for bsize 6-8 and 0 */
83
84 #ifdef CONFIG_IA64_SGI_SN1_SIM
85 /* Support the medusa hack for 8M/16M/32M nodes */
86 #define BankSizeBytes(bsize) ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\
87 (1<<((bsize-9)+MBSHIFT)))
88 #else
89 #define BankSizeBytes(bsize) (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT))
90 #endif
91
92 #define BankSizeToEFIPages(bsize) ((BankSizeBytes(bsize)) >> 12)
93
94 #define GetPhysAddr(n,b) (((u64)n<<SN1_NODE_ADDR_SHIFT) | \
95 ((u64)b<<SN1_BANK_ADDR_SHIFT))
96
97 #define GetNasId(paddr) ((u64)(paddr) >> SN1_NODE_ADDR_SHIFT)
98
99 #define GetBankId(paddr) \
100 (((u64)(paddr) >> SN1_BANK_ADDR_SHIFT) & 7)
101
102 #define SN1_MAX_BANK_SIZE ((u64)BankSizeBytes(5))
103 #define SN1_BANK_SIZE_MASK (~(SN1_MAX_BANK_SIZE-1))
104
105 #endif /* _ASM_IA64_MMZONE_SN1_H */
106