File: /usr/src/linux/include/asm-ia64/sn/xtalk/xbow.h
1 /* $Id$
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2000 by Colin Ngam
9 */
10 #ifndef _ASM_SN_SN_XTALK_XBOW_H
11 #define _ASM_SN_SN_XTALK_XBOW_H
12
13 /*
14 * xbow.h - header file for crossbow chip and xbow section of xbridge
15 */
16
17 #include <asm/sn/xtalk/xtalk.h>
18 #include <asm/sn/xtalk/xwidget.h>
19 #include <asm/sn/xtalk/xswitch.h>
20 #ifdef LANGUAGE_C
21 #include <asm/sn/xtalk/xbow_info.h>
22 #endif
23
24
25 #define XBOW_DRV_PREFIX "xbow_"
26
27 /* The crossbow chip supports 8 8/16 bits I/O ports, numbered 0x8 through 0xf.
28 * It also implements the widget 0 address space and register set.
29 */
30 #define XBOW_PORT_0 0x0
31 #define XBOW_PORT_8 0x8
32 #define XBOW_PORT_9 0x9
33 #define XBOW_PORT_A 0xa
34 #define XBOW_PORT_B 0xb
35 #define XBOW_PORT_C 0xc
36 #define XBOW_PORT_D 0xd
37 #define XBOW_PORT_E 0xe
38 #define XBOW_PORT_F 0xf
39
40 #define MAX_XBOW_PORTS 8 /* number of ports on xbow chip */
41 #define BASE_XBOW_PORT XBOW_PORT_8 /* Lowest external port */
42 #define MAX_PORT_NUM 0x10 /* maximum port number + 1 */
43 #define XBOW_WIDGET_ID 0 /* xbow is itself widget 0 */
44
45 #define XBOW_CREDIT 4
46
47 #define MAX_XBOW_NAME 16
48
49 #if LANGUAGE_C
50 typedef uint32_t xbowreg_t;
51
52 #define XBOWCONST (xbowreg_t)
53
54 /* Generic xbow register, given base and offset */
55 #define XBOW_REG_PTR(base, offset) ((volatile xbowreg_t*) \
56 ((__psunsigned_t)(base) + (__psunsigned_t)(offset)))
57
58 /* Register set for each xbow link */
59 typedef volatile struct xb_linkregs_s {
60 #ifdef LITTLE_ENDIAN
61 /*
62 * we access these through synergy unswizzled space, so the address
63 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
64 * That's why we put the register first and filler second.
65 */
66 xbowreg_t link_ibf;
67 xbowreg_t filler0; /* filler for proper alignment */
68 xbowreg_t link_control;
69 xbowreg_t filler1;
70 xbowreg_t link_status;
71 xbowreg_t filler2;
72 xbowreg_t link_arb_upper;
73 xbowreg_t filler3;
74 xbowreg_t link_arb_lower;
75 xbowreg_t filler4;
76 xbowreg_t link_status_clr;
77 xbowreg_t filler5;
78 xbowreg_t link_reset;
79 xbowreg_t filler6;
80 xbowreg_t link_aux_status;
81 xbowreg_t filler7;
82 #else
83 xbowreg_t filler0; /* filler for proper alignment */
84 xbowreg_t link_ibf;
85 xbowreg_t filler1;
86 xbowreg_t link_control;
87 xbowreg_t filler2;
88 xbowreg_t link_status;
89 xbowreg_t filler3;
90 xbowreg_t link_arb_upper;
91 xbowreg_t filler4;
92 xbowreg_t link_arb_lower;
93 xbowreg_t filler5;
94 xbowreg_t link_status_clr;
95 xbowreg_t filler6;
96 xbowreg_t link_reset;
97 xbowreg_t filler7;
98 xbowreg_t link_aux_status;
99 #endif /* LITTLE_ENDIAN */
100 } xb_linkregs_t;
101
102 typedef volatile struct xbow_s {
103 /* standard widget configuration 0x000000-0x000057 */
104 widget_cfg_t xb_widget; /* 0x000000 */
105
106 /* helper fieldnames for accessing bridge widget */
107
108 #define xb_wid_id xb_widget.w_id
109 #define xb_wid_stat xb_widget.w_status
110 #define xb_wid_err_upper xb_widget.w_err_upper_addr
111 #define xb_wid_err_lower xb_widget.w_err_lower_addr
112 #define xb_wid_control xb_widget.w_control
113 #define xb_wid_req_timeout xb_widget.w_req_timeout
114 #define xb_wid_int_upper xb_widget.w_intdest_upper_addr
115 #define xb_wid_int_lower xb_widget.w_intdest_lower_addr
116 #define xb_wid_err_cmdword xb_widget.w_err_cmd_word
117 #define xb_wid_llp xb_widget.w_llp_cfg
118 #define xb_wid_stat_clr xb_widget.w_tflush
119
120 #ifdef LITTLE_ENDIAN
121 /*
122 * we access these through synergy unswizzled space, so the address
123 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
124 * That's why we put the register first and filler second.
125 */
126 /* xbow-specific widget configuration 0x000058-0x0000FF */
127 xbowreg_t xb_wid_arb_reload; /* 0x00005C */
128 xbowreg_t _pad_000058;
129 xbowreg_t xb_perf_ctr_a; /* 0x000064 */
130 xbowreg_t _pad_000060;
131 xbowreg_t xb_perf_ctr_b; /* 0x00006c */
132 xbowreg_t _pad_000068;
133 xbowreg_t xb_nic; /* 0x000074 */
134 xbowreg_t _pad_000070;
135
136 /* Xbridge only */
137 xbowreg_t xb_w0_rst_fnc; /* 0x00007C */
138 xbowreg_t _pad_000078;
139 xbowreg_t xb_l8_rst_fnc; /* 0x000084 */
140 xbowreg_t _pad_000080;
141 xbowreg_t xb_l9_rst_fnc; /* 0x00008c */
142 xbowreg_t _pad_000088;
143 xbowreg_t xb_la_rst_fnc; /* 0x000094 */
144 xbowreg_t _pad_000090;
145 xbowreg_t xb_lb_rst_fnc; /* 0x00009c */
146 xbowreg_t _pad_000098;
147 xbowreg_t xb_lc_rst_fnc; /* 0x0000a4 */
148 xbowreg_t _pad_0000a0;
149 xbowreg_t xb_ld_rst_fnc; /* 0x0000ac */
150 xbowreg_t _pad_0000a8;
151 xbowreg_t xb_le_rst_fnc; /* 0x0000b4 */
152 xbowreg_t _pad_0000b0;
153 xbowreg_t xb_lf_rst_fnc; /* 0x0000bc */
154 xbowreg_t _pad_0000b8;
155 xbowreg_t xb_lock; /* 0x0000c4 */
156 xbowreg_t _pad_0000c0;
157 xbowreg_t xb_lock_clr; /* 0x0000cc */
158 xbowreg_t _pad_0000c8;
159 /* end of Xbridge only */
160 xbowreg_t _pad_0000d0[12];
161 #else
162 /* xbow-specific widget configuration 0x000058-0x0000FF */
163 xbowreg_t _pad_000058;
164 xbowreg_t xb_wid_arb_reload; /* 0x00005C */
165 xbowreg_t _pad_000060;
166 xbowreg_t xb_perf_ctr_a; /* 0x000064 */
167 xbowreg_t _pad_000068;
168 xbowreg_t xb_perf_ctr_b; /* 0x00006c */
169 xbowreg_t _pad_000070;
170 xbowreg_t xb_nic; /* 0x000074 */
171
172 /* Xbridge only */
173 xbowreg_t _pad_000078;
174 xbowreg_t xb_w0_rst_fnc; /* 0x00007C */
175 xbowreg_t _pad_000080;
176 xbowreg_t xb_l8_rst_fnc; /* 0x000084 */
177 xbowreg_t _pad_000088;
178 xbowreg_t xb_l9_rst_fnc; /* 0x00008c */
179 xbowreg_t _pad_000090;
180 xbowreg_t xb_la_rst_fnc; /* 0x000094 */
181 xbowreg_t _pad_000098;
182 xbowreg_t xb_lb_rst_fnc; /* 0x00009c */
183 xbowreg_t _pad_0000a0;
184 xbowreg_t xb_lc_rst_fnc; /* 0x0000a4 */
185 xbowreg_t _pad_0000a8;
186 xbowreg_t xb_ld_rst_fnc; /* 0x0000ac */
187 xbowreg_t _pad_0000b0;
188 xbowreg_t xb_le_rst_fnc; /* 0x0000b4 */
189 xbowreg_t _pad_0000b8;
190 xbowreg_t xb_lf_rst_fnc; /* 0x0000bc */
191 xbowreg_t _pad_0000c0;
192 xbowreg_t xb_lock; /* 0x0000c4 */
193 xbowreg_t _pad_0000c8;
194 xbowreg_t xb_lock_clr; /* 0x0000cc */
195 /* end of Xbridge only */
196 xbowreg_t _pad_0000d0[12];
197 #endif /* LITTLE_ENDIAN */
198
199 /* Link Specific Registers, port 8..15 0x000100-0x000300 */
200 xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
201 #define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
202
203 } xbow_t;
204
205 /* Configuration structure which describes each xbow link */
206 typedef struct xbow_cfg_s {
207 int xb_port; /* port number (0-15) */
208 int xb_flags; /* port software flags */
209 short xb_shift; /* shift for arb reg (mask is 0xff) */
210 short xb_ul; /* upper or lower arb reg */
211 int xb_pad; /* use this later (pad to ptr align) */
212 xb_linkregs_t *xb_linkregs; /* pointer to link registers */
213 widget_cfg_t *xb_widget; /* pointer to widget registers */
214 char xb_name[MAX_XBOW_NAME]; /* port name */
215 xbowreg_t xb_sh_arb_upper; /* shadow upper arb register */
216 xbowreg_t xb_sh_arb_lower; /* shadow lower arb register */
217 } xbow_cfg_t;
218
219 #define XB_FLAGS_EXISTS 0x1 /* device exists */
220 #define XB_FLAGS_MASTER 0x2
221 #define XB_FLAGS_SLAVE 0x0
222 #define XB_FLAGS_GBR 0x4
223 #define XB_FLAGS_16BIT 0x8
224 #define XB_FLAGS_8BIT 0x0
225
226 /* get xbow config information for port p */
227 #define XB_CONFIG(p) xbow_cfg[xb_ports[p]]
228
229 /* is widget port number valid? (based on version 7.0 of xbow spec) */
230 #define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
231
232 /* whether to use upper or lower arbitration register, given source widget id */
233 #define XBOW_ARB_IS_UPPER(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
234 #define XBOW_ARB_IS_LOWER(wid) ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
235
236 /* offset of arbitration register, given source widget id */
237 #define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
238
239 #endif /* LANGUAGE_C */
240
241 #define XBOW_WID_ID WIDGET_ID
242 #define XBOW_WID_STAT WIDGET_STATUS
243 #define XBOW_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
244 #define XBOW_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
245 #define XBOW_WID_CONTROL WIDGET_CONTROL
246 #define XBOW_WID_REQ_TO WIDGET_REQ_TIMEOUT
247 #define XBOW_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
248 #define XBOW_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
249 #define XBOW_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
250 #define XBOW_WID_LLP WIDGET_LLP_CFG
251 #define XBOW_WID_STAT_CLR WIDGET_TFLUSH
252 #define XBOW_WID_ARB_RELOAD 0x5c
253 #define XBOW_WID_PERF_CTR_A 0x64
254 #define XBOW_WID_PERF_CTR_B 0x6c
255 #define XBOW_WID_NIC 0x74
256
257 /* Xbridge only */
258 #define XBOW_W0_RST_FNC 0x00007C
259 #define XBOW_L8_RST_FNC 0x000084
260 #define XBOW_L9_RST_FNC 0x00008c
261 #define XBOW_LA_RST_FNC 0x000094
262 #define XBOW_LB_RST_FNC 0x00009c
263 #define XBOW_LC_RST_FNC 0x0000a4
264 #define XBOW_LD_RST_FNC 0x0000ac
265 #define XBOW_LE_RST_FNC 0x0000b4
266 #define XBOW_LF_RST_FNC 0x0000bc
267 #define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
268 (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
269 ((x) == 0) ? XBOW_W0_RST_FNC : 0
270 #define XBOW_LOCK 0x0000c4
271 #define XBOW_LOCK_CLR 0x0000cc
272 /* End of Xbridge only */
273
274 /* used only in ide, but defined here within the reserved portion */
275 /* of the widget0 address space (before 0xf4) */
276 #define XBOW_WID_UNDEF 0xe4
277
278 /* pointer to link arbitration register, given xbow base, dst and src widget id */
279 #define XBOW_PRIO_ARBREG_PTR(base, dst_wid, src_wid) \
280 XBOW_REG_PTR(XBOW_PRIO_LINKREGS_PTR(base, dst_wid), XBOW_ARB_OFF(src_wid))
281
282 /* pointer to link registers base, given xbow base and destination widget id */
283 #define XBOW_PRIO_LINKREGS_PTR(base, dst_wid) (xb_linkregs_t*) \
284 XBOW_REG_PTR(base, XB_LINK_REG_BASE(dst_wid))
285
286 /* xbow link register set base, legal value for x is 0x8..0xf */
287 #define XB_LINK_BASE 0x100
288 #define XB_LINK_OFFSET 0x40
289 #define XB_LINK_REG_BASE(x) (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
290
291 #define XB_LINK_IBUF_FLUSH(x) (XB_LINK_REG_BASE(x) + 0x4)
292 #define XB_LINK_CTRL(x) (XB_LINK_REG_BASE(x) + 0xc)
293 #define XB_LINK_STATUS(x) (XB_LINK_REG_BASE(x) + 0x14)
294 #define XB_LINK_ARB_UPPER(x) (XB_LINK_REG_BASE(x) + 0x1c)
295 #define XB_LINK_ARB_LOWER(x) (XB_LINK_REG_BASE(x) + 0x24)
296 #define XB_LINK_STATUS_CLR(x) (XB_LINK_REG_BASE(x) + 0x2c)
297 #define XB_LINK_RESET(x) (XB_LINK_REG_BASE(x) + 0x34)
298 #define XB_LINK_AUX_STATUS(x) (XB_LINK_REG_BASE(x) + 0x3c)
299
300 /* link_control(x) */
301 #define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */
302 /* reserved: 0x40000000 */
303 #define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */
304 #define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */
305 #define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */
306 #define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */
307 #define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */
308 #define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */
309 #define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */
310 #define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */
311 /* reserved: 0x0000fe00 */
312 #define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */
313 #define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */
314 #define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */
315 #define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */
316 #define XB_CTRL_RCV_IE 0x00000010 /* receive */
317 #define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */
318 /* reserved: 0x00000004 */
319 #define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */
320 #define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */
321
322 /* link_status(x) */
323 #define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE
324 /* reserved: 0x7ff80000 */
325 #define XB_STAT_MULTI_ERR 0x00040000 /* multi error */
326 #define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE
327 #define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE
328 #define XB_STAT_BNDWDTH_ALLOC_ID_MSK 0x0000ff00 /* port bitmask */
329 #define XB_STAT_RCV_CNT_OFLOW_ERR XB_CTRL_RCV_CNT_OFLOW_IE
330 #define XB_STAT_XMT_CNT_OFLOW_ERR XB_CTRL_XMT_CNT_OFLOW_IE
331 #define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE
332 #define XB_STAT_RCV_ERR XB_CTRL_RCV_IE
333 #define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE
334 /* reserved: 0x00000004 */
335 #define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE
336 #define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE
337
338 /* link_aux_status(x) */
339 #define XB_AUX_STAT_RCV_CNT 0xff000000
340 #define XB_AUX_STAT_XMT_CNT 0x00ff0000
341 #define XB_AUX_STAT_TOUT_DST 0x0000ff00
342 #define XB_AUX_LINKFAIL_RST_BAD 0x00000040
343 #define XB_AUX_STAT_PRESENT 0x00000020
344 #define XB_AUX_STAT_PORT_WIDTH 0x00000010
345 /* reserved: 0x0000000f */
346
347 /*
348 * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
349 * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
350 */
351 #define XB_ARB_GBR_MSK 0x1f
352 #define XB_ARB_RR_MSK 0x7
353 #define XB_ARB_GBR_SHFT(x) (((x) & 0x3) * 8)
354 #define XB_ARB_RR_SHFT(x) (((x) & 0x3) * 8 + 5)
355 #define XB_ARB_GBR_CNT(reg,x) ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
356 #define XB_ARB_RR_CNT(reg,x) ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
357
358 /* XBOW_WID_STAT */
359 #define XB_WID_STAT_LINK_INTR_SHFT (24)
360 #define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT)
361 #define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
362 #define XB_WID_STAT_WIDGET0_INTR 0x00800000
363 #define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */
364 #define XB_WID_STAT_REG_ACC_ERR 0x00000020
365 #define XB_WID_STAT_RECV_TOUT 0x00000010 /* Xbridge only */
366 #define XB_WID_STAT_ARB_TOUT 0x00000008 /* Xbridge only */
367 #define XB_WID_STAT_XTALK_ERR 0x00000004
368 #define XB_WID_STAT_DST_TOUT 0x00000002 /* Xbridge only */
369 #define XB_WID_STAT_MULTI_ERR 0x00000001
370
371 #define XB_WID_STAT_SRCID_SHFT 6
372
373 /* XBOW_WID_CONTROL */
374 #define XB_WID_CTRL_REG_ACC_IE XB_WID_STAT_REG_ACC_ERR
375 #define XB_WID_CTRL_RECV_TOUT XB_WID_STAT_RECV_TOUT
376 #define XB_WID_CTRL_ARB_TOUT XB_WID_STAT_ARB_TOUT
377 #define XB_WID_CTRL_XTALK_IE XB_WID_STAT_XTALK_ERR
378
379 /* XBOW_WID_INT_UPPER */
380 /* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
381
382 /* XBOW WIDGET part number, in the ID register */
383 #define XBOW_WIDGET_PART_NUM 0x0 /* crossbow */
384 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */
385 #define XBOW_WIDGET_MFGR_NUM 0x0
386 #define XXBOW_WIDGET_MFGR_NUM 0x0
387
388 #define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */
389 #define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */
390 #define XBOW_REV_1_2 0x3 /* xbow rev 1.2 is "3" */
391 #define XBOW_REV_1_3 0x4 /* xbow rev 1.3 is "4" */
392 #define XBOW_REV_2_0 0x5 /* xbow rev 2.0 is "5" */
393
394 #define XXBOW_PART_REV_1_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
395 #define XXBOW_PART_REV_2_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
396
397 /* XBOW_WID_ARB_RELOAD */
398 #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */
399
400
401 #define nasid_has_xbridge(nasid) \
402 (XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM)
403
404
405 #ifdef _LANGUAGE_C
406 /*
407 * XBOW Widget 0 Register formats.
408 * Format for many of these registers are similar to the standard
409 * widget register format described as part of xtalk specification
410 * Standard widget register field format description is available in
411 * xwidget.h
412 * Following structures define the format for xbow widget 0 registers
413 */
414 /*
415 * Xbow Widget 0 Command error word
416 */
417 #ifdef LITTLE_ENDIAN
418
419 typedef union xbw0_cmdword_u {
420 xbowreg_t cmdword;
421 struct {
422 uint32_t rsvd:8, /* Reserved */
423 barr:1, /* Barrier operation */
424 error:1, /* Error Occured */
425 vbpm:1, /* Virtual Backplane message */
426 gbr:1, /* GBR enable ? */
427 ds:2, /* Data size */
428 ct:1, /* Is it a coherent transaction */
429 tnum:5, /* Transaction Number */
430 pactyp:4, /* Packet type: */
431 srcid:4, /* Source ID number */
432 destid:4; /* Desination ID number */
433
434 } xbw0_cmdfield;
435 } xbw0_cmdword_t;
436
437 #else
438
439 typedef union xbw0_cmdword_u {
440 xbowreg_t cmdword;
441 struct {
442 uint32_t destid:4, /* Desination ID number */
443 srcid:4, /* Source ID number */
444 pactyp:4, /* Packet type: */
445 tnum:5, /* Transaction Number */
446 ct:1, /* Is it a coherent transaction */
447 ds:2, /* Data size */
448 gbr:1, /* GBR enable ? */
449 vbpm:1, /* Virtual Backplane message */
450 error:1, /* Error Occured */
451 barr:1, /* Barrier operation */
452 rsvd:8; /* Reserved */
453 } xbw0_cmdfield;
454 } xbw0_cmdword_t;
455
456 #endif
457
458 #define xbcmd_destid xbw0_cmdfield.destid
459 #define xbcmd_srcid xbw0_cmdfield.srcid
460 #define xbcmd_pactyp xbw0_cmdfield.pactyp
461 #define xbcmd_tnum xbw0_cmdfield.tnum
462 #define xbcmd_ct xbw0_cmdfield.ct
463 #define xbcmd_ds xbw0_cmdfield.ds
464 #define xbcmd_gbr xbw0_cmdfield.gbr
465 #define xbcmd_vbpm xbw0_cmdfield.vbpm
466 #define xbcmd_error xbw0_cmdfield.error
467 #define xbcmd_barr xbw0_cmdfield.barr
468
469 /*
470 * Values for field PACTYP in xbow error command word
471 */
472 #define XBCMDTYP_READREQ 0 /* Read Request packet */
473 #define XBCMDTYP_READRESP 1 /* Read Response packet */
474 #define XBCMDTYP_WRREQ_RESP 2 /* Write Request with response */
475 #define XBCMDTYP_WRRESP 3 /* Write Response */
476 #define XBCMDTYP_WRREQ_NORESP 4 /* Write request with No Response */
477 #define XBCMDTYP_FETCHOP 6 /* Fetch & Op packet */
478 #define XBCMDTYP_STOREOP 8 /* Store & Op packet */
479 #define XBCMDTYP_SPLPKT_REQ 0xE /* Special packet request */
480 #define XBCMDTYP_SPLPKT_RESP 0xF /* Special packet response */
481
482 /*
483 * Values for field ds (datasize) in xbow error command word
484 */
485 #define XBCMDSZ_DOUBLEWORD 0
486 #define XBCMDSZ_QUARTRCACHE 1
487 #define XBCMDSZ_FULLCACHE 2
488
489 /*
490 * Xbow widget 0 Status register format.
491 */
492 #ifdef LITTLE_ENDIAN
493
494 typedef union xbw0_status_u {
495 xbowreg_t statusword;
496 struct {
497 uint32_t mult_err:1, /* Multiple error occurred */
498 connect_tout:1, /* Connection timeout */
499 xtalk_err:1, /* Xtalk pkt with error bit */
500 /* End of Xbridge only */
501 w0_arb_tout, /* arbiter timeout err */
502 w0_recv_tout, /* receive timeout err */
503 /* Xbridge only */
504 regacc_err:1, /* Reg Access error */
505 src_id:4, /* source id. Xbridge only */
506 resvd1:13,
507 wid0intr:1; /* Widget 0 err intr */
508 } xbw0_stfield;
509 } xbw0_status_t;
510
511 #else
512
513 typedef union xbw0_status_u {
514 xbowreg_t statusword;
515 struct {
516 uint32_t linkXintr:8, /* link(x) error intr */
517 wid0intr:1, /* Widget 0 err intr */
518 resvd1:13,
519 src_id:4, /* source id. Xbridge only */
520 regacc_err:1, /* Reg Access error */
521 /* Xbridge only */
522 w0_recv_tout, /* receive timeout err */
523 w0_arb_tout, /* arbiter timeout err */
524 /* End of Xbridge only */
525 xtalk_err:1, /* Xtalk pkt with error bit */
526 connect_tout:1, /* Connection timeout */
527 mult_err:1; /* Multiple error occurred */
528 } xbw0_stfield;
529 } xbw0_status_t;
530
531 #endif
532
533 #define xbst_linkXintr xbw0_stfield.linkXintr
534 #define xbst_w0intr xbw0_stfield.wid0intr
535 #define xbst_regacc_err xbw0_stfield.regacc_err
536 #define xbst_xtalk_err xbw0_stfield.xtalk_err
537 #define xbst_connect_tout xbw0_stfield.connect_tout
538 #define xbst_mult_err xbw0_stfield.mult_err
539 #define xbst_src_id xbw0_stfield.src_id /* Xbridge only */
540 #define xbst_w0_recv_tout xbw0_stfield.w0_recv_tout /* Xbridge only */
541 #define xbst_w0_arb_tout xbw0_stfield.w0_arb_tout /* Xbridge only */
542
543 /*
544 * Xbow widget 0 Control register format
545 */
546 #ifdef LITTLE_ENDIAN
547
548 typedef union xbw0_ctrl_u {
549 xbowreg_t ctrlword;
550 struct {
551 uint32_t
552 resvd3:1,
553 conntout_intr:1,
554 xtalkerr_intr:1,
555 w0_arg_tout_intr:1, /* Xbridge only */
556 w0_recv_tout_intr:1, /* Xbridge only */
557 accerr_intr:1,
558 enable_w0_tout_cntr:1, /* Xbridge only */
559 enable_watchdog:1, /* Xbridge only */
560 resvd1:24;
561 } xbw0_ctrlfield;
562 } xbw0_ctrl_t;
563
564 #else
565
566 typedef union xbw0_ctrl_u {
567 xbowreg_t ctrlword;
568 struct {
569 uint32_t
570 resvd1:24,
571 enable_watchdog:1, /* Xbridge only */
572 enable_w0_tout_cntr:1, /* Xbridge only */
573 accerr_intr:1,
574 w0_recv_tout_intr:1, /* Xbridge only */
575 w0_arg_tout_intr:1, /* Xbridge only */
576 xtalkerr_intr:1,
577 conntout_intr:1,
578 resvd3:1;
579 } xbw0_ctrlfield;
580 } xbw0_ctrl_t;
581
582 #endif
583
584 #ifdef LITTLE_ENDIAN
585
586 typedef union xbow_linkctrl_u {
587 xbowreg_t xbl_ctrlword;
588 struct {
589 uint32_t srcto_intr:1,
590 maxto_intr:1,
591 rsvd3:1,
592 trx_retry_intr:1,
593 rcv_err_intr:1,
594 trx_max_retry_intr:1,
595 trxov_intr:1,
596 rcvov_intr:1,
597 bwalloc_intr:1,
598 rsvd2:7,
599 obuf_intr:1,
600 idest_intr:1,
601 llp_credit:5,
602 force_badllp:1,
603 send_bm8:1,
604 inbuf_level:3,
605 perf_mode:2,
606 rsvd1:1,
607 alive_intr:1;
608
609 } xb_linkcontrol;
610 } xbow_linkctrl_t;
611
612 #else
613
614 typedef union xbow_linkctrl_u {
615 xbowreg_t xbl_ctrlword;
616 struct {
617 uint32_t alive_intr:1,
618 rsvd1:1,
619 perf_mode:2,
620 inbuf_level:3,
621 send_bm8:1,
622 force_badllp:1,
623 llp_credit:5,
624 idest_intr:1,
625 obuf_intr:1,
626 rsvd2:7,
627 bwalloc_intr:1,
628 rcvov_intr:1,
629 trxov_intr:1,
630 trx_max_retry_intr:1,
631 rcv_err_intr:1,
632 trx_retry_intr:1,
633 rsvd3:1,
634 maxto_intr:1,
635 srcto_intr:1;
636 } xb_linkcontrol;
637 } xbow_linkctrl_t;
638
639 #endif
640
641
642 #define xbctl_accerr_intr (xbw0_ctrlfield.accerr_intr)
643 #define xbctl_xtalkerr_intr (xbw0_ctrlfield.xtalkerr_intr)
644 #define xbctl_cnntout_intr (xbw0_ctrlfield.conntout_intr)
645
646 #define XBW0_CTRL_ACCERR_INTR (1 << 5)
647 #define XBW0_CTRL_XTERR_INTR (1 << 2)
648 #define XBW0_CTRL_CONNTOUT_INTR (1 << 1)
649
650 /*
651 * Xbow Link specific Registers structure definitions.
652 */
653
654 #ifdef LITTLE_ENDIAN
655
656 typedef union xbow_linkX_status_u {
657 xbowreg_t linkstatus;
658 struct {
659 uint32_t pkt_toutsrc:1,
660 pkt_toutconn:1, /* max_req_tout in Xbridge */
661 pkt_toutdest:1, /* reserved in Xbridge */
662 llp_xmitretry:1,
663 llp_rcverror:1,
664 llp_maxtxretry:1,
665 llp_txovflow:1,
666 llp_rxovflow:1,
667 bw_errport:8, /* BW allocation error port */
668 ioe:1, /* Input overallocation error */
669 illdest:1,
670 merror:1,
671 resvd1:12,
672 alive:1;
673 } xb_linkstatus;
674 } xbwX_stat_t;
675
676 #else
677
678 typedef union xbow_linkX_status_u {
679 xbowreg_t linkstatus;
680 struct {
681 uint32_t alive:1,
682 resvd1:12,
683 merror:1,
684 illdest:1,
685 ioe:1, /* Input overallocation error */
686 bw_errport:8, /* BW allocation error port */
687 llp_rxovflow:1,
688 llp_txovflow:1,
689 llp_maxtxretry:1,
690 llp_rcverror:1,
691 llp_xmitretry:1,
692 pkt_toutdest:1, /* reserved in Xbridge */
693 pkt_toutconn:1, /* max_req_tout in Xbridge */
694 pkt_toutsrc:1;
695 } xb_linkstatus;
696 } xbwX_stat_t;
697
698 #endif
699
700 #define link_alive xb_linkstatus.alive
701 #define link_multierror xb_linkstatus.merror
702 #define link_illegal_dest xb_linkstatus.illdest
703 #define link_ioe xb_linkstatus.ioe
704 #define link_max_req_tout xb_linkstatus.pkt_toutconn /* Xbridge */
705 #define link_pkt_toutconn xb_linkstatus.pkt_toutconn /* Xbow */
706 #define link_pkt_toutdest xb_linkstatus.pkt_toutdest
707 #define link_pkt_toutsrc xb_linkstatus.pkt_toutsrc
708
709 #ifdef LITTLE_ENDIAN
710
711 typedef union xbow_aux_linkX_status_u {
712 xbowreg_t aux_linkstatus;
713 struct {
714 uint32_t rsvd2:4,
715 bit_mode_8:1,
716 wid_present:1,
717 fail_mode:1,
718 rsvd1:1,
719 to_src_loc:8,
720 tx_retry_cnt:8,
721 rx_err_cnt:8;
722 } xb_aux_linkstatus;
723 } xbow_aux_link_status_t;
724
725 #else
726
727 typedef union xbow_aux_linkX_status_u {
728 xbowreg_t aux_linkstatus;
729 struct {
730 uint32_t rx_err_cnt:8,
731 tx_retry_cnt:8,
732 to_src_loc:8,
733 rsvd1:1,
734 fail_mode:1,
735 wid_present:1,
736 bit_mode_8:1,
737 rsvd2:4;
738 } xb_aux_linkstatus;
739 } xbow_aux_link_status_t;
740
741 #endif
742
743
744 #ifdef LITTLE_ENDIAN
745
746 typedef union xbow_perf_count_u {
747 xbowreg_t xb_counter_val;
748 struct {
749 uint32_t count:20,
750 link_select:3,
751 rsvd:9;
752 } xb_perf;
753 } xbow_perfcount_t;
754
755 #else
756
757 typedef union xbow_perf_count_u {
758 xbowreg_t xb_counter_val;
759 struct {
760 uint32_t rsvd:9,
761 link_select:3,
762 count:20;
763 } xb_perf;
764 } xbow_perfcount_t;
765
766 #endif
767
768 #define XBOW_COUNTER_MASK 0xFFFFF
769
770 extern int xbow_widget_present(xbow_t * xbow, int port);
771
772 extern xwidget_intr_preset_f xbow_intr_preset;
773 extern xswitch_reset_link_f xbow_reset_link;
774 void xbow_mlreset(xbow_t *);
775
776 /* ========================================================================
777 */
778
779 #ifdef MACROFIELD_LINE
780 /*
781 * This table forms a relation between the byte offset macros normally
782 * used for ASM coding and the calculated byte offsets of the fields
783 * in the C structure.
784 *
785 * See xbow_check.c xbow_html.c for further details.
786 */
787 #ifndef MACROFIELD_LINE_BITFIELD
788 #define MACROFIELD_LINE_BITFIELD(m) /* ignored */
789 #endif
790
791 struct macrofield_s xbow_macrofield[] =
792 {
793
794 MACROFIELD_LINE(XBOW_WID_ID, xb_wid_id)
795 MACROFIELD_LINE(XBOW_WID_STAT, xb_wid_stat)
796 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xF))
797 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xE))
798 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xD))
799 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xC))
800 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xB))
801 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0xA))
802 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x9))
803 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_LINK_INTR(0x8))
804 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_WIDGET0_INTR)
805 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_REG_ACC_ERR)
806 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_XTALK_ERR)
807 MACROFIELD_LINE_BITFIELD(XB_WID_STAT_MULTI_ERR)
808 MACROFIELD_LINE(XBOW_WID_ERR_UPPER, xb_wid_err_upper)
809 MACROFIELD_LINE(XBOW_WID_ERR_LOWER, xb_wid_err_lower)
810 MACROFIELD_LINE(XBOW_WID_CONTROL, xb_wid_control)
811 MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_REG_ACC_IE)
812 MACROFIELD_LINE_BITFIELD(XB_WID_CTRL_XTALK_IE)
813 MACROFIELD_LINE(XBOW_WID_REQ_TO, xb_wid_req_timeout)
814 MACROFIELD_LINE(XBOW_WID_INT_UPPER, xb_wid_int_upper)
815 MACROFIELD_LINE(XBOW_WID_INT_LOWER, xb_wid_int_lower)
816 MACROFIELD_LINE(XBOW_WID_ERR_CMDWORD, xb_wid_err_cmdword)
817 MACROFIELD_LINE(XBOW_WID_LLP, xb_wid_llp)
818 MACROFIELD_LINE(XBOW_WID_STAT_CLR, xb_wid_stat_clr)
819 MACROFIELD_LINE(XBOW_WID_ARB_RELOAD, xb_wid_arb_reload)
820 MACROFIELD_LINE(XBOW_WID_PERF_CTR_A, xb_perf_ctr_a)
821 MACROFIELD_LINE(XBOW_WID_PERF_CTR_B, xb_perf_ctr_b)
822 MACROFIELD_LINE(XBOW_WID_NIC, xb_nic)
823 MACROFIELD_LINE(XB_LINK_REG_BASE(8), xb_link(8))
824 MACROFIELD_LINE(XB_LINK_IBUF_FLUSH(8), xb_link(8).link_ibf)
825 MACROFIELD_LINE(XB_LINK_CTRL(8), xb_link(8).link_control)
826 MACROFIELD_LINE_BITFIELD(XB_CTRL_LINKALIVE_IE)
827 MACROFIELD_LINE_BITFIELD(XB_CTRL_PERF_CTR_MODE_MSK)
828 MACROFIELD_LINE_BITFIELD(XB_CTRL_IBUF_LEVEL_MSK)
829 MACROFIELD_LINE_BITFIELD(XB_CTRL_8BIT_MODE)
830 MACROFIELD_LINE_BITFIELD(XB_CTRL_BAD_LLP_PKT)
831 MACROFIELD_LINE_BITFIELD(XB_CTRL_WIDGET_CR_MSK)
832 MACROFIELD_LINE_BITFIELD(XB_CTRL_ILLEGAL_DST_IE)
833 MACROFIELD_LINE_BITFIELD(XB_CTRL_OALLOC_IBUF_IE)
834 MACROFIELD_LINE_BITFIELD(XB_CTRL_BNDWDTH_ALLOC_IE)
835 MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_CNT_OFLOW_IE)
836 MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_CNT_OFLOW_IE)
837 MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_MAX_RTRY_IE)
838 MACROFIELD_LINE_BITFIELD(XB_CTRL_RCV_IE)
839 MACROFIELD_LINE_BITFIELD(XB_CTRL_XMT_RTRY_IE)
840 MACROFIELD_LINE_BITFIELD(XB_CTRL_MAXREQ_TOUT_IE)
841 MACROFIELD_LINE_BITFIELD(XB_CTRL_SRC_TOUT_IE)
842 MACROFIELD_LINE(XB_LINK_STATUS(8), xb_link(8).link_status)
843 MACROFIELD_LINE_BITFIELD(XB_STAT_LINKALIVE)
844 MACROFIELD_LINE_BITFIELD(XB_STAT_MULTI_ERR)
845 MACROFIELD_LINE_BITFIELD(XB_STAT_ILLEGAL_DST_ERR)
846 MACROFIELD_LINE_BITFIELD(XB_STAT_OALLOC_IBUF_ERR)
847 MACROFIELD_LINE_BITFIELD(XB_STAT_BNDWDTH_ALLOC_ID_MSK)
848 MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_CNT_OFLOW_ERR)
849 MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_CNT_OFLOW_ERR)
850 MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_MAX_RTRY_ERR)
851 MACROFIELD_LINE_BITFIELD(XB_STAT_RCV_ERR)
852 MACROFIELD_LINE_BITFIELD(XB_STAT_XMT_RTRY_ERR)
853 MACROFIELD_LINE_BITFIELD(XB_STAT_MAXREQ_TOUT_ERR)
854 MACROFIELD_LINE_BITFIELD(XB_STAT_SRC_TOUT_ERR)
855 MACROFIELD_LINE(XB_LINK_ARB_UPPER(8), xb_link(8).link_arb_upper)
856 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xb))
857 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xb))
858 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xa))
859 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xa))
860 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x9))
861 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x9))
862 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0x8))
863 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0x8))
864 MACROFIELD_LINE(XB_LINK_ARB_LOWER(8), xb_link(8).link_arb_lower)
865 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xf))
866 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xf))
867 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xe))
868 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xe))
869 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xd))
870 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xd))
871 MACROFIELD_LINE_BITFIELD(XB_ARB_RR_MSK << XB_ARB_RR_SHFT(0xc))
872 MACROFIELD_LINE_BITFIELD(XB_ARB_GBR_MSK << XB_ARB_GBR_SHFT(0xc))
873 MACROFIELD_LINE(XB_LINK_STATUS_CLR(8), xb_link(8).link_status_clr)
874 MACROFIELD_LINE(XB_LINK_RESET(8), xb_link(8).link_reset)
875 MACROFIELD_LINE(XB_LINK_AUX_STATUS(8), xb_link(8).link_aux_status)
876 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_RCV_CNT)
877 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_XMT_CNT)
878 MACROFIELD_LINE_BITFIELD(XB_AUX_LINKFAIL_RST_BAD)
879 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PRESENT)
880 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_PORT_WIDTH)
881 MACROFIELD_LINE_BITFIELD(XB_AUX_STAT_TOUT_DST)
882 MACROFIELD_LINE(XB_LINK_REG_BASE(0x8), xb_link(0x8))
883 MACROFIELD_LINE(XB_LINK_REG_BASE(0x9), xb_link(0x9))
884 MACROFIELD_LINE(XB_LINK_REG_BASE(0xA), xb_link(0xA))
885 MACROFIELD_LINE(XB_LINK_REG_BASE(0xB), xb_link(0xB))
886 MACROFIELD_LINE(XB_LINK_REG_BASE(0xC), xb_link(0xC))
887 MACROFIELD_LINE(XB_LINK_REG_BASE(0xD), xb_link(0xD))
888 MACROFIELD_LINE(XB_LINK_REG_BASE(0xE), xb_link(0xE))
889 MACROFIELD_LINE(XB_LINK_REG_BASE(0xF), xb_link(0xF))
890 }; /* xbow_macrofield[] */
891
892 #endif /* MACROFIELD_LINE */
893
894 #endif /* _LANGUAGE_C */
895 #endif /* _ASM_SN_SN_XTALK_XBOW_H */
896