File: /usr/src/linux/include/asm-alpha/dma.h
1 /*
2 * include/asm-alpha/dma.h
3 *
4 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
5 * use ISA-compatible dma. The only extension is support for high-page
6 * registers that allow to set the top 8 bits of a 32-bit DMA address.
7 * This register should be written last when setting up a DMA address
8 * as this will also enable DMA across 64 KB boundaries.
9 */
10
11 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
12 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
13 * Written by Hennus Bergman, 1992.
14 * High DMA channel support & info by Hannu Savolainen
15 * and John Boyd, Nov. 1992.
16 */
17
18 #ifndef _ASM_DMA_H
19 #define _ASM_DMA_H
20
21 #include <linux/config.h>
22 #include <linux/spinlock.h>
23 #include <asm/io.h>
24
25 #define dma_outb outb
26 #define dma_inb inb
27
28 /*
29 * NOTES about DMA transfers:
30 *
31 * controller 1: channels 0-3, byte operations, ports 00-1F
32 * controller 2: channels 4-7, word operations, ports C0-DF
33 *
34 * - ALL registers are 8 bits only, regardless of transfer size
35 * - channel 4 is not used - cascades 1 into 2.
36 * - channels 0-3 are byte - addresses/counts are for physical bytes
37 * - channels 5-7 are word - addresses/counts are for physical words
38 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
39 * - transfer count loaded to registers is 1 less than actual count
40 * - controller 2 offsets are all even (2x offsets for controller 1)
41 * - page registers for 5-7 don't use data bit 0, represent 128K pages
42 * - page registers for 0-3 use bit 0, represent 64K pages
43 *
44 * DMA transfers are limited to the lower 16MB of _physical_ memory.
45 * Note that addresses loaded into registers must be _physical_ addresses,
46 * not logical addresses (which may differ if paging is active).
47 *
48 * Address mapping for channels 0-3:
49 *
50 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
51 * | ... | | ... | | ... |
52 * | ... | | ... | | ... |
53 * | ... | | ... | | ... |
54 * P7 ... P0 A7 ... A0 A7 ... A0
55 * | Page | Addr MSB | Addr LSB | (DMA registers)
56 *
57 * Address mapping for channels 5-7:
58 *
59 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
60 * | ... | \ \ ... \ \ \ ... \ \
61 * | ... | \ \ ... \ \ \ ... \ (not used)
62 * | ... | \ \ ... \ \ \ ... \
63 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
64 * | Page | Addr MSB | Addr LSB | (DMA registers)
65 *
66 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
67 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
68 * the hardware level, so odd-byte transfers aren't possible).
69 *
70 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
71 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
72 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
73 *
74 */
75
76 #define MAX_DMA_CHANNELS 8
77
78 /* The maximum address that we can perform a DMA transfer to on Alpha XL,
79 due to a hardware SIO (PCI<->ISA bus bridge) chip limitation, is 64MB.
80 See <asm/apecs.h> for more info.
81 */
82 /* The maximum address that we can perform a DMA transfer to on RUFFIAN,
83 due to a hardware SIO (PCI<->ISA bus bridge) chip limitation, is 16MB.
84 See <asm/pyxis.h> for more info.
85 */
86 /* NOTE: we must define the maximum as something less than 64Mb, to prevent
87 virt_to_bus() from returning an address in the first window, for a
88 data area that goes beyond the 64Mb first DMA window. Sigh...
89 We MUST coordinate the maximum with <asm/apecs.h> for consistency.
90 For now, this limit is set to 48Mb...
91 */
92 #define ALPHA_XL_MAX_DMA_ADDRESS (IDENT_ADDR+0x3000000UL)
93 #define ALPHA_RUFFIAN_MAX_DMA_ADDRESS (IDENT_ADDR+0x1000000UL)
94 #define ALPHA_NAUTILUS_MAX_DMA_ADDRESS (IDENT_ADDR+0x1000000UL)
95 #define ALPHA_MAX_DMA_ADDRESS (~0UL)
96
97 #ifdef CONFIG_ALPHA_GENERIC
98 # define MAX_DMA_ADDRESS (alpha_mv.max_dma_address)
99 #else
100 # ifdef CONFIG_ALPHA_XL
101 # define MAX_DMA_ADDRESS ALPHA_XL_MAX_DMA_ADDRESS
102 # elif defined(CONFIG_ALPHA_RUFFIAN)
103 # define MAX_DMA_ADDRESS ALPHA_RUFFIAN_MAX_DMA_ADDRESS
104 # elif defined(CONFIG_ALPHA_NAUTILUS)
105 # define MAX_DMA_ADDRESS ALPHA_NAUTILUS_MAX_DMA_ADDRESS
106 # else
107 # define MAX_DMA_ADDRESS ALPHA_MAX_DMA_ADDRESS
108 # endif
109 #endif
110
111 /* 8237 DMA controllers */
112 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
113 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
114
115 /* DMA controller registers */
116 #define DMA1_CMD_REG 0x08 /* command register (w) */
117 #define DMA1_STAT_REG 0x08 /* status register (r) */
118 #define DMA1_REQ_REG 0x09 /* request register (w) */
119 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
120 #define DMA1_MODE_REG 0x0B /* mode register (w) */
121 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
122 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
123 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
124 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
125 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
126 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
127
128 #define DMA2_CMD_REG 0xD0 /* command register (w) */
129 #define DMA2_STAT_REG 0xD0 /* status register (r) */
130 #define DMA2_REQ_REG 0xD2 /* request register (w) */
131 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
132 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
133 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
134 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
135 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
136 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
137 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
138 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
139
140 #define DMA_ADDR_0 0x00 /* DMA address registers */
141 #define DMA_ADDR_1 0x02
142 #define DMA_ADDR_2 0x04
143 #define DMA_ADDR_3 0x06
144 #define DMA_ADDR_4 0xC0
145 #define DMA_ADDR_5 0xC4
146 #define DMA_ADDR_6 0xC8
147 #define DMA_ADDR_7 0xCC
148
149 #define DMA_CNT_0 0x01 /* DMA count registers */
150 #define DMA_CNT_1 0x03
151 #define DMA_CNT_2 0x05
152 #define DMA_CNT_3 0x07
153 #define DMA_CNT_4 0xC2
154 #define DMA_CNT_5 0xC6
155 #define DMA_CNT_6 0xCA
156 #define DMA_CNT_7 0xCE
157
158 #define DMA_PAGE_0 0x87 /* DMA page registers */
159 #define DMA_PAGE_1 0x83
160 #define DMA_PAGE_2 0x81
161 #define DMA_PAGE_3 0x82
162 #define DMA_PAGE_5 0x8B
163 #define DMA_PAGE_6 0x89
164 #define DMA_PAGE_7 0x8A
165
166 #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
167 #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
168 #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
169 #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
170 #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
171 #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
172 #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
173 #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7)
174
175 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
176 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
177 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
178
179 #define DMA_AUTOINIT 0x10
180
181 extern spinlock_t dma_spin_lock;
182
183 static __inline__ unsigned long claim_dma_lock(void)
184 {
185 unsigned long flags;
186 spin_lock_irqsave(&dma_spin_lock, flags);
187 return flags;
188 }
189
190 static __inline__ void release_dma_lock(unsigned long flags)
191 {
192 spin_unlock_irqrestore(&dma_spin_lock, flags);
193 }
194
195 /* enable/disable a specific DMA channel */
196 static __inline__ void enable_dma(unsigned int dmanr)
197 {
198 if (dmanr<=3)
199 dma_outb(dmanr, DMA1_MASK_REG);
200 else
201 dma_outb(dmanr & 3, DMA2_MASK_REG);
202 }
203
204 static __inline__ void disable_dma(unsigned int dmanr)
205 {
206 if (dmanr<=3)
207 dma_outb(dmanr | 4, DMA1_MASK_REG);
208 else
209 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
210 }
211
212 /* Clear the 'DMA Pointer Flip Flop'.
213 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
214 * Use this once to initialize the FF to a known state.
215 * After that, keep track of it. :-)
216 * --- In order to do that, the DMA routines below should ---
217 * --- only be used while interrupts are disabled! ---
218 */
219 static __inline__ void clear_dma_ff(unsigned int dmanr)
220 {
221 if (dmanr<=3)
222 dma_outb(0, DMA1_CLEAR_FF_REG);
223 else
224 dma_outb(0, DMA2_CLEAR_FF_REG);
225 }
226
227 /* set mode (above) for a specific DMA channel */
228 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
229 {
230 if (dmanr<=3)
231 dma_outb(mode | dmanr, DMA1_MODE_REG);
232 else
233 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
234 }
235
236 /* set extended mode for a specific DMA channel */
237 static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
238 {
239 if (dmanr<=3)
240 dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG);
241 else
242 dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG);
243 }
244
245 /* Set only the page register bits of the transfer address.
246 * This is used for successive transfers when we know the contents of
247 * the lower 16 bits of the DMA current address register.
248 */
249 static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
250 {
251 switch(dmanr) {
252 case 0:
253 dma_outb(pagenr, DMA_PAGE_0);
254 dma_outb((pagenr >> 8), DMA_HIPAGE_0);
255 break;
256 case 1:
257 dma_outb(pagenr, DMA_PAGE_1);
258 dma_outb((pagenr >> 8), DMA_HIPAGE_1);
259 break;
260 case 2:
261 dma_outb(pagenr, DMA_PAGE_2);
262 dma_outb((pagenr >> 8), DMA_HIPAGE_2);
263 break;
264 case 3:
265 dma_outb(pagenr, DMA_PAGE_3);
266 dma_outb((pagenr >> 8), DMA_HIPAGE_3);
267 break;
268 case 5:
269 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
270 dma_outb((pagenr >> 8), DMA_HIPAGE_5);
271 break;
272 case 6:
273 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
274 dma_outb((pagenr >> 8), DMA_HIPAGE_6);
275 break;
276 case 7:
277 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
278 dma_outb((pagenr >> 8), DMA_HIPAGE_7);
279 break;
280 }
281 }
282
283
284 /* Set transfer address & page bits for specific DMA channel.
285 * Assumes dma flipflop is clear.
286 */
287 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
288 {
289 if (dmanr <= 3) {
290 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
291 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
292 } else {
293 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
294 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
295 }
296 set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
297 }
298
299
300 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
301 * a specific DMA channel.
302 * You must ensure the parameters are valid.
303 * NOTE: from a manual: "the number of transfers is one more
304 * than the initial word count"! This is taken into account.
305 * Assumes dma flip-flop is clear.
306 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
307 */
308 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
309 {
310 count--;
311 if (dmanr <= 3) {
312 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
313 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
314 } else {
315 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
316 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
317 }
318 }
319
320
321 /* Get DMA residue count. After a DMA transfer, this
322 * should return zero. Reading this while a DMA transfer is
323 * still in progress will return unpredictable results.
324 * If called before the channel has been used, it may return 1.
325 * Otherwise, it returns the number of _bytes_ left to transfer.
326 *
327 * Assumes DMA flip-flop is clear.
328 */
329 static __inline__ int get_dma_residue(unsigned int dmanr)
330 {
331 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
332 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
333
334 /* using short to get 16-bit wrap around */
335 unsigned short count;
336
337 count = 1 + dma_inb(io_port);
338 count += dma_inb(io_port) << 8;
339
340 return (dmanr<=3)? count : (count<<1);
341 }
342
343
344 /* These are in kernel/dma.c: */
345 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
346 extern void free_dma(unsigned int dmanr); /* release it again */
347 #define KERNEL_HAVE_CHECK_DMA
348 extern int check_dma(unsigned int dmanr);
349
350 /* From PCI */
351
352 #ifdef CONFIG_PCI
353 extern int isa_dma_bridge_buggy;
354 #else
355 #define isa_dma_bridge_buggy (0)
356 #endif
357
358
359 #endif /* _ASM_DMA_H */
360