File: /usr/src/linux/include/asm-alpha/system.h
1 #ifndef __ALPHA_SYSTEM_H
2 #define __ALPHA_SYSTEM_H
3
4 #include <linux/config.h>
5 #include <asm/pal.h>
6 #include <asm/page.h>
7
8 /*
9 * System defines.. Note that this is included both from .c and .S
10 * files, so it does only defines, not any C code.
11 */
12
13 /*
14 * We leave one page for the initial stack page, and one page for
15 * the initial process structure. Also, the console eats 3 MB for
16 * the initial bootloader (one of which we can reclaim later).
17 */
18 #define BOOT_PCB 0x20000000
19 #define BOOT_ADDR 0x20000000
20 /* Remove when official MILO sources have ELF support: */
21 #define BOOT_SIZE (16*1024)
22
23 #ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
24 #define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
25 #else
26 #define KERNEL_START_PHYS 0x800000 /* Wildfire has a huge console */
27 #endif
28
29 #define KERNEL_START (PAGE_OFFSET+KERNEL_START_PHYS)
30 #define SWAPPER_PGD KERNEL_START
31 #define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
32 #define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
33 #define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
34 #define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
35
36 #define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
37
38 /*
39 * This is setup by the secondary bootstrap loader. Because
40 * the zero page is zeroed out as soon as the vm system is
41 * initialized, we need to copy things out into a more permanent
42 * place.
43 */
44 #define PARAM ZERO_PGE
45 #define COMMAND_LINE ((char*)(PARAM + 0x0000))
46 #define COMMAND_LINE_SIZE 256
47 #define INITRD_START (*(unsigned long *) (PARAM+0x100))
48 #define INITRD_SIZE (*(unsigned long *) (PARAM+0x108))
49
50 #ifndef __ASSEMBLY__
51 #include <linux/kernel.h>
52
53 /*
54 * This is the logout header that should be common to all platforms
55 * (assuming they are running OSF/1 PALcode, I guess).
56 */
57 struct el_common {
58 unsigned int size; /* size in bytes of logout area */
59 int sbz1 : 30; /* should be zero */
60 int err2 : 1; /* second error */
61 int retry : 1; /* retry flag */
62 unsigned int proc_offset; /* processor-specific offset */
63 unsigned int sys_offset; /* system-specific offset */
64 unsigned long code; /* machine check code */
65 };
66
67 /* Machine Check Frame for uncorrectable errors (Large format)
68 * --- This is used to log uncorrectable errors such as
69 * double bit ECC errors.
70 * --- These errors are detected by both processor and systems.
71 */
72 struct el_common_EV5_uncorrectable_mcheck {
73 unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */
74 unsigned long paltemp[24]; /* PAL TEMP REGS. */
75 unsigned long exc_addr; /* Address of excepting instruction*/
76 unsigned long exc_sum; /* Summary of arithmetic traps. */
77 unsigned long exc_mask; /* Exception mask (from exc_sum). */
78 unsigned long pal_base; /* Base address for PALcode. */
79 unsigned long isr; /* Interrupt Status Reg. */
80 unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */
81 unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity
82 <12> set TAG parity*/
83 unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1:
84 <2> Data error in bank 0
85 <3> Data error in bank 1
86 <4> Tag error in bank 0
87 <5> Tag error in bank 1 */
88 unsigned long va; /* Effective VA of fault or miss. */
89 unsigned long mm_stat; /* Holds the reason for D-stream
90 fault or D-cache parity errors */
91 unsigned long sc_addr; /* Address that was being accessed
92 when EV5 detected Secondary cache
93 failure. */
94 unsigned long sc_stat; /* Helps determine if the error was
95 TAG/Data parity(Secondary Cache)*/
96 unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
97 unsigned long ei_addr; /* Physical address of any transfer
98 that is logged in EV5 EI_STAT */
99 unsigned long fill_syndrome; /* For correcting ECC errors. */
100 unsigned long ei_stat; /* Helps identify reason of any
101 processor uncorrectable error
102 at its external interface. */
103 unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/
104 };
105
106 struct el_common_EV6_mcheck {
107 unsigned int FrameSize; /* Bytes, including this field */
108 unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */
109 unsigned int CpuOffset; /* Offset to CPU-specific info */
110 unsigned int SystemOffset; /* Offset to system-specific info */
111 unsigned int MCHK_Code;
112 unsigned int MCHK_Frame_Rev;
113 unsigned long I_STAT; /* EV6 Internal Processor Registers */
114 unsigned long DC_STAT; /* (See the 21264 Spec) */
115 unsigned long C_ADDR;
116 unsigned long DC1_SYNDROME;
117 unsigned long DC0_SYNDROME;
118 unsigned long C_STAT;
119 unsigned long C_STS;
120 unsigned long RESERVED0;
121 unsigned long EXC_ADDR;
122 unsigned long IER_CM;
123 unsigned long ISUM;
124 unsigned long MM_STAT;
125 unsigned long PAL_BASE;
126 unsigned long I_CTL;
127 unsigned long PCTX;
128 };
129
130 extern void halt(void) __attribute__((noreturn));
131 #define __halt() __asm__ __volatile__ ("call_pal %0 #halt" : : "i" (PAL_halt))
132
133 #define prepare_to_switch() do { } while(0)
134 #define switch_to(prev,next,last) \
135 do { \
136 unsigned long pcbb; \
137 current = (next); \
138 pcbb = virt_to_phys(¤t->thread); \
139 (last) = alpha_switch_to(pcbb, (prev)); \
140 check_mmu_context(); \
141 } while (0)
142
143 extern struct task_struct* alpha_switch_to(unsigned long, struct task_struct*);
144
145 #define mb() \
146 __asm__ __volatile__("mb": : :"memory")
147
148 #define rmb() \
149 __asm__ __volatile__("mb": : :"memory")
150
151 #define wmb() \
152 __asm__ __volatile__("wmb": : :"memory")
153
154 #ifdef CONFIG_SMP
155 #define smp_mb() mb()
156 #define smp_rmb() rmb()
157 #define smp_wmb() wmb()
158 #else
159 #define smp_mb() barrier()
160 #define smp_rmb() barrier()
161 #define smp_wmb() barrier()
162 #endif
163
164 #define set_mb(var, value) \
165 do { var = value; mb(); } while (0)
166
167 #define set_wmb(var, value) \
168 do { var = value; wmb(); } while (0)
169
170 #define imb() \
171 __asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
172
173 #define draina() \
174 __asm__ __volatile__ ("call_pal %0 #draina" : : "i" (PAL_draina) : "memory")
175
176 enum implver_enum {
177 IMPLVER_EV4,
178 IMPLVER_EV5,
179 IMPLVER_EV6
180 };
181
182 #ifdef CONFIG_ALPHA_GENERIC
183 #define implver() \
184 ({ unsigned long __implver; \
185 __asm__ ("implver %0" : "=r"(__implver)); \
186 (enum implver_enum) __implver; })
187 #else
188 /* Try to eliminate some dead code. */
189 #ifdef CONFIG_ALPHA_EV4
190 #define implver() IMPLVER_EV4
191 #endif
192 #ifdef CONFIG_ALPHA_EV5
193 #define implver() IMPLVER_EV5
194 #endif
195 #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
196 #define implver() IMPLVER_EV6
197 #endif
198 #endif
199
200 enum amask_enum {
201 AMASK_BWX = (1UL << 0),
202 AMASK_FIX = (1UL << 1),
203 AMASK_MAX = (1UL << 8),
204 AMASK_PRECISE_TRAP = (1UL << 9),
205 };
206
207 #define amask(mask) \
208 ({ unsigned long __amask, __input = (mask); \
209 __asm__ ("amask %1,%0" : "=r"(__amask) : "rI"(__input)); \
210 __amask; })
211
212 #define __CALL_PAL_R0(NAME, TYPE) \
213 static inline TYPE NAME(void) \
214 { \
215 register TYPE __r0 __asm__("$0"); \
216 __asm__ __volatile__( \
217 "call_pal %1 # " #NAME \
218 :"=r" (__r0) \
219 :"i" (PAL_ ## NAME) \
220 :"$1", "$16", "$22", "$23", "$24", "$25"); \
221 return __r0; \
222 }
223
224 #define __CALL_PAL_W1(NAME, TYPE0) \
225 static inline void NAME(TYPE0 arg0) \
226 { \
227 register TYPE0 __r16 __asm__("$16") = arg0; \
228 __asm__ __volatile__( \
229 "call_pal %1 # "#NAME \
230 : "=r"(__r16) \
231 : "i"(PAL_ ## NAME), "0"(__r16) \
232 : "$1", "$22", "$23", "$24", "$25"); \
233 }
234
235 #define __CALL_PAL_W2(NAME, TYPE0, TYPE1) \
236 static inline void NAME(TYPE0 arg0, TYPE1 arg1) \
237 { \
238 register TYPE0 __r16 __asm__("$16") = arg0; \
239 register TYPE1 __r17 __asm__("$17") = arg1; \
240 __asm__ __volatile__( \
241 "call_pal %2 # "#NAME \
242 : "=r"(__r16), "=r"(__r17) \
243 : "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
244 : "$1", "$22", "$23", "$24", "$25"); \
245 }
246
247 #define __CALL_PAL_RW1(NAME, RTYPE, TYPE0) \
248 static inline RTYPE NAME(TYPE0 arg0) \
249 { \
250 register RTYPE __r0 __asm__("$0"); \
251 register TYPE0 __r16 __asm__("$16") = arg0; \
252 __asm__ __volatile__( \
253 "call_pal %2 # "#NAME \
254 : "=r"(__r16), "=r"(__r0) \
255 : "i"(PAL_ ## NAME), "0"(__r16) \
256 : "$1", "$22", "$23", "$24", "$25"); \
257 return __r0; \
258 }
259
260 #define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1) \
261 static inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \
262 { \
263 register RTYPE __r0 __asm__("$0"); \
264 register TYPE0 __r16 __asm__("$16") = arg0; \
265 register TYPE1 __r17 __asm__("$17") = arg1; \
266 __asm__ __volatile__( \
267 "call_pal %3 # "#NAME \
268 : "=r"(__r16), "=r"(__r17), "=r"(__r0) \
269 : "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
270 : "$1", "$22", "$23", "$24", "$25"); \
271 return __r0; \
272 }
273
274 __CALL_PAL_W1(cflush, unsigned long);
275 __CALL_PAL_R0(rdmces, unsigned long);
276 __CALL_PAL_R0(rdps, unsigned long);
277 __CALL_PAL_R0(rdusp, unsigned long);
278 __CALL_PAL_RW1(swpipl, unsigned long, unsigned long);
279 __CALL_PAL_R0(whami, unsigned long);
280 __CALL_PAL_W2(wrent, void*, unsigned long);
281 __CALL_PAL_W1(wripir, unsigned long);
282 __CALL_PAL_W1(wrkgp, unsigned long);
283 __CALL_PAL_W1(wrmces, unsigned long);
284 __CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long);
285 __CALL_PAL_W1(wrusp, unsigned long);
286 __CALL_PAL_W1(wrvptptr, unsigned long);
287
288 #define IPL_MIN 0
289 #define IPL_SW0 1
290 #define IPL_SW1 2
291 #define IPL_DEV0 3
292 #define IPL_DEV1 4
293 #define IPL_TIMER 5
294 #define IPL_PERF 6
295 #define IPL_POWERFAIL 6
296 #define IPL_MCHECK 7
297 #define IPL_MAX 7
298
299 #ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
300 #undef IPL_MIN
301 #define IPL_MIN __min_ipl
302 extern int __min_ipl;
303 #endif
304
305 #define getipl() (rdps() & 7)
306 #define setipl(ipl) ((void) swpipl(ipl))
307
308 #define __cli() do { setipl(IPL_MAX); barrier(); } while(0)
309 #define __sti() do { barrier(); setipl(IPL_MIN); } while(0)
310 #define __save_flags(flags) ((flags) = rdps())
311 #define __save_and_cli(flags) do { (flags) = swpipl(IPL_MAX); barrier(); } while(0)
312 #define __restore_flags(flags) do { barrier(); setipl(flags); barrier(); } while(0)
313
314 #define local_irq_save(flags) __save_and_cli(flags)
315 #define local_irq_restore(flags) __restore_flags(flags)
316 #define local_irq_disable() __cli()
317 #define local_irq_enable() __sti()
318
319 #ifdef CONFIG_SMP
320
321 extern int global_irq_holder;
322
323 #define save_and_cli(flags) (save_flags(flags), cli())
324
325 extern void __global_cli(void);
326 extern void __global_sti(void);
327 extern unsigned long __global_save_flags(void);
328 extern void __global_restore_flags(unsigned long flags);
329
330 #define cli() __global_cli()
331 #define sti() __global_sti()
332 #define save_flags(flags) ((flags) = __global_save_flags())
333 #define restore_flags(flags) __global_restore_flags(flags)
334
335 #else /* CONFIG_SMP */
336
337 #define cli() __cli()
338 #define sti() __sti()
339 #define save_flags(flags) __save_flags(flags)
340 #define save_and_cli(flags) __save_and_cli(flags)
341 #define restore_flags(flags) __restore_flags(flags)
342
343 #endif /* CONFIG_SMP */
344
345 /*
346 * TB routines..
347 */
348 #define __tbi(nr,arg,arg1...) \
349 ({ \
350 register unsigned long __r16 __asm__("$16") = (nr); \
351 register unsigned long __r17 __asm__("$17"); arg; \
352 __asm__ __volatile__( \
353 "call_pal %3 #__tbi" \
354 :"=r" (__r16),"=r" (__r17) \
355 :"0" (__r16),"i" (PAL_tbi) ,##arg1 \
356 :"$0", "$1", "$22", "$23", "$24", "$25"); \
357 })
358
359 #define tbi(x,y) __tbi(x,__r17=(y),"1" (__r17))
360 #define tbisi(x) __tbi(1,__r17=(x),"1" (__r17))
361 #define tbisd(x) __tbi(2,__r17=(x),"1" (__r17))
362 #define tbis(x) __tbi(3,__r17=(x),"1" (__r17))
363 #define tbiap() __tbi(-1, /* no second argument */)
364 #define tbia() __tbi(-2, /* no second argument */)
365
366 /*
367 * Atomic exchange.
368 * Since it can be used to implement critical sections
369 * it must clobber "memory" (also for interrupts in UP).
370 */
371
372 extern __inline__ unsigned long
373 __xchg_u32(volatile int *m, unsigned long val)
374 {
375 unsigned long dummy;
376
377 __asm__ __volatile__(
378 "1: ldl_l %0,%4\n"
379 " bis $31,%3,%1\n"
380 " stl_c %1,%2\n"
381 " beq %1,2f\n"
382 #ifdef CONFIG_SMP
383 " mb\n"
384 #endif
385 ".subsection 2\n"
386 "2: br 1b\n"
387 ".previous"
388 : "=&r" (val), "=&r" (dummy), "=m" (*m)
389 : "rI" (val), "m" (*m) : "memory");
390
391 return val;
392 }
393
394 extern __inline__ unsigned long
395 __xchg_u64(volatile long *m, unsigned long val)
396 {
397 unsigned long dummy;
398
399 __asm__ __volatile__(
400 "1: ldq_l %0,%4\n"
401 " bis $31,%3,%1\n"
402 " stq_c %1,%2\n"
403 " beq %1,2f\n"
404 #ifdef CONFIG_SMP
405 " mb\n"
406 #endif
407 ".subsection 2\n"
408 "2: br 1b\n"
409 ".previous"
410 : "=&r" (val), "=&r" (dummy), "=m" (*m)
411 : "rI" (val), "m" (*m) : "memory");
412
413 return val;
414 }
415
416 /* This function doesn't exist, so you'll get a linker error
417 if something tries to do an invalid xchg(). */
418 extern void __xchg_called_with_bad_pointer(void);
419
420 static __inline__ unsigned long
421 __xchg(volatile void *ptr, unsigned long x, int size)
422 {
423 switch (size) {
424 case 4:
425 return __xchg_u32(ptr, x);
426 case 8:
427 return __xchg_u64(ptr, x);
428 }
429 __xchg_called_with_bad_pointer();
430 return x;
431 }
432
433 #define xchg(ptr,x) \
434 ({ \
435 __typeof__(*(ptr)) _x_ = (x); \
436 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
437 })
438
439 #define tas(ptr) (xchg((ptr),1))
440
441
442 /*
443 * Atomic compare and exchange. Compare OLD with MEM, if identical,
444 * store NEW in MEM. Return the initial value in MEM. Success is
445 * indicated by comparing RETURN with OLD.
446 *
447 * The memory barrier should be placed in SMP only when we actually
448 * make the change. If we don't change anything (so if the returned
449 * prev is equal to old) then we aren't acquiring anything new and
450 * we don't need any memory barrier as far I can tell.
451 */
452
453 #define __HAVE_ARCH_CMPXCHG 1
454
455 extern __inline__ unsigned long
456 __cmpxchg_u32(volatile int *m, int old, int new)
457 {
458 unsigned long prev, cmp;
459
460 __asm__ __volatile__(
461 "1: ldl_l %0,%5\n"
462 " cmpeq %0,%3,%1\n"
463 " beq %1,2f\n"
464 " mov %4,%1\n"
465 " stl_c %1,%2\n"
466 " beq %1,3f\n"
467 #ifdef CONFIG_SMP
468 " mb\n"
469 #endif
470 "2:\n"
471 ".subsection 2\n"
472 "3: br 1b\n"
473 ".previous"
474 : "=&r"(prev), "=&r"(cmp), "=m"(*m)
475 : "r"((long) old), "r"(new), "m"(*m) : "memory");
476
477 return prev;
478 }
479
480 extern __inline__ unsigned long
481 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
482 {
483 unsigned long prev, cmp;
484
485 __asm__ __volatile__(
486 "1: ldq_l %0,%5\n"
487 " cmpeq %0,%3,%1\n"
488 " beq %1,2f\n"
489 " mov %4,%1\n"
490 " stq_c %1,%2\n"
491 " beq %1,3f\n"
492 #ifdef CONFIG_SMP
493 " mb\n"
494 #endif
495 "2:\n"
496 ".subsection 2\n"
497 "3: br 1b\n"
498 ".previous"
499 : "=&r"(prev), "=&r"(cmp), "=m"(*m)
500 : "r"((long) old), "r"(new), "m"(*m) : "memory");
501
502 return prev;
503 }
504
505 /* This function doesn't exist, so you'll get a linker error
506 if something tries to do an invalid cmpxchg(). */
507 extern void __cmpxchg_called_with_bad_pointer(void);
508
509 static __inline__ unsigned long
510 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
511 {
512 switch (size) {
513 case 4:
514 return __cmpxchg_u32(ptr, old, new);
515 case 8:
516 return __cmpxchg_u64(ptr, old, new);
517 }
518 __cmpxchg_called_with_bad_pointer();
519 return old;
520 }
521
522 #define cmpxchg(ptr,o,n) \
523 ({ \
524 __typeof__(*(ptr)) _o_ = (o); \
525 __typeof__(*(ptr)) _n_ = (n); \
526 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
527 (unsigned long)_n_, sizeof(*(ptr))); \
528 })
529
530 #endif /* __ASSEMBLY__ */
531
532 #endif
533