File: /usr/src/linux/include/asm-arm/arch-sa1100/SA-1100.h
1 /*
2 * FILE SA-1100.h
3 *
4 * Version 1.2
5 * Author Copyright (c) Marc A. Viredaz, 1998
6 * DEC Western Research Laboratory, Palo Alto, CA
7 * Date January 1998 (April 1997)
8 * System StrongARM SA-1100
9 * Language C or ARM Assembly
10 * Purpose Definition of constants related to the StrongARM
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
12 * architecture version 4). This file is based on the
13 * StrongARM SA-1100 data sheet version 2.2.
14 *
15 * Language-specific definitions are selected by the
16 * macro "LANGUAGE", which should be defined as either
17 * "C" (default) or "Assembly".
18 */
19
20
21 /* Be sure that virtual mapping is defined right */
22 #ifndef __ASM_ARCH_HARDWARE_H
23 #error You must include hardware.h not SA-1100.h
24 #endif
25
26
27 #ifndef LANGUAGE
28 # ifdef __ASSEMBLY__
29 # define LANGUAGE Assembly
30 # else
31 # define LANGUAGE C
32 # endif
33 #endif
34
35 #ifndef io_p2v
36 #define io_p2v(PhAdd) (PhAdd)
37 #endif
38
39 #include <asm/arch/bitfield.h>
40
41 #define C 0
42 #define Assembly 1
43
44
45 #if LANGUAGE == C
46 typedef unsigned short Word16 ;
47 typedef unsigned int Word32 ;
48 typedef Word32 Word ;
49 typedef Word Quad [4] ;
50 typedef void *Address ;
51 typedef void (*ExcpHndlr) (void) ;
52 #endif /* LANGUAGE == C */
53
54
55 /*
56 * Memory
57 */
58
59 #define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */
60
61 #define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */
62 #define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */
63 /* [byte] */
64 #define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
65 /* [byte] */
66 #define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */
67 /* [byte] */
68 #define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */
69 /* [byte] */
70
71 #define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */
72 #define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */
73 #define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
74 #define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */
75 #define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */
76
77 #define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */
78
79 #define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \
80 (0x00000000 + (Nb)*StMemBnkSp)
81 #define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */
82 #define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
83 #define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */
84 #define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */
85
86 #if LANGUAGE == C
87 typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
88 #define StMemBnk /* Static Memory Bank [0..3] */ \
89 ((StMemBnkType *) io_p2v (_StMemBnk (0)))
90 #define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */
91 #define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
92 #define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */
93 #define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */
94 #endif /* LANGUAGE == C */
95
96 #define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \
97 (0xC0000000 + (Nb)*DRAMBnkSp)
98 #define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */
99 #define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
100 #define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */
101 #define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */
102
103 #if LANGUAGE == C
104 typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
105 #define DRAMBnk /* DRAM Bank [0..3] */ \
106 ((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
107 #define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */
108 #define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
109 #define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */
110 #define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */
111 #endif /* LANGUAGE == C */
112
113 #define _ZeroMem 0xE0000000 /* Zero Memory bank */
114
115 #if LANGUAGE == C
116 typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
117 #define ZeroMem /* Zero Memory bank */ \
118 (*((ZeroMemType *) io_p2v (_ZeroMem)))
119 #endif /* LANGUAGE == C */
120
121
122 /*
123 * Personal Computer Memory Card International Association (PCMCIA) sockets
124 */
125
126 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
127 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
128 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
129 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
130 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
131
132 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
133 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
134 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
135 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
136
137 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
138 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
139 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
140 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
141
142 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
143 (0x20000000 + (Nb)*PCMCIASp)
144 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
145 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
146 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
147 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
148 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
149
150 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
151 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
152 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
153 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
154
155 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
156 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
157 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
158 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
159
160 #if LANGUAGE == C
161
162 typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
163 typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
164
165 #define PCMCIA0 /* PCMCIA 0 */ \
166 (*((PCMCIAType *) io_p2v (_PCMCIA0)))
167 #define PCMCIA0IO /* PCMCIA 0 I/O */ \
168 (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
169 #define PCMCIA0Attr /* PCMCIA 0 Attribute */ \
170 (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
171 #define PCMCIA0Mem /* PCMCIA 0 Memory */ \
172 (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
173
174 #define PCMCIA1 /* PCMCIA 1 */ \
175 (*((PCMCIAType *) io_p2v (_PCMCIA1)))
176 #define PCMCIA1IO /* PCMCIA 1 I/O */ \
177 (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
178 #define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
179 (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
180 #define PCMCIA1Mem /* PCMCIA 1 Memory */ \
181 (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
182
183 #endif /* LANGUAGE == C */
184
185
186 /*
187 * Universal Serial Bus (USB) Device Controller (UDC) control registers
188 *
189 * Registers
190 * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
191 * Controller (UDC) Control Register (read/write).
192 * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
193 * Controller (UDC) Address Register (read/write).
194 * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
195 * Controller (UDC) Output Maximum Packet size register
196 * (read/write).
197 * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
198 * Controller (UDC) Input Maximum Packet size register
199 * (read/write).
200 * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
201 * Controller (UDC) Control/Status register end-point 0
202 * (read/write).
203 * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
204 * Controller (UDC) Control/Status register end-point 1
205 * (output, read/write).
206 * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
207 * Controller (UDC) Control/Status register end-point 2
208 * (input, read/write).
209 * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
210 * Controller (UDC) Data register end-point 0
211 * (read/write).
212 * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
213 * Controller (UDC) Write Count register end-point 0
214 * (read).
215 * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
216 * Controller (UDC) Data Register (read/write).
217 * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
218 * Controller (UDC) Status Register (read/write).
219 */
220
221 #define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */
222 #define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */
223 #define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */
224 /* Packet size reg. */
225 #define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */
226 /* Packet size reg. */
227 #define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */
228 /* reg. end-point 0 */
229 #define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */
230 /* reg. end-point 1 (output) */
231 #define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */
232 /* reg. end-point 2 (input) */
233 #define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */
234 /* end-point 0 */
235 #define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */
236 /* reg. end-point 0 */
237 #define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */
238 #define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */
239
240 #if LANGUAGE == C
241 #define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \
242 (*((volatile Word *) io_p2v (_Ser0UDCCR)))
243 #define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
244 (*((volatile Word *) io_p2v (_Ser0UDCAR)))
245 #define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \
246 /* Packet size reg. */ \
247 (*((volatile Word *) io_p2v (_Ser0UDCOMP)))
248 #define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \
249 /* Packet size reg. */ \
250 (*((volatile Word *) io_p2v (_Ser0UDCIMP)))
251 #define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \
252 /* reg. end-point 0 */ \
253 (*((volatile Word *) io_p2v (_Ser0UDCCS0)))
254 #define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \
255 /* reg. end-point 1 (output) */ \
256 (*((volatile Word *) io_p2v (_Ser0UDCCS1)))
257 #define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \
258 /* reg. end-point 2 (input) */ \
259 (*((volatile Word *) io_p2v (_Ser0UDCCS2)))
260 #define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \
261 /* end-point 0 */ \
262 (*((volatile Word *) io_p2v (_Ser0UDCD0)))
263 #define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \
264 /* reg. end-point 0 */ \
265 (*((volatile Word *) io_p2v (_Ser0UDCWC)))
266 #define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \
267 (*((volatile Word *) io_p2v (_Ser0UDCDR)))
268 #define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \
269 (*((volatile Word *) io_p2v (_Ser0UDCSR)))
270 #endif /* LANGUAGE == C */
271
272 #define UDCCR_UDD 0x00000001 /* UDC Disable */
273 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
274 #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
275 #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
276 /* (disable) */
277 #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
278 /* (disable) */
279 #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
280 /* (disable) */
281 #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
282 /* (disable) */
283 #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
284 #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
285
286 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
287
288 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
289 /* [byte] */
290 #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
291 /* [1..256 byte] */ \
292 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
293
294 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
295 /* [byte] */
296 #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
297 /* [1..256 byte] */ \
298 (((Size) - 1) << FShft (UDCIMP_INMAXP))
299
300 #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
301 #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
302 #define UDCCS0_SST 0x00000004 /* Sent STall */
303 #define UDCCS0_FST 0x00000008 /* Force STall */
304 #define UDCCS0_DE 0x00000010 /* Data End */
305 #define UDCCS0_SE 0x00000020 /* Setup End (read) */
306 #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
307 /* (write) */
308 #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
309
310 #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
311 /* Service request (read) */
312 #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
313 #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
314 #define UDCCS1_SST 0x00000008 /* Sent STall */
315 #define UDCCS1_FST 0x00000010 /* Force STall */
316 #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
317
318 #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
319 /* Service request (read) */
320 #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
321 #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
322 #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
323 #define UDCCS2_SST 0x00000010 /* Sent STall */
324 #define UDCCS2_FST 0x00000020 /* Force STall */
325
326 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
327
328 #define UDCWC_WC Fld (4, 0) /* Write Count */
329
330 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
331
332 #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
333 #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
334 #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
335 #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
336 #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
337 #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
338
339
340 /*
341 * Universal Asynchronous Receiver/Transmitter (UART) control registers
342 *
343 * Registers
344 * Ser1UTCR0 Serial port 1 Universal Asynchronous
345 * Receiver/Transmitter (UART) Control Register 0
346 * (read/write).
347 * Ser1UTCR1 Serial port 1 Universal Asynchronous
348 * Receiver/Transmitter (UART) Control Register 1
349 * (read/write).
350 * Ser1UTCR2 Serial port 1 Universal Asynchronous
351 * Receiver/Transmitter (UART) Control Register 2
352 * (read/write).
353 * Ser1UTCR3 Serial port 1 Universal Asynchronous
354 * Receiver/Transmitter (UART) Control Register 3
355 * (read/write).
356 * Ser1UTDR Serial port 1 Universal Asynchronous
357 * Receiver/Transmitter (UART) Data Register
358 * (read/write).
359 * Ser1UTSR0 Serial port 1 Universal Asynchronous
360 * Receiver/Transmitter (UART) Status Register 0
361 * (read/write).
362 * Ser1UTSR1 Serial port 1 Universal Asynchronous
363 * Receiver/Transmitter (UART) Status Register 1 (read).
364 *
365 * Ser2UTCR0 Serial port 2 Universal Asynchronous
366 * Receiver/Transmitter (UART) Control Register 0
367 * (read/write).
368 * Ser2UTCR1 Serial port 2 Universal Asynchronous
369 * Receiver/Transmitter (UART) Control Register 1
370 * (read/write).
371 * Ser2UTCR2 Serial port 2 Universal Asynchronous
372 * Receiver/Transmitter (UART) Control Register 2
373 * (read/write).
374 * Ser2UTCR3 Serial port 2 Universal Asynchronous
375 * Receiver/Transmitter (UART) Control Register 3
376 * (read/write).
377 * Ser2UTCR4 Serial port 2 Universal Asynchronous
378 * Receiver/Transmitter (UART) Control Register 4
379 * (read/write).
380 * Ser2UTDR Serial port 2 Universal Asynchronous
381 * Receiver/Transmitter (UART) Data Register
382 * (read/write).
383 * Ser2UTSR0 Serial port 2 Universal Asynchronous
384 * Receiver/Transmitter (UART) Status Register 0
385 * (read/write).
386 * Ser2UTSR1 Serial port 2 Universal Asynchronous
387 * Receiver/Transmitter (UART) Status Register 1 (read).
388 *
389 * Ser3UTCR0 Serial port 3 Universal Asynchronous
390 * Receiver/Transmitter (UART) Control Register 0
391 * (read/write).
392 * Ser3UTCR1 Serial port 3 Universal Asynchronous
393 * Receiver/Transmitter (UART) Control Register 1
394 * (read/write).
395 * Ser3UTCR2 Serial port 3 Universal Asynchronous
396 * Receiver/Transmitter (UART) Control Register 2
397 * (read/write).
398 * Ser3UTCR3 Serial port 3 Universal Asynchronous
399 * Receiver/Transmitter (UART) Control Register 3
400 * (read/write).
401 * Ser3UTDR Serial port 3 Universal Asynchronous
402 * Receiver/Transmitter (UART) Data Register
403 * (read/write).
404 * Ser3UTSR0 Serial port 3 Universal Asynchronous
405 * Receiver/Transmitter (UART) Status Register 0
406 * (read/write).
407 * Ser3UTSR1 Serial port 3 Universal Asynchronous
408 * Receiver/Transmitter (UART) Status Register 1 (read).
409 *
410 * Clocks
411 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
412 * or 3.5795 MHz).
413 * fua, Tua Frequency, period of the UART communication.
414 */
415
416 #define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
417 (0x80010000 + ((Nb) - 1)*0x00020000)
418 #define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
419 (0x80010004 + ((Nb) - 1)*0x00020000)
420 #define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
421 (0x80010008 + ((Nb) - 1)*0x00020000)
422 #define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
423 (0x8001000C + ((Nb) - 1)*0x00020000)
424 #define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \
425 (0x80010010 + ((Nb) - 1)*0x00020000)
426 #define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
427 (0x80010014 + ((Nb) - 1)*0x00020000)
428 #define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
429 (0x8001001C + ((Nb) - 1)*0x00020000)
430 #define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
431 (0x80010020 + ((Nb) - 1)*0x00020000)
432
433 #define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
434 #define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
435 #define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
436 #define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
437 #define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
438 #define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
439 #define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
440
441 #define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
442 #define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
443 #define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
444 #define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
445 #define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
446 #define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
447 #define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
448 #define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
449
450 #define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
451 #define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
452 #define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
453 #define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
454 #define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
455 #define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
456 #define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
457
458 /*
459 * Register offsets
460 */
461 #define UTCR0 0x00
462 #define UTCR1 0x04
463 #define UTCR2 0x08
464 #define UTCR3 0x0c
465 #define UTDR 0x14
466 #define UTSR0 0x1c
467 #define UTSR1 0x20
468
469 #if LANGUAGE == C
470
471 #define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
472 (*((volatile Word *) io_p2v (_Ser1UTCR0)))
473 #define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
474 (*((volatile Word *) io_p2v (_Ser1UTCR1)))
475 #define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
476 (*((volatile Word *) io_p2v (_Ser1UTCR2)))
477 #define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
478 (*((volatile Word *) io_p2v (_Ser1UTCR3)))
479 #define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
480 (*((volatile Word *) io_p2v (_Ser1UTDR)))
481 #define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
482 (*((volatile Word *) io_p2v (_Ser1UTSR0)))
483 #define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
484 (*((volatile Word *) io_p2v (_Ser1UTSR1)))
485
486 #define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \
487 (*((volatile Word *) io_p2v (_Ser2UTCR0)))
488 #define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
489 (*((volatile Word *) io_p2v (_Ser2UTCR1)))
490 #define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \
491 (*((volatile Word *) io_p2v (_Ser2UTCR2)))
492 #define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \
493 (*((volatile Word *) io_p2v (_Ser2UTCR3)))
494 #define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \
495 (*((volatile Word *) io_p2v (_Ser2UTCR4)))
496 #define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \
497 (*((volatile Word *) io_p2v (_Ser2UTDR)))
498 #define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \
499 (*((volatile Word *) io_p2v (_Ser2UTSR0)))
500 #define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
501 (*((volatile Word *) io_p2v (_Ser2UTSR1)))
502
503 #define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \
504 (*((volatile Word *) io_p2v (_Ser3UTCR0)))
505 #define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
506 (*((volatile Word *) io_p2v (_Ser3UTCR1)))
507 #define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \
508 (*((volatile Word *) io_p2v (_Ser3UTCR2)))
509 #define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \
510 (*((volatile Word *) io_p2v (_Ser3UTCR3)))
511 #define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \
512 (*((volatile Word *) io_p2v (_Ser3UTDR)))
513 #define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \
514 (*((volatile Word *) io_p2v (_Ser3UTSR0)))
515 #define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
516 (*((volatile Word *) io_p2v (_Ser3UTSR1)))
517
518 #elif LANGUAGE == Assembly
519 #define Ser1UTCR0 ( io_p2v (_Ser1UTCR0))
520 #define Ser1UTCR1 ( io_p2v (_Ser1UTCR1))
521 #define Ser1UTCR2 ( io_p2v (_Ser1UTCR2))
522 #define Ser1UTCR3 ( io_p2v (_Ser1UTCR3))
523 #define Ser1UTDR ( io_p2v (_Ser1UTDR))
524 #define Ser1UTSR0 ( io_p2v (_Ser1UTSR0))
525 #define Ser1UTSR1 ( io_p2v (_Ser1UTSR1))
526
527 #define Ser2UTCR0 ( io_p2v (_Ser2UTCR0))
528 #define Ser2UTCR1 ( io_p2v (_Ser2UTCR1))
529 #define Ser2UTCR2 ( io_p2v (_Ser2UTCR2))
530 #define Ser2UTCR3 ( io_p2v (_Ser2UTCR3))
531 #define Ser2UTCR4 ( io_p2v (_Ser2UTCR4))
532 #define Ser2UTDR ( io_p2v (_Ser2UTDR))
533 #define Ser2UTSR0 ( io_p2v (_Ser2UTSR0))
534 #define Ser2UTSR1 ( io_p2v (_Ser2UTSR1))
535
536 #define Ser3UTCR0 ( io_p2v (_Ser3UTCR0))
537 #define Ser3UTCR1 ( io_p2v (_Ser3UTCR1))
538 #define Ser3UTCR2 ( io_p2v (_Ser3UTCR2))
539 #define Ser3UTCR3 ( io_p2v (_Ser3UTCR3))
540 #define Ser3UTDR ( io_p2v (_Ser3UTDR))
541 #define Ser3UTSR0 ( io_p2v (_Ser3UTSR0))
542 #define Ser3UTSR1 ( io_p2v (_Ser3UTSR1))
543
544 #endif /* LANGUAGE == C */
545
546 #define UTCR0_PE 0x00000001 /* Parity Enable */
547 #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
548 #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
549 #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
550 #define UTCR0_SBS 0x00000004 /* Stop Bit Select */
551 #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
552 #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
553 #define UTCR0_DSS 0x00000008 /* Data Size Select */
554 #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
555 #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
556 #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
557 /* (ser. port 1: GPIO [18], */
558 /* ser. port 3: GPIO [20]) */
559 #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
560 #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
561 #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
562 #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
563 #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
564 #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
565 #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
566 (UTCR0_1StpBit + UTCR0_8BitData)
567
568 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
569 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
570 /* fua = fxtl/(16*(BRD[11:0] + 1)) */
571 /* Tua = 16*(BRD [11:0] + 1)*Txtl */
572 #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
573 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
574 FShft (UTCR1_BRD))
575 #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
576 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
577 FShft (UTCR2_BRD))
578 /* fua = fxtl/(16*Floor (Div/16)) */
579 /* Tua = 16*Floor (Div/16)*Txtl */
580 #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
581 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
582 FShft (UTCR1_BRD))
583 #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
584 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
585 FShft (UTCR2_BRD))
586 /* fua = fxtl/(16*Ceil (Div/16)) */
587 /* Tua = 16*Ceil (Div/16)*Txtl */
588
589 #define UTCR3_RXE 0x00000001 /* Receive Enable */
590 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
591 #define UTCR3_BRK 0x00000004 /* BReaK mode */
592 #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
593 /* more Interrupt Enable */
594 #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
595 /* Interrupt Enable */
596 #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
597 #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
598 /* TIE, LBM can be set or cleared) */ \
599 (UTCR3_RXE + UTCR3_TXE)
600
601 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
602 /* (HP-SIR) modulation Enable */
603 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
604 #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
605 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
606 #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
607 #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
608
609 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
610 #if 0 /* Hidden receive FIFO bits */
611 #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
612 #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
613 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
614 #endif /* 0 */
615
616 #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
617 /* Service request (read) */
618 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
619 /* more Service request (read) */
620 #define UTSR0_RID 0x00000004 /* Receiver IDle */
621 #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
622 #define UTSR0_REB 0x00000010 /* Receive End of Break */
623 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
624
625 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
626 #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
627 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
628 #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
629 #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
630 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
631
632
633 /*
634 * Synchronous Data Link Controller (SDLC) control registers
635 *
636 * Registers
637 * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
638 * Control Register 0 (read/write).
639 * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
640 * Control Register 1 (read/write).
641 * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
642 * Control Register 2 (read/write).
643 * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
644 * Control Register 3 (read/write).
645 * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
646 * Control Register 4 (read/write).
647 * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
648 * Data Register (read/write).
649 * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
650 * Status Register 0 (read/write).
651 * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
652 * Status Register 1 (read/write).
653 *
654 * Clocks
655 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
656 * or 3.5795 MHz).
657 * fsd, Tsd Frequency, period of the SDLC communication.
658 */
659
660 #define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */
661 #define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */
662 #define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */
663 #define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */
664 #define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */
665 #define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
666 #define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */
667 #define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */
668
669 #if LANGUAGE == C
670 #define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
671 (*((volatile Word *) io_p2v (_Ser1SDCR0)))
672 #define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
673 (*((volatile Word *) io_p2v (_Ser1SDCR1)))
674 #define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
675 (*((volatile Word *) io_p2v (_Ser1SDCR2)))
676 #define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
677 (*((volatile Word *) io_p2v (_Ser1SDCR3)))
678 #define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
679 (*((volatile Word *) io_p2v (_Ser1SDCR4)))
680 #define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
681 (*((volatile Word *) io_p2v (_Ser1SDDR)))
682 #define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
683 (*((volatile Word *) io_p2v (_Ser1SDSR0)))
684 #define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
685 (*((volatile Word *) io_p2v (_Ser1SDSR1)))
686 #endif /* LANGUAGE == C */
687
688 #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
689 #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
690 #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
691 #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
692 #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
693 #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
694 #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
695 #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
696 #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
697 #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
698 #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
699 #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
700 /* (GPIO [16]) */
701 #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
702 #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
703 #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
704 #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
705 #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
706 #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
707 #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
708 #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
709
710 #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
711 /* (GPIO [17]) */
712 #define SDCR1_TXE 0x00000002 /* Transmit Enable */
713 #define SDCR1_RXE 0x00000004 /* Receive Enable */
714 #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
715 /* more Interrupt Enable */
716 #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
717 /* Interrupt Enable */
718 #define SDCR1_AME 0x00000020 /* Address Match Enable */
719 #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
720 #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
721 #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
722 #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
723
724 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
725
726 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
727 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
728 /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
729 /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
730 #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
731 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
732 FShft (SDCR3_BRD))
733 #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
734 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
735 FShft (SDCR4_BRD))
736 /* fsd = fxtl/(16*Floor (Div/16)) */
737 /* Tsd = 16*Floor (Div/16)*Txtl */
738 #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
739 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
740 FShft (SDCR3_BRD))
741 #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
742 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
743 FShft (SDCR4_BRD))
744 /* fsd = fxtl/(16*Ceil (Div/16)) */
745 /* Tsd = 16*Ceil (Div/16)*Txtl */
746
747 #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
748 #if 0 /* Hidden receive FIFO bits */
749 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
750 #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
751 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
752 #endif /* 0 */
753
754 #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
755 #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
756 #define SDSR0_RAB 0x00000004 /* Receive ABort */
757 #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
758 /* Service request (read) */
759 #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
760 /* more Service request (read) */
761
762 #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
763 #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
764 #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
765 #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
766 #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
767 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
768 #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
769 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
770
771
772 /*
773 * High-Speed Serial to Parallel controller (HSSP) control registers
774 *
775 * Registers
776 * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
777 * controller (HSSP) Control Register 0 (read/write).
778 * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
779 * controller (HSSP) Control Register 1 (read/write).
780 * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
781 * controller (HSSP) Data Register (read/write).
782 * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
783 * controller (HSSP) Status Register 0 (read/write).
784 * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
785 * controller (HSSP) Status Register 1 (read).
786 * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
787 * controller (HSSP) Control Register 2 (read/write).
788 * [The HSCR2 register is only implemented in
789 * versions 2.0 (rev. = 8) and higher of the StrongARM
790 * SA-1100.]
791 */
792
793 #define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */
794 #define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */
795 #define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */
796 #define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */
797 #define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */
798 #define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */
799
800 #if LANGUAGE == C
801 #define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \
802 (*((volatile Word *) io_p2v (_Ser2HSCR0)))
803 #define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
804 (*((volatile Word *) io_p2v (_Ser2HSCR1)))
805 #define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \
806 (*((volatile Word *) io_p2v (_Ser2HSDR)))
807 #define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \
808 (*((volatile Word *) io_p2v (_Ser2HSSR0)))
809 #define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
810 (*((volatile Word *) io_p2v (_Ser2HSSR1)))
811 #define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \
812 (*((volatile Word *) io_p2v (_Ser2HSCR2)))
813 #endif /* LANGUAGE == C */
814
815 #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
816 #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
817 #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
818 #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
819 #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
820 #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
821 #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
822 #define HSCR0_TXE 0x00000008 /* Transmit Enable */
823 #define HSCR0_RXE 0x00000010 /* Receive Enable */
824 #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
825 /* more Interrupt Enable */
826 #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
827 /* Interrupt Enable */
828 #define HSCR0_AME 0x00000080 /* Address Match Enable */
829
830 #define HSCR1_AMV Fld (8, 0) /* Address Match Value */
831
832 #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
833 #if 0 /* Hidden receive FIFO bits */
834 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
835 #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
836 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
837 #endif /* 0 */
838
839 #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
840 #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
841 #define HSSR0_RAB 0x00000004 /* Receive ABort */
842 #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
843 /* Service request (read) */
844 #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
845 /* more Service request (read) */
846 #define HSSR0_FRE 0x00000020 /* receive FRaming Error */
847
848 #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
849 #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
850 #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
851 #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
852 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
853 #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
854 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
855
856 #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
857 #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
858 /* (inverted) */
859 #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
860 /* (non-inverted) */
861 #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
862 #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
863 /* (inverted) */
864 #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
865 /* (non-inverted) */
866
867
868 /*
869 * Multi-media Communications Port (MCP) control registers
870 *
871 * Registers
872 * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
873 * Control Register 0 (read/write).
874 * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
875 * Data Register 0 (audio, read/write).
876 * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
877 * Data Register 1 (telecom, read/write).
878 * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
879 * Data Register 2 (CODEC registers, read/write).
880 * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
881 * Status Register (read/write).
882 * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
883 * Control Register 1 (read/write).
884 * [The MCCR1 register is only implemented in
885 * versions 2.0 (rev. = 8) and higher of the StrongARM
886 * SA-1100.]
887 *
888 * Clocks
889 * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
890 * 12 MHz, or GPIO [21]).
891 * faud, Taud Frequency, period of the audio sampling.
892 * ftcm, Ttcm Frequency, period of the telecom sampling.
893 */
894
895 #define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */
896 #define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */
897 /* (audio) */
898 #define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
899 /* (telecom) */
900 #define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */
901 /* (CODEC reg.) */
902 #define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */
903 #define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */
904
905 #if LANGUAGE == C
906 #define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \
907 (*((volatile Word *) io_p2v (_Ser4MCCR0)))
908 #define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \
909 /* (audio) */ \
910 (*((volatile Word *) io_p2v (_Ser4MCDR0)))
911 #define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
912 /* (telecom) */ \
913 (*((volatile Word *) io_p2v (_Ser4MCDR1)))
914 #define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \
915 /* (CODEC reg.) */ \
916 (*((volatile Word *) io_p2v (_Ser4MCDR2)))
917 #define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \
918 (*((volatile Word *) io_p2v (_Ser4MCSR)))
919 #define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
920 (*((volatile Word *) io_p2v (_Ser4MCCR1)))
921 #endif /* LANGUAGE == C */
922
923 #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
924 /* [6..127] */
925 /* faud = fmc/(32*ASD) */
926 /* Taud = 32*ASD*Tmc */
927 #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
928 /* [192..4064] */ \
929 ((Div)/32 << FShft (MCCR0_ASD))
930 /* faud = fmc/(32*Floor (Div/32)) */
931 /* Taud = 32*Floor (Div/32)*Tmc */
932 #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
933 (((Div) + 31)/32 << FShft (MCCR0_ASD))
934 /* faud = fmc/(32*Ceil (Div/32)) */
935 /* Taud = 32*Ceil (Div/32)*Tmc */
936 #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
937 /* Divisor/32 [16..127] */
938 /* ftcm = fmc/(32*TSD) */
939 /* Ttcm = 32*TSD*Tmc */
940 #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
941 /* [512..4064] */ \
942 ((Div)/32 << FShft (MCCR0_TSD))
943 /* ftcm = fmc/(32*Floor (Div/32)) */
944 /* Ttcm = 32*Floor (Div/32)*Tmc */
945 #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
946 (((Div) + 31)/32 << FShft (MCCR0_TSD))
947 /* ftcm = fmc/(32*Ceil (Div/32)) */
948 /* Ttcm = 32*Ceil (Div/32)*Tmc */
949 #define MCCR0_MCE 0x00010000 /* MCP Enable */
950 #define MCCR0_ECS 0x00020000 /* External Clock Select */
951 #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
952 #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
953 #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
954 /* sampling/storing Mode */
955 #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
956 #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
957 #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
958 /* or less interrupt Enable */
959 #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
960 /* or more interrupt Enable */
961 #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
962 /* or less interrupt Enable */
963 #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
964 /* more interrupt Enable */
965 #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
966 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
967 #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
968 (((Div) - 1) << FShft (MCCR0_ECP))
969
970 #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
971 /* FIFOs */
972
973 #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
974 /* FIFOs */
975
976 /* receive/transmit CODEC reg. */
977 /* FIFOs: */
978 #define MCDR2_DATA Fld (16, 0) /* reg. DATA */
979 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
980 #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
981 #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
982 #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
983
984 #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
985 /* or less Service request (read) */
986 #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
987 /* more Service request (read) */
988 #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
989 /* or less Service request (read) */
990 #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
991 /* or more Service request (read) */
992 #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
993 #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
994 #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
995 #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
996 #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
997 /* (read) */
998 #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
999 /* (read) */
1000 #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
1001 /* (read) */
1002 #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
1003 /* (read) */
1004 #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
1005 /* (read) */
1006 #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
1007 /* (read) */
1008 #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
1009 #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
1010
1011 #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
1012 #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
1013 /* (11.981 MHz) */
1014 #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
1015 /* (9.585 MHz) */
1016
1017
1018 /*
1019 * Synchronous Serial Port (SSP) control registers
1020 *
1021 * Registers
1022 * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
1023 * Register 0 (read/write).
1024 * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
1025 * Register 1 (read/write).
1026 * [Bits SPO and SP are only implemented in versions 2.0
1027 * (rev. = 8) and higher of the StrongARM SA-1100.]
1028 * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
1029 * Register (read/write).
1030 * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
1031 * Register (read/write).
1032 *
1033 * Clocks
1034 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
1035 * or 3.5795 MHz).
1036 * fss, Tss Frequency, period of the SSP communication.
1037 */
1038
1039 #define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */
1040 #define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */
1041 #define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */
1042 #define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */
1043
1044 #if LANGUAGE == C
1045 #define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \
1046 (*((volatile Word *) io_p2v (_Ser4SSCR0)))
1047 #define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
1048 (*((volatile Word *) io_p2v (_Ser4SSCR1)))
1049 #define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \
1050 (*((volatile Word *) io_p2v (_Ser4SSDR)))
1051 #define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \
1052 (*((volatile Word *) io_p2v (_Ser4SSSR)))
1053 #endif /* LANGUAGE == C */
1054
1055 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
1056 #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
1057 (((Size) - 1) << FShft (SSCR0_DSS))
1058 #define SSCR0_FRF Fld (2, 4) /* FRame Format */
1059 #define SSCR0_Motorola /* Motorola Serial Peripheral */ \
1060 /* Interface (SPI) format */ \
1061 (0 << FShft (SSCR0_FRF))
1062 #define SSCR0_TI /* Texas Instruments Synchronous */ \
1063 /* Serial format */ \
1064 (1 << FShft (SSCR0_FRF))
1065 #define SSCR0_National /* National Microwire format */ \
1066 (2 << FShft (SSCR0_FRF))
1067 #define SSCR0_SSE 0x00000080 /* SSP Enable */
1068 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
1069 /* fss = fxtl/(2*(SCR + 1)) */
1070 /* Tss = 2*(SCR + 1)*Txtl */
1071 #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
1072 (((Div) - 2)/2 << FShft (SSCR0_SCR))
1073 /* fss = fxtl/(2*Floor (Div/2)) */
1074 /* Tss = 2*Floor (Div/2)*Txtl */
1075 #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
1076 (((Div) - 1)/2 << FShft (SSCR0_SCR))
1077 /* fss = fxtl/(2*Ceil (Div/2)) */
1078 /* Tss = 2*Ceil (Div/2)*Txtl */
1079
1080 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
1081 /* Interrupt Enable */
1082 #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
1083 /* Interrupt Enable */
1084 #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
1085 #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
1086 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
1087 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
1088 #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
1089 #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
1090 /* after frame (SFRM, 1st edge) */
1091 #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
1092 /* after frame (SFRM, 1st edge) */
1093 #define SSCR1_ECS 0x00000020 /* External Clock Select */
1094 #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
1095 #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
1096
1097 #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
1098
1099 #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
1100 #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
1101 #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
1102 #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
1103 /* Service request (read) */
1104 #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
1105 /* Service request (read) */
1106 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
1107
1108
1109 /*
1110 * Operating System (OS) timer control registers
1111 *
1112 * Registers
1113 * OSMR0 Operating System (OS) timer Match Register 0
1114 * (read/write).
1115 * OSMR1 Operating System (OS) timer Match Register 1
1116 * (read/write).
1117 * OSMR2 Operating System (OS) timer Match Register 2
1118 * (read/write).
1119 * OSMR3 Operating System (OS) timer Match Register 3
1120 * (read/write).
1121 * OSCR Operating System (OS) timer Counter Register
1122 * (read/write).
1123 * OSSR Operating System (OS) timer Status Register
1124 * (read/write).
1125 * OWER Operating System (OS) timer Watch-dog Enable Register
1126 * (read/write).
1127 * OIER Operating System (OS) timer Interrupt Enable Register
1128 * (read/write).
1129 */
1130
1131 #define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \
1132 (0x90000000 + (Nb)*4)
1133 #define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */
1134 #define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
1135 #define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */
1136 #define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */
1137 #define _OSCR 0x90000010 /* OS timer Counter Reg. */
1138 #define _OSSR 0x90000014 /* OS timer Status Reg. */
1139 #define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
1140 #define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */
1141
1142 #if LANGUAGE == C
1143 #define OSMR /* OS timer Match Reg. [0..3] */ \
1144 ((volatile Word *) io_p2v (_OSMR (0)))
1145 #define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */
1146 #define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
1147 #define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */
1148 #define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */
1149 #define OSCR /* OS timer Counter Reg. */ \
1150 (*((volatile Word *) io_p2v (_OSCR)))
1151 #define OSSR /* OS timer Status Reg. */ \
1152 (*((volatile Word *) io_p2v (_OSSR)))
1153 #define OWER /* OS timer Watch-dog Enable Reg. */ \
1154 (*((volatile Word *) io_p2v (_OWER)))
1155 #define OIER /* OS timer Interrupt Enable Reg. */ \
1156 (*((volatile Word *) io_p2v (_OIER)))
1157 #endif /* LANGUAGE == C */
1158
1159 #define OSSR_M(Nb) /* Match detected [0..3] */ \
1160 (0x00000001 << (Nb))
1161 #define OSSR_M0 OSSR_M (0) /* Match detected 0 */
1162 #define OSSR_M1 OSSR_M (1) /* Match detected 1 */
1163 #define OSSR_M2 OSSR_M (2) /* Match detected 2 */
1164 #define OSSR_M3 OSSR_M (3) /* Match detected 3 */
1165
1166 #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
1167 /* (set only) */
1168
1169 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
1170 (0x00000001 << (Nb))
1171 #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
1172 #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
1173 #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
1174 #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
1175
1176
1177 /*
1178 * Real-Time Clock (RTC) control registers
1179 *
1180 * Registers
1181 * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
1182 * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
1183 * RTTR Real-Time Clock (RTC) Trim Register (read/write).
1184 * RTSR Real-Time Clock (RTC) Status Register (read/write).
1185 *
1186 * Clocks
1187 * frtx, Trtx Frequency, period of the real-time clock crystal
1188 * (32.768 kHz nominal).
1189 * frtc, Trtc Frequency, period of the real-time clock counter
1190 * (1 Hz nominal).
1191 */
1192
1193 #define _RTAR 0x90010000 /* RTC Alarm Reg. */
1194 #define _RCNR 0x90010004 /* RTC CouNt Reg. */
1195 #define _RTTR 0x90010008 /* RTC Trim Reg. */
1196 #define _RTSR 0x90010010 /* RTC Status Reg. */
1197
1198 #if LANGUAGE == C
1199 #define RTAR /* RTC Alarm Reg. */ \
1200 (*((volatile Word *) io_p2v (_RTAR)))
1201 #define RCNR /* RTC CouNt Reg. */ \
1202 (*((volatile Word *) io_p2v (_RCNR)))
1203 #define RTTR /* RTC Trim Reg. */ \
1204 (*((volatile Word *) io_p2v (_RTTR)))
1205 #define RTSR /* RTC Status Reg. */ \
1206 (*((volatile Word *) io_p2v (_RTSR)))
1207 #endif /* LANGUAGE == C */
1208
1209 #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
1210 #define RTTR_D Fld (10, 16) /* trim Delete count */
1211 /* frtc = (1023*(C + 1) - D)*frtx/ */
1212 /* (1023*(C + 1)^2) */
1213 /* Trtc = (1023*(C + 1)^2)*Trtx/ */
1214 /* (1023*(C + 1) - D) */
1215
1216 #define RTSR_AL 0x00000001 /* ALarm detected */
1217 #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
1218 #define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
1219 #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
1220
1221
1222 /*
1223 * Power Manager (PM) control registers
1224 *
1225 * Registers
1226 * PMCR Power Manager (PM) Control Register (read/write).
1227 * PSSR Power Manager (PM) Sleep Status Register (read/write).
1228 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
1229 * PWER Power Manager (PM) Wake-up Enable Register
1230 * (read/write).
1231 * PCFR Power Manager (PM) general ConFiguration Register
1232 * (read/write).
1233 * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
1234 * Configuration Register (read/write).
1235 * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
1236 * Sleep state Register (read/write, see GPIO pins).
1237 * POSR Power Manager (PM) Oscillator Status Register (read).
1238 *
1239 * Clocks
1240 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
1241 * or 3.5795 MHz).
1242 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1243 */
1244
1245 #define _PMCR 0x90020000 /* PM Control Reg. */
1246 #define _PSSR 0x90020004 /* PM Sleep Status Reg. */
1247 #define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
1248 #define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
1249 #define _PCFR 0x90020010 /* PM general ConFiguration Reg. */
1250 #define _PPCR 0x90020014 /* PM PLL Configuration Reg. */
1251 #define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */
1252 #define _POSR 0x9002001C /* PM Oscillator Status Reg. */
1253
1254 #if LANGUAGE == C
1255 #define PMCR /* PM Control Reg. */ \
1256 (*((volatile Word *) io_p2v (_PMCR)))
1257 #define PSSR /* PM Sleep Status Reg. */ \
1258 (*((volatile Word *) io_p2v (_PSSR)))
1259 #define PSPR /* PM Scratch-Pad Reg. */ \
1260 (*((volatile Word *) io_p2v (_PSPR)))
1261 #define PWER /* PM Wake-up Enable Reg. */ \
1262 (*((volatile Word *) io_p2v (_PWER)))
1263 #define PCFR /* PM general ConFiguration Reg. */ \
1264 (*((volatile Word *) io_p2v (_PCFR)))
1265 #define PPCR /* PM PLL Configuration Reg. */ \
1266 (*((volatile Word *) io_p2v (_PPCR)))
1267 #define PGSR /* PM GPIO Sleep state Reg. */ \
1268 (*((volatile Word *) io_p2v (_PGSR)))
1269 #define POSR /* PM Oscillator Status Reg. */ \
1270 (*((volatile Word *) io_p2v (_POSR)))
1271
1272 #elif LANGUAGE == Assembly
1273 #define PMCR (io_p2v (_PMCR))
1274 #define PSSR (io_p2v (_PSSR))
1275 #define PSPR (io_p2v (_PSPR))
1276 #define PWER (io_p2v (_PWER))
1277 #define PCFR (io_p2v (_PCFR))
1278 #define PPCR (io_p2v (_PPCR))
1279 #define PGSR (io_p2v (_PGSR))
1280 #define POSR (io_p2v (_POSR))
1281
1282 #endif /* LANGUAGE == C */
1283
1284 #define PMCR_SF 0x00000001 /* Sleep Force (set only) */
1285
1286 #define PSSR_SS 0x00000001 /* Software Sleep */
1287 #define PSSR_BFS 0x00000002 /* Battery Fault Status */
1288 /* (BATT_FAULT) */
1289 #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
1290 #define PSSR_DH 0x00000008 /* DRAM control Hold */
1291 #define PSSR_PH 0x00000010 /* Peripheral control Hold */
1292
1293 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
1294 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1295 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1296 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1297 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1298 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1299 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1300 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1301 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1302 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1303 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1304 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1305 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1306 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1307 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1308 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1309 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1310 #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
1311 #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
1312 #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
1313 #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
1314 #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
1315 #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
1316 #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
1317 #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
1318 #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
1319 #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
1320 #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
1321 #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
1322 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1323
1324 #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
1325 #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
1326 #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
1327 #define PCFR_FP 0x00000002 /* Float PCMCIA pins */
1328 #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
1329 #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
1330 #define PCFR_FS 0x00000004 /* Float Static memory pins */
1331 #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
1332 #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
1333 #define PCFR_FO 0x00000008 /* Force RTC oscillator */
1334 /* (32.768 kHz) enable On */
1335
1336 #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
1337 #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
1338 (0x00 << FShft (PPCR_CCF))
1339 #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
1340 (0x01 << FShft (PPCR_CCF))
1341 #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
1342 (0x02 << FShft (PPCR_CCF))
1343 #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
1344 (0x03 << FShft (PPCR_CCF))
1345 #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
1346 (0x04 << FShft (PPCR_CCF))
1347 #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
1348 (0x05 << FShft (PPCR_CCF))
1349 #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
1350 (0x06 << FShft (PPCR_CCF))
1351 #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
1352 (0x07 << FShft (PPCR_CCF))
1353 #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
1354 (0x08 << FShft (PPCR_CCF))
1355 #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
1356 (0x09 << FShft (PPCR_CCF))
1357 #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
1358 (0x0A << FShft (PPCR_CCF))
1359 #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
1360 (0x0B << FShft (PPCR_CCF))
1361 #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
1362 (0x0C << FShft (PPCR_CCF))
1363 #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
1364 (0x0D << FShft (PPCR_CCF))
1365 #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
1366 (0x0E << FShft (PPCR_CCF))
1367 #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
1368 (0x0F << FShft (PPCR_CCF))
1369 /* 3.6864 MHz crystal (fxtl): */
1370 #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
1371 #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
1372 #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
1373 #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
1374 #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
1375 #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
1376 #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
1377 #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
1378 #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
1379 #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
1380 #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
1381 #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
1382 #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
1383 #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
1384 #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
1385 #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
1386 /* 3.5795 MHz crystal (fxtl): */
1387 #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
1388 #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
1389 #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
1390 #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
1391 #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
1392 #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
1393 #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
1394 #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
1395 #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
1396 #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
1397 #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
1398 #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
1399 #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
1400 #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
1401 #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
1402 #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
1403
1404 #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
1405
1406
1407 /*
1408 * Reset Controller (RC) control registers
1409 *
1410 * Registers
1411 * RSRR Reset Controller (RC) Software Reset Register
1412 * (read/write).
1413 * RCSR Reset Controller (RC) Status Register (read/write).
1414 */
1415
1416 #define _RSRR 0x90030000 /* RC Software Reset Reg. */
1417 #define _RCSR 0x90030004 /* RC Status Reg. */
1418
1419 #if LANGUAGE == C
1420 #define RSRR /* RC Software Reset Reg. */ \
1421 (*((volatile Word *) io_p2v (_RSRR)))
1422 #define RCSR /* RC Status Reg. */ \
1423 (*((volatile Word *) io_p2v (_RCSR)))
1424 #endif /* LANGUAGE == C */
1425
1426 #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
1427
1428 #define RCSR_HWR 0x00000001 /* HardWare Reset */
1429 #define RCSR_SWR 0x00000002 /* SoftWare Reset */
1430 #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1431 #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1432
1433
1434 /*
1435 * Test unit control registers
1436 *
1437 * Registers
1438 * TUCR Test Unit Control Register (read/write).
1439 */
1440
1441 #define _TUCR 0x90030008 /* Test Unit Control Reg. */
1442
1443 #if LANGUAGE == C
1444 #define TUCR /* Test Unit Control Reg. */ \
1445 (*((volatile Word *) io_p2v (_TUCR)))
1446 #endif /* LANGUAGE == C */
1447
1448 #define TUCR_TIC 0x00000040 /* TIC mode */
1449 #define TUCR_TTST 0x00000080 /* Trim TeST mode */
1450 #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
1451 /* Check */
1452 #define TUCR_PMD 0x00000200 /* Power Management Disable */
1453 #define TUCR_MR 0x00000400 /* Memory Request mode */
1454 #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
1455 #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
1456 /* grant (MBGNT) on GPIO [22:21] */
1457 #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
1458 #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
1459 #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
1460 #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
1461 #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
1462 #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
1463 #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
1464 (0 << FShft (TUCR_TSEL))
1465 #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
1466 (1 << FShft (TUCR_TSEL))
1467 #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
1468 (2 << FShft (TUCR_TSEL))
1469 #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
1470 (3 << FShft (TUCR_TSEL))
1471 #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
1472 /* Clocks on GPIO [26:27] */ \
1473 (4 << FShft (TUCR_TSEL))
1474 #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
1475 /* (Alternative) */ \
1476 (5 << FShft (TUCR_TSEL))
1477 #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
1478 (6 << FShft (TUCR_TSEL))
1479 #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
1480 (7 << FShft (TUCR_TSEL))
1481
1482
1483 /*
1484 * General-Purpose Input/Output (GPIO) control registers
1485 *
1486 * Registers
1487 * GPLR General-Purpose Input/Output (GPIO) Pin Level
1488 * Register (read).
1489 * GPDR General-Purpose Input/Output (GPIO) Pin Direction
1490 * Register (read/write).
1491 * GPSR General-Purpose Input/Output (GPIO) Pin output Set
1492 * Register (write).
1493 * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
1494 * Register (write).
1495 * GRER General-Purpose Input/Output (GPIO) Rising-Edge
1496 * detect Register (read/write).
1497 * GFER General-Purpose Input/Output (GPIO) Falling-Edge
1498 * detect Register (read/write).
1499 * GEDR General-Purpose Input/Output (GPIO) Edge Detect
1500 * status Register (read/write).
1501 * GAFR General-Purpose Input/Output (GPIO) Alternate
1502 * Function Register (read/write).
1503 *
1504 * Clock
1505 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1506 */
1507
1508 #define _GPLR 0x90040000 /* GPIO Pin Level Reg. */
1509 #define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */
1510 #define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */
1511 #define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */
1512 #define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
1513 #define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
1514 #define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */
1515 #define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */
1516
1517 #if LANGUAGE == C
1518 #define GPLR /* GPIO Pin Level Reg. */ \
1519 (*((volatile Word *) io_p2v (_GPLR)))
1520 #define GPDR /* GPIO Pin Direction Reg. */ \
1521 (*((volatile Word *) io_p2v (_GPDR)))
1522 #define GPSR /* GPIO Pin output Set Reg. */ \
1523 (*((volatile Word *) io_p2v (_GPSR)))
1524 #define GPCR /* GPIO Pin output Clear Reg. */ \
1525 (*((volatile Word *) io_p2v (_GPCR)))
1526 #define GRER /* GPIO Rising-Edge detect Reg. */ \
1527 (*((volatile Word *) io_p2v (_GRER)))
1528 #define GFER /* GPIO Falling-Edge detect Reg. */ \
1529 (*((volatile Word *) io_p2v (_GFER)))
1530 #define GEDR /* GPIO Edge Detect status Reg. */ \
1531 (*((volatile Word *) io_p2v (_GEDR)))
1532 #define GAFR /* GPIO Alternate Function Reg. */ \
1533 (*((volatile Word *) io_p2v (_GAFR)))
1534 #elif LANGUAGE == Assembly
1535
1536 #define GPLR (io_p2v (_GPLR))
1537 #define GPDR (io_p2v (_GPDR))
1538 #define GPSR (io_p2v (_GPSR))
1539 #define GPCR (io_p2v (_GPCR))
1540 #define GRER (io_p2v (_GRER))
1541 #define GFER (io_p2v (_GFER))
1542 #define GEDR (io_p2v (_GEDR))
1543 #define GAFR (io_p2v (_GAFR))
1544
1545 #endif /* LANGUAGE == C */
1546
1547 #define GPIO_MIN (0)
1548 #define GPIO_MAX (27)
1549
1550 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
1551 (0x00000001 << (Nb))
1552 #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
1553 #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
1554 #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
1555 #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
1556 #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
1557 #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
1558 #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
1559 #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
1560 #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
1561 #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
1562 #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
1563 #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
1564 #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
1565 #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
1566 #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
1567 #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
1568 #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
1569 #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
1570 #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
1571 #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
1572 #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
1573 #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
1574 #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
1575 #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
1576 #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
1577 #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
1578 #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
1579 #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
1580
1581 #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
1582 GPIO_GPIO ((Nb) - 6)
1583 #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
1584 #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
1585 #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
1586 #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
1587 #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
1588 #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
1589 #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
1590 #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
1591 /* ser. port 4: */
1592 #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
1593 #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
1594 #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
1595 #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
1596 /* ser. port 1: */
1597 #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
1598 #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
1599 #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
1600 #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
1601 #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
1602 /* ser. port 4: */
1603 #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
1604 /* ser. port 3: */
1605 #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
1606 /* ser. port 4: */
1607 #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
1608 /* test controller: */
1609 #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
1610 #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
1611 #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
1612 #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
1613 #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
1614 #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
1615 #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
1616 #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
1617
1618 #define GPDR_In 0 /* Input */
1619 #define GPDR_Out 1 /* Output */
1620
1621
1622 /*
1623 * Interrupt Controller (IC) control registers
1624 *
1625 * Registers
1626 * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
1627 * Pending register (read).
1628 * ICMR Interrupt Controller (IC) Mask Register (read/write).
1629 * ICLR Interrupt Controller (IC) Level Register (read/write).
1630 * ICCR Interrupt Controller (IC) Control Register
1631 * (read/write).
1632 * [The ICCR register is only implemented in versions 2.0
1633 * (rev. = 8) and higher of the StrongARM SA-1100.]
1634 * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
1635 * (FIQ) Pending register (read).
1636 * ICPR Interrupt Controller (IC) Pending Register (read).
1637 * [The ICPR register is active low (inverted) in
1638 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1639 * StrongARM SA-1100, it is active high (non-inverted) in
1640 * versions 2.0 (rev. = 8) and higher.]
1641 */
1642
1643 #define _ICIP 0x90050000 /* IC IRQ Pending reg. */
1644 #define _ICMR 0x90050004 /* IC Mask Reg. */
1645 #define _ICLR 0x90050008 /* IC Level Reg. */
1646 #define _ICCR 0x9005000C /* IC Control Reg. */
1647 #define _ICFP 0x90050010 /* IC FIQ Pending reg. */
1648 #define _ICPR 0x90050020 /* IC Pending Reg. */
1649
1650 #if LANGUAGE == C
1651 #define ICIP /* IC IRQ Pending reg. */ \
1652 (*((volatile Word *) io_p2v (_ICIP)))
1653 #define ICMR /* IC Mask Reg. */ \
1654 (*((volatile Word *) io_p2v (_ICMR)))
1655 #define ICLR /* IC Level Reg. */ \
1656 (*((volatile Word *) io_p2v (_ICLR)))
1657 #define ICCR /* IC Control Reg. */ \
1658 (*((volatile Word *) io_p2v (_ICCR)))
1659 #define ICFP /* IC FIQ Pending reg. */ \
1660 (*((volatile Word *) io_p2v (_ICFP)))
1661 #define ICPR /* IC Pending Reg. */ \
1662 (*((volatile Word *) io_p2v (_ICPR)))
1663 #endif /* LANGUAGE == C */
1664
1665 #define IC_GPIO(Nb) /* GPIO [0..10] */ \
1666 (0x00000001 << (Nb))
1667 #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
1668 #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
1669 #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
1670 #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
1671 #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
1672 #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
1673 #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
1674 #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
1675 #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
1676 #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
1677 #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
1678 #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
1679 #define IC_LCD 0x00001000 /* LCD controller */
1680 #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
1681 #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
1682 #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
1683 #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
1684 #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
1685 #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
1686 #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
1687 #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
1688 (0x00100000 << (Nb))
1689 #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
1690 #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
1691 #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
1692 #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
1693 #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
1694 #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
1695 #define IC_OST(Nb) /* OS Timer match [0..3] */ \
1696 (0x04000000 << (Nb))
1697 #define IC_OST0 IC_OST (0) /* OS Timer match 0 */
1698 #define IC_OST1 IC_OST (1) /* OS Timer match 1 */
1699 #define IC_OST2 IC_OST (2) /* OS Timer match 2 */
1700 #define IC_OST3 IC_OST (3) /* OS Timer match 3 */
1701 #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
1702 #define IC_RTCAlrm 0x80000000 /* RTC Alarm */
1703
1704 #define ICLR_IRQ 0 /* Interrupt ReQuest */
1705 #define ICLR_FIQ 1 /* Fast Interrupt reQuest */
1706
1707 #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1708 /* Mask */
1709 #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1710 /* (ICMR ignored) */
1711 #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
1712 /* enable (ICMR used) */
1713
1714
1715 /*
1716 * Peripheral Pin Controller (PPC) control registers
1717 *
1718 * Registers
1719 * PPDR Peripheral Pin Controller (PPC) Pin Direction
1720 * Register (read/write).
1721 * PPSR Peripheral Pin Controller (PPC) Pin State Register
1722 * (read/write).
1723 * PPAR Peripheral Pin Controller (PPC) Pin Assignment
1724 * Register (read/write).
1725 * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
1726 * Direction Register (read/write).
1727 * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
1728 * (read).
1729 */
1730
1731 #define _PPDR 0x90060000 /* PPC Pin Direction Reg. */
1732 #define _PPSR 0x90060004 /* PPC Pin State Reg. */
1733 #define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */
1734 #define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
1735 /* Reg. */
1736 #define _PPFR 0x90060010 /* PPC Pin Flag Reg. */
1737
1738 #if LANGUAGE == C
1739 #define PPDR /* PPC Pin Direction Reg. */ \
1740 (*((volatile Word *) io_p2v (_PPDR)))
1741 #define PPSR /* PPC Pin State Reg. */ \
1742 (*((volatile Word *) io_p2v (_PPSR)))
1743 #define PPAR /* PPC Pin Assignment Reg. */ \
1744 (*((volatile Word *) io_p2v (_PPAR)))
1745 #define PSDR /* PPC Sleep-mode pin Direction */ \
1746 /* Reg. */ \
1747 (*((volatile Word *) io_p2v (_PSDR)))
1748 #define PPFR /* PPC Pin Flag Reg. */ \
1749 (*((volatile Word *) io_p2v (_PPFR)))
1750 #endif /* LANGUAGE == C */
1751
1752 #define PPC_LDD(Nb) /* LCD Data [0..7] */ \
1753 (0x00000001 << (Nb))
1754 #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
1755 #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
1756 #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
1757 #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
1758 #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
1759 #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
1760 #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
1761 #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
1762 #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
1763 #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
1764 #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
1765 #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
1766 /* ser. port 1: */
1767 #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
1768 #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
1769 /* ser. port 2: */
1770 #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
1771 #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
1772 /* ser. port 3: */
1773 #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
1774 #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
1775 /* ser. port 4: */
1776 #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
1777 #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
1778 #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
1779 #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
1780
1781 #define PPDR_In 0 /* Input */
1782 #define PPDR_Out 1 /* Output */
1783
1784 /* ser. port 1: */
1785 #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
1786 #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
1787 #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
1788 /* ser. port 4: */
1789 #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
1790 #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
1791 /* & SFRM_C */
1792 #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
1793
1794 #define PSDR_OutL 0 /* Output Low in sleep mode */
1795 #define PSDR_Flt 1 /* Floating (input) in sleep mode */
1796
1797 #define PPFR_LCD 0x00000001 /* LCD controller */
1798 #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
1799 #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
1800 #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
1801 #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
1802 #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
1803 #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
1804 #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
1805 #define PPFR_PerEn 0 /* Peripheral Enabled */
1806 #define PPFR_PPCEn 1 /* PPC Enabled */
1807
1808
1809 /*
1810 * Dynamic Random-Access Memory (DRAM) control registers
1811 *
1812 * Registers
1813 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1814 * CoNFiGuration register (read/write).
1815 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1816 * Column Address Strobe (CAS) shift register 0
1817 * (read/write).
1818 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1819 * Column Address Strobe (CAS) shift register 1
1820 * (read/write).
1821 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1822 * Column Address Strobe (CAS) shift register 2
1823 * (read/write).
1824 *
1825 * Clocks
1826 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1827 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1828 * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
1829 */
1830
1831 /* Memory system: */
1832 #define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */
1833 #define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \
1834 (0xA0000004 + (Nb)*4)
1835 #define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */
1836 #define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
1837 #define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */
1838
1839 #if LANGUAGE == C
1840 /* Memory system: */
1841 #define MDCNFG /* DRAM CoNFiGuration reg. */ \
1842 (*((volatile Word *) io_p2v (_MDCNFG)))
1843 #define MDCAS /* DRAM CAS shift reg. [0..3] */ \
1844 ((volatile Word *) io_p2v (_MDCAS (0)))
1845 #define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */
1846 #define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
1847 #define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */
1848
1849 #elif LANGUAGE == Assembly
1850
1851 #define MDCNFG (io_p2v(_MDCNFG))
1852
1853 #endif /* LANGUAGE == C */
1854
1855 /* SA1100 MDCNFG values */
1856 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
1857 (0x00000001 << (Nb))
1858 #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
1859 #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
1860 #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
1861 #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
1862 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1863 #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
1864 (((Add) - 9) << FShft (MDCNFG_DRAC))
1865 #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
1866 /* (fcas = fcpu/2) */
1867 #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1868 #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
1869 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1870 #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
1871 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1872 #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1873 #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
1874 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1875 #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
1876 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1877 #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
1878 #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
1879 ((Tcpu) << FShft (MDCNFG_TDL))
1880 #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
1881 /* [Tmem] */
1882 #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
1883 /* [0..262136 Tcpu] */ \
1884 ((Tcpu)/8 << FShft (MDCNFG_DRI))
1885
1886 /* SA1110 MDCNFG values */
1887 #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
1888 #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
1889 #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
1890 #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
1891 #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
1892 /* bank 0/1 */
1893 #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
1894 #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
1895 #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
1896 /* deassertion 0/1 */
1897 #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1898 #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
1899 #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
1900 #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
1901 #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
1902 #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
1903 /* bank 0/1 */
1904 #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
1905 #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
1906 #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
1907 /* deassertion 0/1 */
1908 #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1909
1910
1911 /*
1912 * Static memory control registers
1913 *
1914 * Registers
1915 * MSC0 Memory system: Static memory Control register 0
1916 * (read/write).
1917 * MSC1 Memory system: Static memory Control register 1
1918 * (read/write).
1919 *
1920 * Clocks
1921 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1922 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1923 */
1924
1925 /* Memory system: */
1926 #define _MSC(Nb) /* Static memory Control reg. */ \
1927 /* [0..1] */ \
1928 (0xA0000010 + (Nb)*4)
1929 #define _MSC0 _MSC (0) /* Static memory Control reg. 0 */
1930 #define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
1931 #define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */
1932
1933 #if LANGUAGE == C
1934 /* Memory system: */
1935 #define MSC /* Static memory Control reg. */ \
1936 /* [0..1] */ \
1937 ((volatile Word *) io_p2v (_MSC (0)))
1938 #define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
1939 #define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
1940 #define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
1941
1942 #elif LANGUAGE == Assembly
1943
1944 #define MSC0 io_p2v(0xa0000010)
1945 #define MSC1 io_p2v(0xa0000014)
1946 #define MSC2 io_p2v(0xa000002c)
1947
1948 #endif /* LANGUAGE == C */
1949
1950 #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
1951 Fld (16, ((Nb) Modulo 2)*16)
1952 #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
1953 #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
1954 #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
1955 #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
1956
1957 #define MSC_RT Fld (2, 0) /* ROM/static memory Type */
1958 #define MSC_NonBrst /* Non-Burst static memory */ \
1959 (0 << FShft (MSC_RT))
1960 #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
1961 (1 << FShft (MSC_RT))
1962 #define MSC_Brst4 /* Burst-of-4 static memory */ \
1963 (2 << FShft (MSC_RT))
1964 #define MSC_Brst8 /* Burst-of-8 static memory */ \
1965 (3 << FShft (MSC_RT))
1966 #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
1967 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1968 #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1969 #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1970 /* First access - 1(.5) [Tmem] */
1971 #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
1972 /* static memory) [3..65 Tcpu] */ \
1973 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1974 #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
1975 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1976 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1977 /* static memory) [2..64 Tcpu] */ \
1978 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1979 #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
1980 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1981 #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1982 /* Next access - 1 [Tmem] */
1983 #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
1984 /* static memory) [2..64 Tcpu] */ \
1985 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1986 #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
1987 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1988 #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
1989 /* static memory) [2..64 Tcpu] */ \
1990 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1991 #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
1992 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1993 #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
1994 /* time/2 [Tmem] */
1995 #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
1996 (((Tcpu)/4) << FShft (MSC_RRR))
1997 #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
1998 ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
1999
2000
2001 /*
2002 * Personal Computer Memory Card International Association (PCMCIA) control
2003 * register
2004 *
2005 * Register
2006 * MECR Memory system: Expansion memory bus (PCMCIA)
2007 * Configuration Register (read/write).
2008 *
2009 * Clocks
2010 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
2011 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
2012 * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
2013 */
2014
2015 /* Memory system: */
2016 #define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */
2017 /* Configuration Reg. */
2018
2019 #if LANGUAGE == C
2020 /* Memory system: */
2021 #define MECR /* Expansion memory bus (PCMCIA) */ \
2022 /* Configuration Reg. */ \
2023 (*((volatile Word *) io_p2v (_MECR)))
2024 #endif /* LANGUAGE == C */
2025
2026 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
2027 Fld (15, (Nb)*16)
2028 #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
2029 #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
2030
2031 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
2032 #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
2033 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
2034 #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
2035 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
2036 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
2037 /* [Tmem] */
2038 #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
2039 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
2040 #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
2041 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
2042 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
2043 #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
2044 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
2045 #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
2046 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
2047
2048 /*
2049 * On SA1110 only
2050 */
2051
2052 #define _MDREFR 0xA000001C
2053
2054 #if LANGUAGE == C
2055 /* Memory system: */
2056 #define MDREFR \
2057 (*((volatile Word *) io_p2v (_MDREFR)))
2058
2059 #elif LANGUAGE == Assembly
2060
2061 #define MDREFR (io_p2v(_MDREFR))
2062
2063 #endif /* LANGUAGE == C */
2064
2065 #define MDREFR_TRASR Fld (4, 0)
2066 #define MDREFR_DRI Fld (12, 4)
2067 #define MDREFR_E0PIN (1 << 16)
2068 #define MDREFR_K0RUN (1 << 17)
2069 #define MDREFR_K0DB2 (1 << 18)
2070 #define MDREFR_E1PIN (1 << 20)
2071 #define MDREFR_K1RUN (1 << 21)
2072 #define MDREFR_K1DB2 (1 << 22)
2073 #define MDREFR_K2RUN (1 << 25)
2074 #define MDREFR_K2DB2 (1 << 26)
2075 #define MDREFR_EAPD (1 << 28)
2076 #define MDREFR_KAPD (1 << 29)
2077 #define MDREFR_SLFRSH (1 << 31)
2078
2079
2080 /*
2081 * Direct Memory Access (DMA) control registers
2082 *
2083 * Registers
2084 * DDAR0 Direct Memory Access (DMA) Device Address Register
2085 * channel 0 (read/write).
2086 * DCSR0 Direct Memory Access (DMA) Control and Status
2087 * Register channel 0 (read/write).
2088 * DBSA0 Direct Memory Access (DMA) Buffer Start address
2089 * register A channel 0 (read/write).
2090 * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
2091 * register A channel 0 (read/write).
2092 * DBSB0 Direct Memory Access (DMA) Buffer Start address
2093 * register B channel 0 (read/write).
2094 * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
2095 * register B channel 0 (read/write).
2096 *
2097 * DDAR1 Direct Memory Access (DMA) Device Address Register
2098 * channel 1 (read/write).
2099 * DCSR1 Direct Memory Access (DMA) Control and Status
2100 * Register channel 1 (read/write).
2101 * DBSA1 Direct Memory Access (DMA) Buffer Start address
2102 * register A channel 1 (read/write).
2103 * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
2104 * register A channel 1 (read/write).
2105 * DBSB1 Direct Memory Access (DMA) Buffer Start address
2106 * register B channel 1 (read/write).
2107 * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
2108 * register B channel 1 (read/write).
2109 *
2110 * DDAR2 Direct Memory Access (DMA) Device Address Register
2111 * channel 2 (read/write).
2112 * DCSR2 Direct Memory Access (DMA) Control and Status
2113 * Register channel 2 (read/write).
2114 * DBSA2 Direct Memory Access (DMA) Buffer Start address
2115 * register A channel 2 (read/write).
2116 * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
2117 * register A channel 2 (read/write).
2118 * DBSB2 Direct Memory Access (DMA) Buffer Start address
2119 * register B channel 2 (read/write).
2120 * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
2121 * register B channel 2 (read/write).
2122 *
2123 * DDAR3 Direct Memory Access (DMA) Device Address Register
2124 * channel 3 (read/write).
2125 * DCSR3 Direct Memory Access (DMA) Control and Status
2126 * Register channel 3 (read/write).
2127 * DBSA3 Direct Memory Access (DMA) Buffer Start address
2128 * register A channel 3 (read/write).
2129 * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
2130 * register A channel 3 (read/write).
2131 * DBSB3 Direct Memory Access (DMA) Buffer Start address
2132 * register B channel 3 (read/write).
2133 * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
2134 * register B channel 3 (read/write).
2135 *
2136 * DDAR4 Direct Memory Access (DMA) Device Address Register
2137 * channel 4 (read/write).
2138 * DCSR4 Direct Memory Access (DMA) Control and Status
2139 * Register channel 4 (read/write).
2140 * DBSA4 Direct Memory Access (DMA) Buffer Start address
2141 * register A channel 4 (read/write).
2142 * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
2143 * register A channel 4 (read/write).
2144 * DBSB4 Direct Memory Access (DMA) Buffer Start address
2145 * register B channel 4 (read/write).
2146 * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
2147 * register B channel 4 (read/write).
2148 *
2149 * DDAR5 Direct Memory Access (DMA) Device Address Register
2150 * channel 5 (read/write).
2151 * DCSR5 Direct Memory Access (DMA) Control and Status
2152 * Register channel 5 (read/write).
2153 * DBSA5 Direct Memory Access (DMA) Buffer Start address
2154 * register A channel 5 (read/write).
2155 * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
2156 * register A channel 5 (read/write).
2157 * DBSB5 Direct Memory Access (DMA) Buffer Start address
2158 * register B channel 5 (read/write).
2159 * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
2160 * register B channel 5 (read/write).
2161 */
2162
2163 #define DMASp 0x00000020 /* DMA control reg. Space [byte] */
2164
2165 #define _DDAR(Nb) /* DMA Device Address Reg. */ \
2166 /* channel [0..5] */ \
2167 (0xB0000000 + (Nb)*DMASp)
2168 #define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \
2169 /* channel [0..5] (write) */ \
2170 (0xB0000004 + (Nb)*DMASp)
2171 #define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \
2172 /* channel [0..5] (write) */ \
2173 (0xB0000008 + (Nb)*DMASp)
2174 #define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
2175 /* channel [0..5] (read) */ \
2176 (0xB000000C + (Nb)*DMASp)
2177 #define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
2178 /* channel [0..5] */ \
2179 (0xB0000010 + (Nb)*DMASp)
2180 #define _DBTA(Nb) /* DMA Buffer Transfer count */ \
2181 /* reg. A channel [0..5] */ \
2182 (0xB0000014 + (Nb)*DMASp)
2183 #define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
2184 /* channel [0..5] */ \
2185 (0xB0000018 + (Nb)*DMASp)
2186 #define _DBTB(Nb) /* DMA Buffer Transfer count */ \
2187 /* reg. B channel [0..5] */ \
2188 (0xB000001C + (Nb)*DMASp)
2189
2190 #define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
2191 /* channel 0 */
2192 #define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */
2193 /* channel 0 (write) */
2194 #define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */
2195 /* channel 0 (write) */
2196 #define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */
2197 /* channel 0 (read) */
2198 #define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
2199 /* channel 0 */
2200 #define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */
2201 /* reg. A channel 0 */
2202 #define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
2203 /* channel 0 */
2204 #define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */
2205 /* reg. B channel 0 */
2206
2207 #define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
2208 /* channel 1 */
2209 #define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */
2210 /* channel 1 (write) */
2211 #define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */
2212 /* channel 1 (write) */
2213 #define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */
2214 /* channel 1 (read) */
2215 #define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
2216 /* channel 1 */
2217 #define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
2218 /* reg. A channel 1 */
2219 #define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
2220 /* channel 1 */
2221 #define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
2222 /* reg. B channel 1 */
2223
2224 #define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
2225 /* channel 2 */
2226 #define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */
2227 /* channel 2 (write) */
2228 #define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */
2229 /* channel 2 (write) */
2230 #define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */
2231 /* channel 2 (read) */
2232 #define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
2233 /* channel 2 */
2234 #define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */
2235 /* reg. A channel 2 */
2236 #define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
2237 /* channel 2 */
2238 #define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */
2239 /* reg. B channel 2 */
2240
2241 #define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
2242 /* channel 3 */
2243 #define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */
2244 /* channel 3 (write) */
2245 #define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */
2246 /* channel 3 (write) */
2247 #define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */
2248 /* channel 3 (read) */
2249 #define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
2250 /* channel 3 */
2251 #define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */
2252 /* reg. A channel 3 */
2253 #define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */
2254 /* channel 3 */
2255 #define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */
2256 /* reg. B channel 3 */
2257
2258 #define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
2259 /* channel 4 */
2260 #define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */
2261 /* channel 4 (write) */
2262 #define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */
2263 /* channel 4 (write) */
2264 #define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */
2265 /* channel 4 (read) */
2266 #define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
2267 /* channel 4 */
2268 #define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */
2269 /* reg. A channel 4 */
2270 #define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
2271 /* channel 4 */
2272 #define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */
2273 /* reg. B channel 4 */
2274
2275 #define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
2276 /* channel 5 */
2277 #define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */
2278 /* channel 5 (write) */
2279 #define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */
2280 /* channel 5 (write) */
2281 #define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */
2282 /* channel 5 (read) */
2283 #define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
2284 /* channel 5 */
2285 #define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */
2286 /* reg. A channel 5 */
2287 #define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
2288 /* channel 5 */
2289 #define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */
2290 /* reg. B channel 5 */
2291
2292 #if LANGUAGE == C
2293
2294 #define DDAR0 /* DMA Device Address Reg. */ \
2295 /* channel 0 */ \
2296 (*((volatile Word *) io_p2v (_DDAR0)))
2297 #define SetDCSR0 /* Set DMA Control & Status Reg. */ \
2298 /* channel 0 (write) */ \
2299 (*((volatile Word *) io_p2v (_SetDCSR0)))
2300 #define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
2301 /* channel 0 (write) */ \
2302 (*((volatile Word *) io_p2v (_ClrDCSR0)))
2303 #define RdDCSR0 /* Read DMA Control & Status Reg. */ \
2304 /* channel 0 (read) */ \
2305 (*((volatile Word *) io_p2v (_RdDCSR0)))
2306 #define DBSA0 /* DMA Buffer Start address reg. A */ \
2307 /* channel 0 */ \
2308 (*((volatile Address *) io_p2v (_DBSA0)))
2309 #define DBTA0 /* DMA Buffer Transfer count */ \
2310 /* reg. A channel 0 */ \
2311 (*((volatile Word *) io_p2v (_DBTA0)))
2312 #define DBSB0 /* DMA Buffer Start address reg. B */ \
2313 /* channel 0 */ \
2314 (*((volatile Address *) io_p2v (_DBSB0)))
2315 #define DBTB0 /* DMA Buffer Transfer count */ \
2316 /* reg. B channel 0 */ \
2317 (*((volatile Word *) io_p2v (_DBTB0)))
2318
2319 #define DDAR1 /* DMA Device Address Reg. */ \
2320 /* channel 1 */ \
2321 (*((volatile Word *) io_p2v (_DDAR1)))
2322 #define SetDCSR1 /* Set DMA Control & Status Reg. */ \
2323 /* channel 1 (write) */ \
2324 (*((volatile Word *) io_p2v (_SetDCSR1)))
2325 #define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
2326 /* channel 1 (write) */ \
2327 (*((volatile Word *) io_p2v (_ClrDCSR1)))
2328 #define RdDCSR1 /* Read DMA Control & Status Reg. */ \
2329 /* channel 1 (read) */ \
2330 (*((volatile Word *) io_p2v (_RdDCSR1)))
2331 #define DBSA1 /* DMA Buffer Start address reg. A */ \
2332 /* channel 1 */ \
2333 (*((volatile Address *) io_p2v (_DBSA1)))
2334 #define DBTA1 /* DMA Buffer Transfer count */ \
2335 /* reg. A channel 1 */ \
2336 (*((volatile Word *) io_p2v (_DBTA1)))
2337 #define DBSB1 /* DMA Buffer Start address reg. B */ \
2338 /* channel 1 */ \
2339 (*((volatile Address *) io_p2v (_DBSB1)))
2340 #define DBTB1 /* DMA Buffer Transfer count */ \
2341 /* reg. B channel 1 */ \
2342 (*((volatile Word *) io_p2v (_DBTB1)))
2343
2344 #define DDAR2 /* DMA Device Address Reg. */ \
2345 /* channel 2 */ \
2346 (*((volatile Word *) io_p2v (_DDAR2)))
2347 #define SetDCSR2 /* Set DMA Control & Status Reg. */ \
2348 /* channel 2 (write) */ \
2349 (*((volatile Word *) io_p2v (_SetDCSR2)))
2350 #define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
2351 /* channel 2 (write) */ \
2352 (*((volatile Word *) io_p2v (_ClrDCSR2)))
2353 #define RdDCSR2 /* Read DMA Control & Status Reg. */ \
2354 /* channel 2 (read) */ \
2355 (*((volatile Word *) io_p2v (_RdDCSR2)))
2356 #define DBSA2 /* DMA Buffer Start address reg. A */ \
2357 /* channel 2 */ \
2358 (*((volatile Address *) io_p2v (_DBSA2)))
2359 #define DBTA2 /* DMA Buffer Transfer count */ \
2360 /* reg. A channel 2 */ \
2361 (*((volatile Word *) io_p2v (_DBTA2)))
2362 #define DBSB2 /* DMA Buffer Start address reg. B */ \
2363 /* channel 2 */ \
2364 (*((volatile Address *) io_p2v (_DBSB2)))
2365 #define DBTB2 /* DMA Buffer Transfer count */ \
2366 /* reg. B channel 2 */ \
2367 (*((volatile Word *) io_p2v (_DBTB2)))
2368
2369 #define DDAR3 /* DMA Device Address Reg. */ \
2370 /* channel 3 */ \
2371 (*((volatile Word *) io_p2v (_DDAR3)))
2372 #define SetDCSR3 /* Set DMA Control & Status Reg. */ \
2373 /* channel 3 (write) */ \
2374 (*((volatile Word *) io_p2v (_SetDCSR3)))
2375 #define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
2376 /* channel 3 (write) */ \
2377 (*((volatile Word *) io_p2v (_ClrDCSR3)))
2378 #define RdDCSR3 /* Read DMA Control & Status Reg. */ \
2379 /* channel 3 (read) */ \
2380 (*((volatile Word *) io_p2v (_RdDCSR3)))
2381 #define DBSA3 /* DMA Buffer Start address reg. A */ \
2382 /* channel 3 */ \
2383 (*((volatile Address *) io_p2v (_DBSA3)))
2384 #define DBTA3 /* DMA Buffer Transfer count */ \
2385 /* reg. A channel 3 */ \
2386 (*((volatile Word *) io_p2v (_DBTA3)))
2387 #define DBSB3 /* DMA Buffer Start address reg. B */ \
2388 /* channel 3 */ \
2389 (*((volatile Address *) io_p2v (_DBSB3)))
2390 #define DBTB3 /* DMA Buffer Transfer count */ \
2391 /* reg. B channel 3 */ \
2392 (*((volatile Word *) io_p2v (_DBTB3)))
2393
2394 #define DDAR4 /* DMA Device Address Reg. */ \
2395 /* channel 4 */ \
2396 (*((volatile Word *) io_p2v (_DDAR4)))
2397 #define SetDCSR4 /* Set DMA Control & Status Reg. */ \
2398 /* channel 4 (write) */ \
2399 (*((volatile Word *) io_p2v (_SetDCSR4)))
2400 #define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
2401 /* channel 4 (write) */ \
2402 (*((volatile Word *) io_p2v (_ClrDCSR4)))
2403 #define RdDCSR4 /* Read DMA Control & Status Reg. */ \
2404 /* channel 4 (read) */ \
2405 (*((volatile Word *) io_p2v (_RdDCSR4)))
2406 #define DBSA4 /* DMA Buffer Start address reg. A */ \
2407 /* channel 4 */ \
2408 (*((volatile Address *) io_p2v (_DBSA4)))
2409 #define DBTA4 /* DMA Buffer Transfer count */ \
2410 /* reg. A channel 4 */ \
2411 (*((volatile Word *) io_p2v (_DBTA4)))
2412 #define DBSB4 /* DMA Buffer Start address reg. B */ \
2413 /* channel 4 */ \
2414 (*((volatile Address *) io_p2v (_DBSB4)))
2415 #define DBTB4 /* DMA Buffer Transfer count */ \
2416 /* reg. B channel 4 */ \
2417 (*((volatile Word *) io_p2v (_DBTB4)))
2418
2419 #define DDAR5 /* DMA Device Address Reg. */ \
2420 /* channel 5 */ \
2421 (*((volatile Word *) io_p2v (_DDAR5)))
2422 #define SetDCSR5 /* Set DMA Control & Status Reg. */ \
2423 /* channel 5 (write) */ \
2424 (*((volatile Word *) io_p2v (_SetDCSR5)))
2425 #define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
2426 /* channel 5 (write) */ \
2427 (*((volatile Word *) io_p2v (_ClrDCSR5)))
2428 #define RdDCSR5 /* Read DMA Control & Status Reg. */ \
2429 /* channel 5 (read) */ \
2430 (*((volatile Word *) io_p2v (_RdDCSR5)))
2431 #define DBSA5 /* DMA Buffer Start address reg. A */ \
2432 /* channel 5 */ \
2433 (*((volatile Address *) io_p2v (_DBSA5)))
2434 #define DBTA5 /* DMA Buffer Transfer count */ \
2435 /* reg. A channel 5 */ \
2436 (*((volatile Word *) io_p2v (_DBTA5)))
2437 #define DBSB5 /* DMA Buffer Start address reg. B */ \
2438 /* channel 5 */ \
2439 (*((volatile Address *) io_p2v (_DBSB5)))
2440 #define DBTB5 /* DMA Buffer Transfer count */ \
2441 /* reg. B channel 5 */ \
2442 (*((volatile Word *) io_p2v (_DBTB5)))
2443
2444 #endif /* LANGUAGE == C */
2445
2446 #define DDAR_RW 0x00000001 /* device data Read/Write */
2447 #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
2448 /* (memory -> device) */
2449 #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
2450 /* (device -> memory) */
2451 #define DDAR_E 0x00000002 /* big/little Endian device */
2452 #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
2453 #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
2454 #define DDAR_BS 0x00000004 /* device Burst Size */
2455 #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
2456 #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
2457 #define DDAR_DW 0x00000008 /* device Data Width */
2458 #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
2459 #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
2460 #define DDAR_DS Fld (4, 4) /* Device Select */
2461 #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
2462 (0x0 << FShft (DDAR_DS))
2463 #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
2464 (0x1 << FShft (DDAR_DS))
2465 #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
2466 (0x2 << FShft (DDAR_DS))
2467 #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
2468 (0x3 << FShft (DDAR_DS))
2469 #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
2470 (0x4 << FShft (DDAR_DS))
2471 #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
2472 (0x5 << FShft (DDAR_DS))
2473 #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
2474 (0x6 << FShft (DDAR_DS))
2475 #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
2476 (0x7 << FShft (DDAR_DS))
2477 #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
2478 (0x8 << FShft (DDAR_DS))
2479 #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
2480 (0x9 << FShft (DDAR_DS))
2481 #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
2482 /* (audio) */ \
2483 (0xA << FShft (DDAR_DS))
2484 #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
2485 /* (audio) */ \
2486 (0xB << FShft (DDAR_DS))
2487 #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
2488 /* (telecom) */ \
2489 (0xC << FShft (DDAR_DS))
2490 #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
2491 /* (telecom) */ \
2492 (0xD << FShft (DDAR_DS))
2493 #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
2494 (0xE << FShft (DDAR_DS))
2495 #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
2496 (0xF << FShft (DDAR_DS))
2497 #define DDAR_DA Fld (24, 8) /* Device Address */
2498 #define DDAR_DevAdd(Add) /* Device Address */ \
2499 (((Add) & 0xF0000000) | \
2500 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
2501 #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
2502 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
2503 DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
2504 #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
2505 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
2506 DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
2507 #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
2508 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2509 DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
2510 #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
2511 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2512 DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
2513 #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
2514 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2515 DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
2516 #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
2517 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2518 DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
2519 #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
2520 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2521 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
2522 #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
2523 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2524 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
2525 #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
2526 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
2527 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
2528 #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
2529 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
2530 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
2531 #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
2532 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2533 DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
2534 #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
2535 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2536 DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
2537 #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
2538 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
2539 DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
2540 #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
2541 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
2542 DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
2543 #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
2544 /* (telecom) */ \
2545 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
2546 DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
2547 #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
2548 /* (telecom) */ \
2549 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
2550 DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
2551 #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
2552 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
2553 DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
2554 #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
2555 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
2556 DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
2557
2558 #define DCSR_RUN 0x00000001 /* DMA RUNing */
2559 #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
2560 #define DCSR_ERROR 0x00000004 /* DMA ERROR */
2561 #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
2562 #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
2563 #define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
2564 #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
2565 #define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
2566 #define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
2567 #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
2568
2569 #define DBT_TC Fld (13, 0) /* Transfer Count */
2570 #define DBTA_TCA DBT_TC /* Transfer Count buffer A */
2571 #define DBTB_TCB DBT_TC /* Transfer Count buffer B */
2572
2573
2574 /*
2575 * Liquid Crystal Display (LCD) control registers
2576 *
2577 * Registers
2578 * LCCR0 Liquid Crystal Display (LCD) Control Register 0
2579 * (read/write).
2580 * [Bits LDM, BAM, and ERM are only implemented in
2581 * versions 2.0 (rev. = 8) and higher of the StrongARM
2582 * SA-1100.]
2583 * LCSR Liquid Crystal Display (LCD) Status Register
2584 * (read/write).
2585 * [Bit LDD can be only read in versions 1.0 (rev. = 1)
2586 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
2587 * read and written (cleared) in versions 2.0 (rev. = 8)
2588 * and higher.]
2589 * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
2590 * (DMA) Base Address Register channel 1 (read/write).
2591 * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
2592 * (DMA) Current Address Register channel 1 (read).
2593 * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
2594 * (DMA) Base Address Register channel 2 (read/write).
2595 * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
2596 * (DMA) Current Address Register channel 2 (read).
2597 * LCCR1 Liquid Crystal Display (LCD) Control Register 1
2598 * (read/write).
2599 * [The LCCR1 register can be only written in
2600 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2601 * StrongARM SA-1100, it can be written and read in
2602 * versions 2.0 (rev. = 8) and higher.]
2603 * LCCR2 Liquid Crystal Display (LCD) Control Register 2
2604 * (read/write).
2605 * [The LCCR1 register can be only written in
2606 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2607 * StrongARM SA-1100, it can be written and read in
2608 * versions 2.0 (rev. = 8) and higher.]
2609 * LCCR3 Liquid Crystal Display (LCD) Control Register 3
2610 * (read/write).
2611 * [The LCCR1 register can be only written in
2612 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2613 * StrongARM SA-1100, it can be written and read in
2614 * versions 2.0 (rev. = 8) and higher. Bit PCP is only
2615 * implemented in versions 2.0 (rev. = 8) and higher of
2616 * the StrongARM SA-1100.]
2617 *
2618 * Clocks
2619 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
2620 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
2621 * fpix, Tpix Frequency, period of the pixel clock.
2622 * fln, Tln Frequency, period of the line clock.
2623 * fac, Tac Frequency, period of the AC bias clock.
2624 */
2625
2626 #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
2627 #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
2628 /* [byte] */ \
2629 (16*LCD_PEntrySp)
2630 #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
2631 /* [byte] */ \
2632 (256*LCD_PEntrySp)
2633 #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
2634 /* dummy-Palette Space [byte] */ \
2635 (16*LCD_PEntrySp)
2636
2637 #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
2638 #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
2639 #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
2640 #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
2641 #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
2642 #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
2643 (0 << FShft (LCD_PBS))
2644 #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
2645 (1 << FShft (LCD_PBS))
2646 #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
2647 (2 << FShft (LCD_PBS))
2648
2649 #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
2650 #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
2651 #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
2652 #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
2653 #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
2654 #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
2655 #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
2656 #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
2657 #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
2658 #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
2659 #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
2660 #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
2661 #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
2662 #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
2663 #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
2664 #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
2665 /* (Alternative) */
2666
2667 #define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
2668 #define _LCSR 0xB0100004 /* LCD Status Reg. */
2669 #define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
2670 /* channel 1 */
2671 #define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
2672 /* channel 1 */
2673 #define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
2674 /* channel 2 */
2675 #define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
2676 /* channel 2 */
2677 #define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
2678 #define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
2679 #define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
2680
2681 #if LANGUAGE == C
2682 #define LCCR0 /* LCD Control Reg. 0 */ \
2683 (*((volatile Word *) io_p2v (_LCCR0)))
2684 #define LCSR /* LCD Status Reg. */ \
2685 (*((volatile Word *) io_p2v (_LCSR)))
2686 #define DBAR1 /* LCD DMA Base Address Reg. */ \
2687 /* channel 1 */ \
2688 (*((volatile Address *) io_p2v (_DBAR1)))
2689 #define DCAR1 /* LCD DMA Current Address Reg. */ \
2690 /* channel 1 */ \
2691 (*((volatile Address *) io_p2v (_DCAR1)))
2692 #define DBAR2 /* LCD DMA Base Address Reg. */ \
2693 /* channel 2 */ \
2694 (*((volatile Address *) io_p2v (_DBAR2)))
2695 #define DCAR2 /* LCD DMA Current Address Reg. */ \
2696 /* channel 2 */ \
2697 (*((volatile Address *) io_p2v (_DCAR2)))
2698 #define LCCR1 /* LCD Control Reg. 1 */ \
2699 (*((volatile Word *) io_p2v (_LCCR1)))
2700 #define LCCR2 /* LCD Control Reg. 2 */ \
2701 (*((volatile Word *) io_p2v (_LCCR2)))
2702 #define LCCR3 /* LCD Control Reg. 3 */ \
2703 (*((volatile Word *) io_p2v (_LCCR3)))
2704 #endif /* LANGUAGE == C */
2705
2706 #define LCCR0_LEN 0x00000001 /* LCD ENable */
2707 #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
2708 #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
2709 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
2710 #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
2711 /* Select */
2712 #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
2713 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
2714 #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
2715 /* interrupt Mask (disable) */
2716 #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
2717 /* interrupt Mask (disable) */
2718 #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
2719 /* IUU, OOL, OUL, OOU, and OUU) */
2720 /* interrupt Mask (disable) */
2721 #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
2722 #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
2723 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
2724 #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
2725 #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
2726 #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
2727 #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
2728 /* display mode) */
2729 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
2730 /* display */
2731 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
2732 /* display */
2733 #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
2734 /* [Tmem] */
2735 #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
2736 /* [0..510 Tcpu] */ \
2737 ((Tcpu)/2 << FShft (LCCR0_PDD))
2738
2739 #define LCSR_LDD 0x00000001 /* LCD Disable Done */
2740 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
2741 #define LCSR_BER 0x00000004 /* Bus ERror */
2742 #define LCSR_ABC 0x00000008 /* AC Bias clock Count */
2743 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
2744 /* panel */
2745 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
2746 /* panel */
2747 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
2748 /* panel */
2749 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
2750 /* panel */
2751 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
2752 /* panel */
2753 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
2754 /* panel */
2755 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
2756 /* panel */
2757 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
2758 /* panel */
2759
2760 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
2761 #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
2762 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
2763 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
2764 /* pulse Width - 1 [Tpix] (L_LCLK) */
2765 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
2766 /* pulse Width [1..64 Tpix] */ \
2767 (((Tpix) - 1) << FShft (LCCR1_HSW))
2768 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2769 /* count - 1 [Tpix] */
2770 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2771 /* [1..256 Tpix] */ \
2772 (((Tpix) - 1) << FShft (LCCR1_ELW))
2773 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2774 /* Wait count - 1 [Tpix] */
2775 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2776 /* [1..256 Tpix] */ \
2777 (((Tpix) - 1) << FShft (LCCR1_BLW))
2778
2779 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2780 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
2781 (((Line) - 1) << FShft (LCCR2_LPP))
2782 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
2783 /* Width - 1 [Tln] (L_FCLK) */
2784 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
2785 /* Width [1..64 Tln] */ \
2786 (((Tln) - 1) << FShft (LCCR2_VSW))
2787 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2788 /* count [Tln] */
2789 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2790 /* [0..255 Tln] */ \
2791 ((Tln) << FShft (LCCR2_EFW))
2792 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2793 /* Wait count [Tln] */
2794 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2795 /* [0..255 Tln] */ \
2796 ((Tln) << FShft (LCCR2_BFW))
2797
2798 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
2799 /* [1..255] (L_PCLK) */
2800 /* fpix = fcpu/(2*(PCD + 2)) */
2801 /* Tpix = 2*(PCD + 2)*Tcpu */
2802 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
2803 (((Div) - 4)/2 << FShft (LCCR3_PCD))
2804 /* fpix = fcpu/(2*Floor (Div/2)) */
2805 /* Tpix = 2*Floor (Div/2)*Tcpu */
2806 #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
2807 (((Div) - 3)/2 << FShft (LCCR3_PCD))
2808 /* fpix = fcpu/(2*Ceil (Div/2)) */
2809 /* Tpix = 2*Ceil (Div/2)*Tcpu */
2810 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
2811 /* [Tln] (L_BIAS) */
2812 #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
2813 (((Div) - 2)/2 << FShft (LCCR3_ACB))
2814 /* fac = fln/(2*Floor (Div/2)) */
2815 /* Tac = 2*Floor (Div/2)*Tln */
2816 #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
2817 (((Div) - 1)/2 << FShft (LCCR3_ACB))
2818 /* fac = fln/(2*Ceil (Div/2)) */
2819 /* Tac = 2*Ceil (Div/2)*Tln */
2820 #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
2821 /* Interrupt */
2822 #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
2823 /* Off */ \
2824 (0 << FShft (LCCR3_API))
2825 #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
2826 /* [1..15] */ \
2827 ((Trans) << FShft (LCCR3_API))
2828 #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
2829 /* Polarity (L_FCLK) */
2830 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
2831 /* active High */
2832 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
2833 /* active Low */
2834 #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
2835 /* pulse Polarity (L_LCLK) */
2836 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
2837 /* pulse active High */
2838 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
2839 /* pulse active Low */
2840 #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
2841 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
2842 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
2843 #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
2844 /* active display mode) */
2845 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
2846 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
2847
2848
2849 #undef C
2850 #undef Assembly
2851
2852