File: /usr/src/linux/include/asm-arm/arch-sa1100/assabet.h
1 /*
2 * linux/include/asm-arm/arch-sa1100/assabet.h
3 *
4 * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
5 *
6 * This file contains the hardware specific definitions for Assabet
7 *
8 * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
9 * Definitions for Neponset added.
10 */
11
12 #ifndef __ASM_ARCH_HARDWARE_H
13 #error "include <asm/hardware.h> instead"
14 #endif
15
16
17 /* System Configuration Register flags */
18
19 #define SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
20 #define SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
21 #define SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
22 #define SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
23 #define SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
24 #define SCR_SA1111 (1<<9) /* Neponset (0 = present) */
25
26 #define SCR_INIT -1
27
28
29 /* Board Control Register */
30
31 #define BCR_BASE 0xf1000000
32 #define BCR (*(volatile unsigned int *)(BCR_BASE))
33
34 #define BCR_DB1110 \
35 (BCR_SPK_OFF | BCR_QMUTE | BCR_LED_GREEN | BCR_LED_RED | \
36 BCR_RS232EN | BCR_LCD_12RGB | BCR_IRDA_MD0)
37
38 #define BCR_DB1111 \
39 (BCR_SPK_OFF | BCR_QMUTE | BCR_LED_GREEN | BCR_LED_RED | \
40 BCR_RS232EN | BCR_LCD_12RGB | BCR_CF_BUS_OFF | BCR_STEREO_LB | \
41 BCR_IRDA_MD1 | BCR_CF_RST)
42
43 #define BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
44 #define BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
45 #define BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
46 #define BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
47 #define BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
48 #define BCR_IRDA_MD0 (1<<4) /* Range/Power select */
49 #define BCR_IRDA_MD1 (1<<5) /* Range/Power select */
50 #define BCR_STEREO_LB (1<<6) /* Stereo Loopback */
51 #define BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
52 #define BCR_AUDIO_ON (1<<8) /* Audio power on */
53 #define BCR_LIGHT_ON (1<<9) /* Backlight */
54 #define BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
55 #define BCR_LCD_ON (1<<11) /* LCD power on */
56 #define BCR_RS232EN (1<<12) /* RS232 transceiver enable */
57 #define BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
58 #define BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
59 #define BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
60 #define BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
61 #define BCR_COM_RTS (1<<17) /* COMport Request To Send */
62 #define BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
63 #define BCR_SMB_EN (1<<19) /* System management bus enable */
64 #define BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable */
65 #define BCR_QMUTE (1<<21) /* Quick Mute */
66 #define BCR_RAD_ON (1<<22) /* Radio Power On */
67 #define BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
68
69 #ifndef __ASSEMBLY__
70 extern unsigned long SCR_value;
71 extern unsigned long BCR_value;
72 #define BCR_set( x ) BCR = (BCR_value |= (x))
73 #define BCR_clear( x ) BCR = (BCR_value &= ~(x))
74 #endif
75
76 #define BSR_BASE 0xf1000000
77 #define BSR (*(volatile unsigned int*)(BSR_BASE))
78
79 #define BSR_RS232_VALID (1 << 24)
80 #define BSR_COM_DCD (1 << 25)
81 #define BSR_COM_CTS (1 << 26)
82 #define BSR_COM_DSR (1 << 27)
83 #define BSR_RAD_CTS (1 << 28)
84 #define BSR_RAD_DSR (1 << 29)
85 #define BSR_RAD_DCD (1 << 30)
86 #define BSR_RAD_RI (1 << 31)
87
88
89 /* GPIOs for which the generic definition doesn't say much */
90 #define GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
91 #define GPIO_L3_I2C_SDA GPIO_GPIO (15) /* L3 and SMB control ports */
92 #define GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
93 #define GPIO_L3_MODE GPIO_GPIO (17) /* L3 mode signal with LED */
94 #define GPIO_L3_I2C_SCL GPIO_GPIO (18) /* L3 and I2C control ports */
95 #define GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
96 #define GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
97 #define GPIO_MBGNT GPIO_GPIO (21) /* 1111 MBGNT */
98 #define GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
99 #define GPIO_MBREQ GPIO_GPIO (22) /* 1111 MBREQ */
100 #define GPIO_UCB1300_IRQ GPIO_GPIO (23) /* UCB GPIO and touchscreen */
101 #define GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
102 #define GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
103 #define GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
104 #define GPIO_NEP_IRQ GPIO_GPIO (25) /* Neponset IRQ */
105 #define GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
106 #define GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
107
108 #define IRQ_GPIO_CF_IRQ IRQ_GPIO21
109 #define IRQ_GPIO_CF_CD IRQ_GPIO22
110 #define IRQ_GPIO_MBREQ IRQ_GPIO22
111 #define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO23
112 #define IRQ_GPIO_CF_BVD2 IRQ_GPIO24
113 #define IRQ_GPIO_CF_BVD1 IRQ_GPIO25
114 #define IRQ_GPIO_NEP_IRQ IRQ_GPIO25
115
116
117 /*
118 * Neponset definitions:
119 */
120
121 #define SA1111_BASE (0x40000000)
122
123 #define NEPONSET_ETHERNET_IRQ MISC_IRQ0
124 #define NEPONSET_USAR_IRQ MISC_IRQ1
125
126 #define NEPONSET_CPLD_BASE (0x10000000)
127 #define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
128 #define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
129
130 #define _IRR 0x10000024 /* Interrupt Reason Register */
131 #define _AUD_CTL 0x100000c0 /* Audio controls (RW) */
132 #define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */
133 #define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */
134 #define _NCR_0 0x100000a0 /* Control Register (RW) */
135 #define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */
136 #define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */
137 #define _SWPK 0x10000020 /* Switch pack (RO) */
138 #define _WHOAMI 0x10000000 /* System ID Register (RO) */
139
140 #define _LEDS 0x10000010 /* LEDs [31:0] (WO) */
141
142 #ifndef __ASSEMBLY__
143
144 #define IRR (*((volatile u_char *) Nep_p2v(_IRR)))
145 #define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
146 #define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
147 #define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
148 #define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0)))
149 #define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
150 #define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
151 #define SWPK (*((volatile u_char *) Nep_p2v(_SWPK)))
152 #define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI)))
153
154 #define LEDS (*((volatile Word *) Nep_p2v(_LEDS)))
155
156 #endif
157
158 #define IRR_ETHERNET (1<<0)
159 #define IRR_USAR (1<<1)
160 #define IRR_SA1111 (1<<2)
161
162 #define AUD_SEL_1341 (1<<0)
163 #define AUD_MUTE_1341 (1<<1)
164
165 #define MDM_CTL0_RTS1 (1 << 0)
166 #define MDM_CTL0_DTR1 (1 << 1)
167 #define MDM_CTL0_RTS2 (1 << 2)
168 #define MDM_CTL0_DTR2 (1 << 3)
169
170 #define MDM_CTL1_CTS1 (1 << 0)
171 #define MDM_CTL1_DSR1 (1 << 1)
172 #define MDM_CTL1_DCD1 (1 << 2)
173 #define MDM_CTL1_CTS2 (1 << 3)
174 #define MDM_CTL1_DSR2 (1 << 4)
175 #define MDM_CTL1_DCD2 (1 << 5)
176
177 #define NCR_GP01_OFF (1<<0)
178 #define NCR_TP_PWR_EN (1<<1)
179 #define NCR_MS_PWR_EN (1<<2)
180 #define NCR_ENET_OSC_EN (1<<3)
181 #define NCR_SPI_KB_WK_UP (1<<4)
182 #define NCR_A0VPP (1<<5)
183 #define NCR_A1VPP (1<<6)
184
185 #ifndef __ASSEMBLY__
186 #define machine_has_neponset() ((SCR_value & SCR_SA1111) == 0)
187 #endif
188
189