1 #ifndef _ASM_CACHE_H 2 #define _ASM_CACHE_H 3 4 /* Etrax 100LX have 32-byte cache-lines. When we add support for future chips 5 * here should be a check for CPU type. 6 */ 7 8 #define L1_CACHE_BYTES 32 9 10 #endif /* _ASM_CACHE_H */ 11