File: /usr/src/linux/include/asm-cris/pgtable.h
1 /* CRIS pgtable.h - macros and functions to manipulate page tables
2 *
3 * HISTORY:
4 *
5 * $Log: pgtable.h,v $
6 * Revision 1.11 2001/04/04 14:38:36 bjornw
7 * Removed bad_pagetable handling and the _kernel functions
8 *
9 * Revision 1.10 2001/03/23 07:46:42 starvik
10 * Corrected according to review remarks
11 *
12 * Revision 1.9 2000/11/22 14:57:53 bjornw
13 * * extern inline -> static inline
14 * * include asm-generic/pgtable.h
15 *
16 * Revision 1.8 2000/11/21 13:56:16 bjornw
17 * Use CONFIG_CRIS_LOW_MAP for the low VM map instead of explicit CPU type
18 *
19 * Revision 1.7 2000/10/06 15:05:32 bjornw
20 * VMALLOC area changed in memory mapping change
21 *
22 * Revision 1.6 2000/10/04 16:59:14 bjornw
23 * Changed comments
24 *
25 * Revision 1.5 2000/09/13 14:39:53 bjornw
26 * New macros
27 *
28 * Revision 1.4 2000/08/17 15:38:48 bjornw
29 * 2.4.0-test6 modifications:
30 * * flush_dcache_page added
31 * * MAP_NR removed
32 * * virt_to_page added
33 *
34 * Plus some comments and type-clarifications.
35 *
36 * Revision 1.3 2000/08/15 16:33:35 bjornw
37 * pmd_bad should recognize both kernel and user page-tables
38 *
39 * Revision 1.2 2000/07/10 17:06:01 bjornw
40 * Fixed warnings
41 *
42 * Revision 1.1.1.1 2000/07/10 16:32:31 bjornw
43 * CRIS architecture, working draft
44 *
45 *
46 * Revision 1.11 2000/05/29 14:55:56 bjornw
47 * Small tweaks of pte_mk routines
48 *
49 * Revision 1.10 2000/01/27 01:49:06 bjornw
50 * * Ooops. The physical frame number in a PTE entry needs to point to the
51 * DRAM directly, not to what the kernel thinks is DRAM (due to KSEG mapping).
52 * Hence we need to strip bit 31 so 0xcXXXXXXX -> 0x4XXXXXXX.
53 *
54 * Revision 1.9 2000/01/26 16:25:50 bjornw
55 * Fixed PAGE_KERNEL bits
56 *
57 * Revision 1.8 2000/01/23 22:53:22 bjornw
58 * Correct flush_tlb_* macros and externs
59 *
60 * Revision 1.7 2000/01/18 16:22:55 bjornw
61 * Use PAGE_MASK instead of PFN_MASK.
62 *
63 * Revision 1.6 2000/01/17 02:42:53 bjornw
64 * Added the pmd_set macro.
65 *
66 * Revision 1.5 2000/01/16 19:53:42 bjornw
67 * Removed VMALLOC_OFFSET. Changed definitions of swapper_pg_dir and zero_page.
68 *
69 * Revision 1.4 2000/01/14 16:38:20 bjornw
70 * PAGE_DIRTY -> PAGE_SILENT_WRITE, removed PAGE_COW from PAGE_COPY.
71 *
72 * Revision 1.3 1999/12/04 20:12:21 bjornw
73 * * PTE bits have moved to asm/mmu.h
74 * * Fixed definitions of the higher level page protection bits
75 * * Added the pte_* functions, including dirty/accessed SW simulation
76 * (these are exactly the same as for the MIPS port)
77 *
78 * Revision 1.2 1999/12/04 00:41:54 bjornw
79 * * Fixed page table offsets, sizes and shifts
80 * * Removed reference to i386 SMP stuff
81 * * Added stray comments about Linux/CRIS mm design
82 * * Include asm/mmu.h which will contain MMU details
83 *
84 * Revision 1.1 1999/12/03 15:04:02 bjornw
85 * Copied from include/asm-etrax100. For the new CRIS architecture.
86 */
87
88 #ifndef _CRIS_PGTABLE_H
89 #define _CRIS_PGTABLE_H
90
91 #include <linux/config.h>
92 #include <asm/mmu.h>
93
94 /*
95 * The Linux memory management assumes a three-level page table setup. On
96 * CRIS, we use that, but "fold" the mid level into the top-level page
97 * table. Since the MMU TLB is software loaded through an interrupt, it
98 * supports any page table structure, so we could have used a three-level
99 * setup, but for the amounts of memory we normally use, a two-level is
100 * probably more efficient.
101 *
102 * This file contains the functions and defines necessary to modify and use
103 * the CRIS page table tree.
104 */
105
106 /* The cache doesn't need to be flushed when TLB entries change because
107 * the cache is mapped to physical memory, not virtual memory
108 */
109 #define flush_cache_all() do { } while (0)
110 #define flush_cache_mm(mm) do { } while (0)
111 #define flush_cache_range(mm, start, end) do { } while (0)
112 #define flush_cache_page(vma, vmaddr) do { } while (0)
113 #define flush_page_to_ram(page) do { } while (0)
114 #define flush_dcache_page(page) do { } while (0)
115 #define flush_icache_range(start, end) do { } while (0)
116 #define flush_icache_page(vma,pg) do { } while (0)
117
118 /*
119 * TLB flushing (implemented in arch/cris/mm/tlb.c):
120 *
121 * - flush_tlb() flushes the current mm struct TLBs
122 * - flush_tlb_all() flushes all processes TLBs
123 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
124 * - flush_tlb_page(vma, vmaddr) flushes one page
125 * - flush_tlb_range(mm, start, end) flushes a range of pages
126 *
127 */
128
129 extern void flush_tlb_all(void);
130 extern void flush_tlb_mm(struct mm_struct *mm);
131 extern void flush_tlb_page(struct vm_area_struct *vma,
132 unsigned long addr);
133 extern void flush_tlb_range(struct mm_struct *mm,
134 unsigned long start,
135 unsigned long end);
136
137 static inline void flush_tlb_pgtables(struct mm_struct *mm,
138 unsigned long start, unsigned long end)
139 {
140 /* CRIS does not keep any page table caches in TLB */
141 }
142
143
144 static inline void flush_tlb(void)
145 {
146 flush_tlb_mm(current->mm);
147 }
148
149 /* Certain architectures need to do special things when pte's
150 * within a page table are directly modified. Thus, the following
151 * hook is made available.
152 */
153 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
154 /*
155 * (pmds are folded into pgds so this doesnt get actually called,
156 * but the define is needed for a generic inline function.)
157 */
158 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
159 #define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
160
161 /* PMD_SHIFT determines the size of the area a second-level page table can
162 * map. It is equal to the page size times the number of PTE's that fit in
163 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
164 */
165
166 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
167 #define PMD_SIZE (1UL << PMD_SHIFT)
168 #define PMD_MASK (~(PMD_SIZE-1))
169
170 /* PGDIR_SHIFT determines what a third-level page table entry can map.
171 * Since we fold into a two-level structure, this is the same as PMD_SHIFT.
172 */
173
174 #define PGDIR_SHIFT PMD_SHIFT
175 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
176 #define PGDIR_MASK (~(PGDIR_SIZE-1))
177
178 /*
179 * entries per page directory level: we use a two-level, so
180 * we don't really have any PMD directory physically.
181 * pointers are 4 bytes so we can use the page size and
182 * divide it by 4 (shift by 2).
183 */
184 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
185 #define PTRS_PER_PMD 1
186 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
187
188 /* calculate how many PGD entries a user-level program can use
189 * the first mappable virtual address is 0
190 * (TASK_SIZE is the maximum virtual address space)
191 */
192
193 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
194 #define FIRST_USER_PGD_NR 0
195
196 /*
197 * Kernels own virtual memory area.
198 */
199
200 #ifdef CONFIG_CRIS_LOW_MAP
201 #define VMALLOC_START KSEG_7
202 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
203 #define VMALLOC_END KSEG_8
204 #else
205 #define VMALLOC_START KSEG_D
206 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
207 #define VMALLOC_END KSEG_E
208 #endif
209
210 /* Define some higher level generic page attributes. The PTE bits are
211 * defined in asm-cris/mmu.h, and these are just combinations of those.
212 */
213
214 #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
215 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
216
217 #define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
218 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_SILENT_WRITE)
219
220 #define PAGE_NONE __pgprot(_PAGE_PRESENT | __READABLE)
221 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
222 _PAGE_ACCESSED)
223 #define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW
224 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
225 #define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
226 _PAGE_PRESENT | __READABLE | __WRITEABLE)
227 #define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
228
229 /*
230 * CRIS can't do page protection for execute, and considers read the same.
231 * Also, write permissions imply read permissions. This is the closest we can
232 * get..
233 */
234
235 #define __P000 PAGE_NONE
236 #define __P001 PAGE_READONLY
237 #define __P010 PAGE_COPY
238 #define __P011 PAGE_COPY
239 #define __P100 PAGE_READONLY
240 #define __P101 PAGE_READONLY
241 #define __P110 PAGE_COPY
242 #define __P111 PAGE_COPY
243
244 #define __S000 PAGE_NONE
245 #define __S001 PAGE_READONLY
246 #define __S010 PAGE_SHARED
247 #define __S011 PAGE_SHARED
248 #define __S100 PAGE_READONLY
249 #define __S101 PAGE_READONLY
250 #define __S110 PAGE_SHARED
251 #define __S111 PAGE_SHARED
252
253 /* zero page used for uninitialized stuff */
254 extern unsigned long empty_zero_page;
255 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
256
257 /* number of bits that fit into a memory pointer */
258 #define BITS_PER_PTR (8*sizeof(unsigned long))
259
260 /* to align the pointer to a pointer address */
261 #define PTR_MASK (~(sizeof(void*)-1))
262
263 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
264 /* 64-bit machines, beware! SRB. */
265 #define SIZEOF_PTR_LOG2 2
266
267 /* to find an entry in a page-table */
268 #define PAGE_PTR(address) \
269 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
270
271 /* to set the page-dir */
272 #define SET_PAGE_DIR(tsk,pgdir)
273
274 #define pte_none(x) (!pte_val(x))
275 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
276 #define pte_clear(xp) do { pte_val(*(xp)) = 0; } while (0)
277
278 #define pmd_none(x) (!pmd_val(x))
279 /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad
280 * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
281 */
282 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
283 #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
284 #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
285
286 /*
287 * The "pgd_xxx()" functions here are trivial for a folded two-level
288 * setup: the pgd is never bad, and a pmd always exists (as it's folded
289 * into the pgd entry)
290 */
291 static inline int pgd_none(pgd_t pgd) { return 0; }
292 static inline int pgd_bad(pgd_t pgd) { return 0; }
293 static inline int pgd_present(pgd_t pgd) { return 1; }
294 static inline void pgd_clear(pgd_t * pgdp) { }
295
296 /*
297 * The following only work if pte_present() is true.
298 * Undefined behaviour if not..
299 */
300
301 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
302 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
303 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
304 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
305 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
306
307 static inline pte_t pte_wrprotect(pte_t pte)
308 {
309 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
310 return pte;
311 }
312
313 static inline pte_t pte_rdprotect(pte_t pte)
314 {
315 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
316 return pte;
317 }
318
319 static inline pte_t pte_exprotect(pte_t pte)
320 {
321 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
322 return pte;
323 }
324
325 static inline pte_t pte_mkclean(pte_t pte)
326 {
327 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
328 return pte;
329 }
330
331 static inline pte_t pte_mkold(pte_t pte)
332 {
333 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
334 return pte;
335 }
336
337 static inline pte_t pte_mkwrite(pte_t pte)
338 {
339 pte_val(pte) |= _PAGE_WRITE;
340 if (pte_val(pte) & _PAGE_MODIFIED)
341 pte_val(pte) |= _PAGE_SILENT_WRITE;
342 return pte;
343 }
344
345 static inline pte_t pte_mkread(pte_t pte)
346 {
347 pte_val(pte) |= _PAGE_READ;
348 if (pte_val(pte) & _PAGE_ACCESSED)
349 pte_val(pte) |= _PAGE_SILENT_READ;
350 return pte;
351 }
352
353 static inline pte_t pte_mkexec(pte_t pte)
354 {
355 pte_val(pte) |= _PAGE_READ;
356 if (pte_val(pte) & _PAGE_ACCESSED)
357 pte_val(pte) |= _PAGE_SILENT_READ;
358 return pte;
359 }
360
361 static inline pte_t pte_mkdirty(pte_t pte)
362 {
363 pte_val(pte) |= _PAGE_MODIFIED;
364 if (pte_val(pte) & _PAGE_WRITE)
365 pte_val(pte) |= _PAGE_SILENT_WRITE;
366 return pte;
367 }
368
369 static inline pte_t pte_mkyoung(pte_t pte)
370 {
371 pte_val(pte) |= _PAGE_ACCESSED;
372 if (pte_val(pte) & _PAGE_READ)
373 {
374 pte_val(pte) |= _PAGE_SILENT_READ;
375 if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
376 (_PAGE_WRITE | _PAGE_MODIFIED))
377 pte_val(pte) |= _PAGE_SILENT_WRITE;
378 }
379 return pte;
380 }
381
382 /*
383 * Conversion functions: convert a page and protection to a page entry,
384 * and a page entry and page directory to the page they refer to.
385 */
386
387 /* What actually goes as arguments to the various functions is less than
388 * obvious, but a rule of thumb is that struct page's goes as struct page *,
389 * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
390 * addresses (the 0xc0xxxxxx's) goes as void *'s.
391 */
392
393 static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
394 {
395 pte_t pte;
396 /* the PTE needs a physical address */
397 pte_val(pte) = __pa(page) | pgprot_val(pgprot);
398 return pte;
399 }
400
401 #define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
402
403 #define mk_pte_phys(physpage, pgprot) \
404 ({ \
405 pte_t __pte; \
406 \
407 pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
408 __pte; \
409 })
410
411 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
412 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
413
414
415 /* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
416 * __pte_page(pte_val) refers to the "virtual" DRAM interval
417 * pte_pagenr refers to the page-number counted starting from the virtual DRAM start
418 */
419
420 static inline unsigned long __pte_page(pte_t pte)
421 {
422 /* the PTE contains a physical address */
423 return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
424 }
425
426 #define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
427
428 /* permanent address of a page */
429
430 #define page_address(page) ((page)->virtual)
431 #define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
432 #define pte_page(pte) (mem_map+pte_pagenr(pte))
433
434 /* only the pte's themselves need to point to physical DRAM (see above)
435 * the pagetable links are purely handled within the kernel SW and thus
436 * don't need the __pa and __va transformations.
437 */
438
439 static inline unsigned long pmd_page(pmd_t pmd)
440 { return pmd_val(pmd) & PAGE_MASK; }
441
442 static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
443 { pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }
444
445 /* to find an entry in a page-table-directory. */
446 #define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
447
448 /* to find an entry in a page-table-directory */
449 static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
450 {
451 return mm->pgd + pgd_index(address);
452 }
453
454 /* to find an entry in a kernel page-table-directory */
455 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
456
457 /* Find an entry in the second-level page table.. */
458 static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
459 {
460 return (pmd_t *) dir;
461 }
462
463 /* Find an entry in the third-level page table.. */
464 static inline pte_t * pte_offset(pmd_t * dir, unsigned long address)
465 {
466 return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
467 }
468
469 #define pte_ERROR(e) \
470 printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
471 #define pmd_ERROR(e) \
472 printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
473 #define pgd_ERROR(e) \
474 printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
475
476 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
477
478 /*
479 * CRIS doesn't have any external MMU info: the kernel page
480 * tables contain all the necessary information.
481 *
482 * Actually I am not sure on what this could be used for.
483 */
484 static inline void update_mmu_cache(struct vm_area_struct * vma,
485 unsigned long address, pte_t pte)
486 {
487 }
488
489 /* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
490 /* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
491
492 #define SWP_TYPE(x) (((x).val >> 5) & 0x7f)
493 #define SWP_OFFSET(x) ((x).val >> 12)
494 #define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
495 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
496 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
497
498 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
499 #define PageSkip(page) (0)
500 #define kern_addr_valid(addr) (1)
501
502 #include <asm-generic/pgtable.h>
503
504 #endif /* _CRIS_PGTABLE_H */
505