File: /usr/src/linux/include/asm-ia64/processor.h
1 #ifndef _ASM_IA64_PROCESSOR_H
2 #define _ASM_IA64_PROCESSOR_H
3
4 /*
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
6 * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1998-2001 Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
15
16 #include <linux/config.h>
17
18 #include <asm/ptrace.h>
19 #include <asm/kregs.h>
20 #include <asm/system.h>
21 #include <asm/types.h>
22
23 #define IA64_NUM_DBG_REGS 8
24 /*
25 * Limits for PMC and PMD are set to less than maximum architected values
26 * but should be sufficient for a while
27 */
28 #define IA64_NUM_PMC_REGS 32
29 #define IA64_NUM_PMD_REGS 32
30 #define IA64_NUM_PMD_COUNTERS 4
31
32 #define DEFAULT_MAP_BASE 0x2000000000000000
33 #define DEFAULT_TASK_SIZE 0xa000000000000000
34
35 /*
36 * TASK_SIZE really is a mis-named. It really is the maximum user
37 * space address (plus one). On IA-64, there are five regions of 2TB
38 * each (assuming 8KB page size), for a total of 8TB of user virtual
39 * address space.
40 */
41 #define TASK_SIZE (current->thread.task_size)
42
43 /*
44 * This decides where the kernel will search for a free chunk of vm
45 * space during mmap's.
46 */
47 #define TASK_UNMAPPED_BASE (current->thread.map_base)
48
49 /*
50 * Bus types
51 */
52 #define EISA_bus 0
53 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
54 #define MCA_bus 0
55 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
56
57 /* Processor status register bits: */
58 #define IA64_PSR_BE_BIT 1
59 #define IA64_PSR_UP_BIT 2
60 #define IA64_PSR_AC_BIT 3
61 #define IA64_PSR_MFL_BIT 4
62 #define IA64_PSR_MFH_BIT 5
63 #define IA64_PSR_IC_BIT 13
64 #define IA64_PSR_I_BIT 14
65 #define IA64_PSR_PK_BIT 15
66 #define IA64_PSR_DT_BIT 17
67 #define IA64_PSR_DFL_BIT 18
68 #define IA64_PSR_DFH_BIT 19
69 #define IA64_PSR_SP_BIT 20
70 #define IA64_PSR_PP_BIT 21
71 #define IA64_PSR_DI_BIT 22
72 #define IA64_PSR_SI_BIT 23
73 #define IA64_PSR_DB_BIT 24
74 #define IA64_PSR_LP_BIT 25
75 #define IA64_PSR_TB_BIT 26
76 #define IA64_PSR_RT_BIT 27
77 /* The following are not affected by save_flags()/restore_flags(): */
78 #define IA64_PSR_CPL0_BIT 32
79 #define IA64_PSR_CPL1_BIT 33
80 #define IA64_PSR_IS_BIT 34
81 #define IA64_PSR_MC_BIT 35
82 #define IA64_PSR_IT_BIT 36
83 #define IA64_PSR_ID_BIT 37
84 #define IA64_PSR_DA_BIT 38
85 #define IA64_PSR_DD_BIT 39
86 #define IA64_PSR_SS_BIT 40
87 #define IA64_PSR_RI_BIT 41
88 #define IA64_PSR_ED_BIT 43
89 #define IA64_PSR_BN_BIT 44
90
91 #define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
92 #define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
93 #define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
94 #define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
95 #define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
96 #define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
97 #define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
98 #define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
99 #define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
100 #define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
101 #define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
102 #define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
103 #define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
104 #define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
105 #define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
106 #define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
107 #define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
108 #define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
109 #define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
110 /* The following are not affected by save_flags()/restore_flags(): */
111 #define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
112 #define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
113 #define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
114 #define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
115 #define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
116 #define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
117 #define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
118 #define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
119 #define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
120 #define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
121
122 /* User mask bits: */
123 #define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
124
125 /* Default Control Register */
126 #define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
127 #define IA64_DCR_BE_BIT 1 /* big-endian default */
128 #define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
129 #define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
130 #define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
131 #define IA64_DCR_DK_BIT 10 /* defer key miss faults */
132 #define IA64_DCR_DX_BIT 11 /* defer key permission faults */
133 #define IA64_DCR_DR_BIT 12 /* defer access right faults */
134 #define IA64_DCR_DA_BIT 13 /* defer access bit faults */
135 #define IA64_DCR_DD_BIT 14 /* defer debug faults */
136
137 #define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
138 #define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
139 #define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
140 #define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
141 #define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
142 #define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
143 #define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
144 #define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
145 #define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
146 #define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
147
148 /* Interrupt Status Register */
149 #define IA64_ISR_X_BIT 32 /* execute access */
150 #define IA64_ISR_W_BIT 33 /* write access */
151 #define IA64_ISR_R_BIT 34 /* read access */
152 #define IA64_ISR_NA_BIT 35 /* non-access */
153 #define IA64_ISR_SP_BIT 36 /* speculative load exception */
154 #define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
155 #define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
156
157 #define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
158 #define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
159 #define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
160 #define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
161 #define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
162 #define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
163 #define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
164
165 #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
166 #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
167 #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
168 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
169 #define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
170 #define IA64_THREAD_KRBS_SYNCED (__IA64_UL(1) << 5) /* krbs synced with process vm? */
171 #define IA64_KERNEL_DEATH (__IA64_UL(1) << 63) /* see die_if_kernel()... */
172
173 #define IA64_THREAD_UAC_SHIFT 3
174 #define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
175
176
177 /*
178 * This shift should be large enough to be able to represent
179 * 1000000/itc_freq with good accuracy while being small enough to fit
180 * 1000000<<IA64_USEC_PER_CYC_SHIFT in 64 bits.
181 */
182 #define IA64_USEC_PER_CYC_SHIFT 41
183
184 #ifndef __ASSEMBLY__
185
186 #include <linux/threads.h>
187
188 #include <asm/fpu.h>
189 #include <asm/offsets.h>
190 #include <asm/page.h>
191 #include <asm/rse.h>
192 #include <asm/unwind.h>
193
194 /* like above but expressed as bitfields for more efficient access: */
195 struct ia64_psr {
196 __u64 reserved0 : 1;
197 __u64 be : 1;
198 __u64 up : 1;
199 __u64 ac : 1;
200 __u64 mfl : 1;
201 __u64 mfh : 1;
202 __u64 reserved1 : 7;
203 __u64 ic : 1;
204 __u64 i : 1;
205 __u64 pk : 1;
206 __u64 reserved2 : 1;
207 __u64 dt : 1;
208 __u64 dfl : 1;
209 __u64 dfh : 1;
210 __u64 sp : 1;
211 __u64 pp : 1;
212 __u64 di : 1;
213 __u64 si : 1;
214 __u64 db : 1;
215 __u64 lp : 1;
216 __u64 tb : 1;
217 __u64 rt : 1;
218 __u64 reserved3 : 4;
219 __u64 cpl : 2;
220 __u64 is : 1;
221 __u64 mc : 1;
222 __u64 it : 1;
223 __u64 id : 1;
224 __u64 da : 1;
225 __u64 dd : 1;
226 __u64 ss : 1;
227 __u64 ri : 2;
228 __u64 ed : 1;
229 __u64 bn : 1;
230 __u64 reserved4 : 19;
231 };
232
233 /*
234 * CPU type, hardware bug flags, and per-CPU state. Frequently used
235 * state comes earlier:
236 */
237 struct cpuinfo_ia64 {
238 /* irq_stat must be 64-bit aligned */
239 union {
240 struct {
241 __u32 irq_count;
242 __u32 bh_count;
243 } f;
244 __u64 irq_and_bh_counts;
245 } irq_stat;
246 __u32 softirq_pending;
247 __u32 phys_stacked_size_p8; /* size of physical stacked registers + 8 */
248 __u64 itm_delta; /* # of clock cycles between clock ticks */
249 __u64 itm_next; /* interval timer mask value to use for next clock tick */
250 __u64 *pgd_quick;
251 __u64 *pmd_quick;
252 __u64 *pte_quick;
253 __u64 pgtable_cache_sz;
254 /* CPUID-derived information: */
255 __u64 ppn;
256 __u64 features;
257 __u8 number;
258 __u8 revision;
259 __u8 model;
260 __u8 family;
261 __u8 archrev;
262 char vendor[16];
263 __u64 itc_freq; /* frequency of ITC counter */
264 __u64 proc_freq; /* frequency of processor */
265 __u64 cyc_per_usec; /* itc_freq/1000000 */
266 __u64 usec_per_cyc; /* 2^IA64_USEC_PER_CYC_SHIFT*1000000/itc_freq */
267 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
268 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
269 __u64 ptce_base;
270 __u32 ptce_count[2];
271 __u32 ptce_stride[2];
272 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
273 #ifdef CONFIG_SMP
274 __u64 loops_per_jiffy;
275 __u64 ipi_count;
276 __u64 prof_counter;
277 __u64 prof_multiplier;
278 __u64 ipi_operation;
279 #endif
280 #ifdef CONFIG_NUMA
281 struct cpuinfo_ia64 *cpu_data[NR_CPUS];
282 #endif
283 } __attribute__ ((aligned (PAGE_SIZE))) ;
284
285 /*
286 * The "local" data pointer. It points to the per-CPU data of the currently executing
287 * CPU, much like "current" points to the per-task data of the currently executing task.
288 */
289 #define local_cpu_data ((struct cpuinfo_ia64 *) PERCPU_ADDR)
290
291 /*
292 * On NUMA systems, cpu_data for each cpu is allocated during cpu_init() & is allocated on
293 * the node that contains the cpu. This minimizes off-node memory references. cpu_data
294 * for each cpu contains an array of pointers to the cpu_data structures of each of the
295 * other cpus.
296 *
297 * On non-NUMA systems, cpu_data is a static array allocated at compile time. References
298 * to the cpu_data of another cpu is done by direct references to the appropriate entry of
299 * the array.
300 */
301 #ifdef CONFIG_NUMA
302 # define cpu_data(cpu) local_cpu_data->cpu_data_ptrs[cpu]
303 #else
304 extern struct cpuinfo_ia64 _cpu_data[NR_CPUS];
305 # define cpu_data(cpu) (&_cpu_data[cpu])
306 #endif
307
308 extern void identify_cpu (struct cpuinfo_ia64 *);
309 extern void print_cpu_info (struct cpuinfo_ia64 *);
310
311 typedef struct {
312 unsigned long seg;
313 } mm_segment_t;
314
315 #define SET_UNALIGN_CTL(task,value) \
316 ({ \
317 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
318 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
319 0; \
320 })
321 #define GET_UNALIGN_CTL(task,addr) \
322 ({ \
323 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
324 (int *) (addr)); \
325 })
326
327 struct siginfo;
328
329 struct thread_struct {
330 __u64 ksp; /* kernel stack pointer */
331 unsigned long flags; /* various flags */
332 __u64 map_base; /* base address for get_unmapped_area() */
333 __u64 task_size; /* limit for task size */
334 struct siginfo *siginfo; /* current siginfo struct for ptrace() */
335
336 #ifdef CONFIG_IA32_SUPPORT
337 __u64 eflag; /* IA32 EFLAGS reg */
338 __u64 fsr; /* IA32 floating pt status reg */
339 __u64 fcr; /* IA32 floating pt control reg */
340 __u64 fir; /* IA32 fp except. instr. reg */
341 __u64 fdr; /* IA32 fp except. data reg */
342 __u64 csd; /* IA32 code selector descriptor */
343 __u64 ssd; /* IA32 stack selector descriptor */
344 __u64 tssd; /* IA32 TSS descriptor */
345 __u64 old_iob; /* old IOBase value */
346 union {
347 __u64 sigmask; /* aligned mask for sigsuspend scall */
348 } un;
349 # define INIT_THREAD_IA32 0, 0, 0x17800000037fULL, 0, 0, 0, 0, 0, 0, {0},
350 #else
351 # define INIT_THREAD_IA32
352 #endif /* CONFIG_IA32_SUPPORT */
353 #ifdef CONFIG_PERFMON
354 __u64 pmc[IA64_NUM_PMC_REGS];
355 __u64 pmd[IA64_NUM_PMD_REGS];
356 unsigned long pfm_pend_notify; /* non-zero if we need to notify and block */
357 void *pfm_context; /* pointer to detailed PMU context */
358 # define INIT_THREAD_PM {0, }, {0, }, 0, 0,
359 #else
360 # define INIT_THREAD_PM
361 #endif
362 __u64 dbr[IA64_NUM_DBG_REGS];
363 __u64 ibr[IA64_NUM_DBG_REGS];
364 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
365 };
366
367 #define INIT_THREAD { \
368 0, /* ksp */ \
369 0, /* flags */ \
370 DEFAULT_MAP_BASE, /* map_base */ \
371 DEFAULT_TASK_SIZE, /* task_size */ \
372 0, /* siginfo */ \
373 INIT_THREAD_IA32 \
374 INIT_THREAD_PM \
375 {0, }, /* dbr */ \
376 {0, }, /* ibr */ \
377 {{{{0}}}, } /* fph */ \
378 }
379
380 #define start_thread(regs,new_ip,new_sp) do { \
381 set_fs(USER_DS); \
382 ia64_psr(regs)->dfh = 1; /* disable fph */ \
383 ia64_psr(regs)->mfh = 0; /* clear mfh */ \
384 ia64_psr(regs)->cpl = 3; /* set user mode */ \
385 ia64_psr(regs)->ri = 0; /* clear return slot number */ \
386 ia64_psr(regs)->is = 0; /* IA-64 instruction set */ \
387 regs->cr_iip = new_ip; \
388 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
389 regs->ar_rnat = 0; \
390 regs->ar_bspstore = IA64_RBS_BOT; \
391 regs->ar_fpsr = FPSR_DEFAULT; \
392 regs->loadrs = 0; \
393 regs->r8 = current->mm->dumpable; /* set "don't zap registers" flag */ \
394 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
395 if (!__builtin_expect (current->mm->dumpable, 1)) { \
396 /* \
397 * Zap scratch regs to avoid leaking bits between processes with different \
398 * uid/privileges. \
399 */ \
400 regs->ar_pfs = 0; \
401 regs->pr = 0; \
402 /* \
403 * XXX fix me: everything below can go away once we stop preserving scratch \
404 * regs on a system call. \
405 */ \
406 regs->b6 = 0; \
407 regs->r1 = 0; regs->r2 = 0; regs->r3 = 0; \
408 regs->r13 = 0; regs->r14 = 0; regs->r15 = 0; \
409 regs->r9 = 0; regs->r11 = 0; \
410 regs->r16 = 0; regs->r17 = 0; regs->r18 = 0; regs->r19 = 0; \
411 regs->r20 = 0; regs->r21 = 0; regs->r22 = 0; regs->r23 = 0; \
412 regs->r24 = 0; regs->r25 = 0; regs->r26 = 0; regs->r27 = 0; \
413 regs->r28 = 0; regs->r29 = 0; regs->r30 = 0; regs->r31 = 0; \
414 regs->ar_ccv = 0; \
415 regs->b0 = 0; regs->b7 = 0; \
416 regs->f6.u.bits[0] = 0; regs->f6.u.bits[1] = 0; \
417 regs->f7.u.bits[0] = 0; regs->f7.u.bits[1] = 0; \
418 regs->f8.u.bits[0] = 0; regs->f8.u.bits[1] = 0; \
419 regs->f9.u.bits[0] = 0; regs->f9.u.bits[1] = 0; \
420 } \
421 } while (0)
422
423 /* Forward declarations, a strange C thing... */
424 struct mm_struct;
425 struct task_struct;
426
427 /*
428 * Free all resources held by a thread. This is called after the
429 * parent of DEAD_TASK has collected the exist status of the task via
430 * wait().
431 */
432 #ifdef CONFIG_PERFMON
433 extern void release_thread (struct task_struct *task);
434 #else
435 # define release_thread(dead_task)
436 #endif
437
438 /*
439 * This is the mechanism for creating a new kernel thread.
440 *
441 * NOTE 1: Only a kernel-only process (ie the swapper or direct
442 * descendants who haven't done an "execve()") should use this: it
443 * will work within a system call from a "real" process, but the
444 * process memory space will not be free'd until both the parent and
445 * the child have exited.
446 *
447 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
448 * into trouble in init/main.c when the child thread returns to
449 * do_basic_setup() and the timing is such that free_initmem() has
450 * been called already.
451 */
452 extern int kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
453
454 /* Copy and release all segment info associated with a VM */
455 #define copy_segments(tsk, mm) do { } while (0)
456 #define release_segments(mm) do { } while (0)
457
458 /* Get wait channel for task P. */
459 extern unsigned long get_wchan (struct task_struct *p);
460
461 /* Return instruction pointer of blocked task TSK. */
462 #define KSTK_EIP(tsk) \
463 ({ \
464 struct pt_regs *_regs = ia64_task_regs(tsk); \
465 _regs->cr_iip + ia64_psr(_regs)->ri; \
466 })
467
468 /* Return stack pointer of blocked task TSK. */
469 #define KSTK_ESP(tsk) ((tsk)->thread.ksp)
470
471 static inline unsigned long
472 ia64_get_kr (unsigned long regnum)
473 {
474 unsigned long r;
475
476 switch (regnum) {
477 case 0: asm volatile ("mov %0=ar.k0" : "=r"(r)); break;
478 case 1: asm volatile ("mov %0=ar.k1" : "=r"(r)); break;
479 case 2: asm volatile ("mov %0=ar.k2" : "=r"(r)); break;
480 case 3: asm volatile ("mov %0=ar.k3" : "=r"(r)); break;
481 case 4: asm volatile ("mov %0=ar.k4" : "=r"(r)); break;
482 case 5: asm volatile ("mov %0=ar.k5" : "=r"(r)); break;
483 case 6: asm volatile ("mov %0=ar.k6" : "=r"(r)); break;
484 case 7: asm volatile ("mov %0=ar.k7" : "=r"(r)); break;
485 }
486 return r;
487 }
488
489 static inline void
490 ia64_set_kr (unsigned long regnum, unsigned long r)
491 {
492 switch (regnum) {
493 case 0: asm volatile ("mov ar.k0=%0" :: "r"(r)); break;
494 case 1: asm volatile ("mov ar.k1=%0" :: "r"(r)); break;
495 case 2: asm volatile ("mov ar.k2=%0" :: "r"(r)); break;
496 case 3: asm volatile ("mov ar.k3=%0" :: "r"(r)); break;
497 case 4: asm volatile ("mov ar.k4=%0" :: "r"(r)); break;
498 case 5: asm volatile ("mov ar.k5=%0" :: "r"(r)); break;
499 case 6: asm volatile ("mov ar.k6=%0" :: "r"(r)); break;
500 case 7: asm volatile ("mov ar.k7=%0" :: "r"(r)); break;
501 }
502 }
503
504 #ifndef CONFIG_SMP
505
506 static inline struct task_struct *
507 ia64_get_fpu_owner (void)
508 {
509 return (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER);
510 }
511
512 static inline void
513 ia64_set_fpu_owner (struct task_struct *t)
514 {
515 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) t);
516 }
517
518 #endif /* !CONFIG_SMP */
519
520 extern void __ia64_init_fpu (void);
521 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
522 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
523 extern void ia64_save_debug_regs (unsigned long *save_area);
524 extern void ia64_load_debug_regs (unsigned long *save_area);
525
526 #ifdef CONFIG_IA32_SUPPORT
527 extern void ia32_save_state (struct task_struct *task);
528 extern void ia32_load_state (struct task_struct *task);
529 #endif
530
531 #ifdef CONFIG_PERFMON
532 extern void ia64_save_pm_regs (struct task_struct *task);
533 extern void ia64_load_pm_regs (struct task_struct *task);
534 #endif
535
536 #define ia64_fph_enable() asm volatile (";; rsm psr.dfh;; srlz.d;;" ::: "memory");
537 #define ia64_fph_disable() asm volatile (";; ssm psr.dfh;; srlz.d;;" ::: "memory");
538
539 /* load fp 0.0 into fph */
540 static inline void
541 ia64_init_fpu (void) {
542 ia64_fph_enable();
543 __ia64_init_fpu();
544 ia64_fph_disable();
545 }
546
547 /* save f32-f127 at FPH */
548 static inline void
549 ia64_save_fpu (struct ia64_fpreg *fph) {
550 ia64_fph_enable();
551 __ia64_save_fpu(fph);
552 ia64_fph_disable();
553 }
554
555 /* load f32-f127 from FPH */
556 static inline void
557 ia64_load_fpu (struct ia64_fpreg *fph) {
558 ia64_fph_enable();
559 __ia64_load_fpu(fph);
560 ia64_fph_disable();
561 }
562
563 static inline void
564 ia64_fc (void *addr)
565 {
566 asm volatile ("fc %0" :: "r"(addr) : "memory");
567 }
568
569 static inline void
570 ia64_sync_i (void)
571 {
572 asm volatile (";; sync.i" ::: "memory");
573 }
574
575 static inline void
576 ia64_srlz_i (void)
577 {
578 asm volatile (";; srlz.i ;;" ::: "memory");
579 }
580
581 static inline void
582 ia64_srlz_d (void)
583 {
584 asm volatile (";; srlz.d" ::: "memory");
585 }
586
587 static inline __u64
588 ia64_get_rr (__u64 reg_bits)
589 {
590 __u64 r;
591 asm volatile ("mov %0=rr[%1]" : "=r"(r) : "r"(reg_bits) : "memory");
592 return r;
593 }
594
595 static inline void
596 ia64_set_rr (__u64 reg_bits, __u64 rr_val)
597 {
598 asm volatile ("mov rr[%0]=%1" :: "r"(reg_bits), "r"(rr_val) : "memory");
599 }
600
601 static inline __u64
602 ia64_get_dcr (void)
603 {
604 __u64 r;
605 asm volatile ("mov %0=cr.dcr" : "=r"(r));
606 return r;
607 }
608
609 static inline void
610 ia64_set_dcr (__u64 val)
611 {
612 asm volatile ("mov cr.dcr=%0;;" :: "r"(val) : "memory");
613 ia64_srlz_d();
614 }
615
616 static inline __u64
617 ia64_get_lid (void)
618 {
619 __u64 r;
620 asm volatile ("mov %0=cr.lid" : "=r"(r));
621 return r;
622 }
623
624 static inline void
625 ia64_invala (void)
626 {
627 asm volatile ("invala" ::: "memory");
628 }
629
630 /*
631 * Save the processor status flags in FLAGS and then clear the
632 * interrupt collection and interrupt enable bits.
633 */
634 #define ia64_clear_ic(flags) \
635 asm volatile ("mov %0=psr;; rsm psr.i | psr.ic;; srlz.i;;" \
636 : "=r"(flags) :: "memory");
637
638 /*
639 * Insert a translation into an instruction and/or data translation
640 * register.
641 */
642 static inline void
643 ia64_itr (__u64 target_mask, __u64 tr_num,
644 __u64 vmaddr, __u64 pte,
645 __u64 log_page_size)
646 {
647 asm volatile ("mov cr.itir=%0" :: "r"(log_page_size << 2) : "memory");
648 asm volatile ("mov cr.ifa=%0;;" :: "r"(vmaddr) : "memory");
649 if (target_mask & 0x1)
650 asm volatile ("itr.i itr[%0]=%1"
651 :: "r"(tr_num), "r"(pte) : "memory");
652 if (target_mask & 0x2)
653 asm volatile (";;itr.d dtr[%0]=%1"
654 :: "r"(tr_num), "r"(pte) : "memory");
655 }
656
657 /*
658 * Insert a translation into the instruction and/or data translation
659 * cache.
660 */
661 static inline void
662 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
663 __u64 log_page_size)
664 {
665 asm volatile ("mov cr.itir=%0" :: "r"(log_page_size << 2) : "memory");
666 asm volatile ("mov cr.ifa=%0;;" :: "r"(vmaddr) : "memory");
667 /* as per EAS2.6, itc must be the last instruction in an instruction group */
668 if (target_mask & 0x1)
669 asm volatile ("itc.i %0;;" :: "r"(pte) : "memory");
670 if (target_mask & 0x2)
671 asm volatile (";;itc.d %0;;" :: "r"(pte) : "memory");
672 }
673
674 /*
675 * Purge a range of addresses from instruction and/or data translation
676 * register(s).
677 */
678 static inline void
679 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
680 {
681 if (target_mask & 0x1)
682 asm volatile ("ptr.i %0,%1" :: "r"(vmaddr), "r"(log_size << 2));
683 if (target_mask & 0x2)
684 asm volatile ("ptr.d %0,%1" :: "r"(vmaddr), "r"(log_size << 2));
685 }
686
687 /* Set the interrupt vector address. The address must be suitably aligned (32KB). */
688 static inline void
689 ia64_set_iva (void *ivt_addr)
690 {
691 asm volatile ("mov cr.iva=%0;; srlz.i;;" :: "r"(ivt_addr) : "memory");
692 }
693
694 /* Set the page table address and control bits. */
695 static inline void
696 ia64_set_pta (__u64 pta)
697 {
698 /* Note: srlz.i implies srlz.d */
699 asm volatile ("mov cr.pta=%0;; srlz.i;;" :: "r"(pta) : "memory");
700 }
701
702 static inline __u64
703 ia64_get_cpuid (__u64 regnum)
704 {
705 __u64 r;
706
707 asm ("mov %0=cpuid[%r1]" : "=r"(r) : "rO"(regnum));
708 return r;
709 }
710
711 static inline void
712 ia64_eoi (void)
713 {
714 asm ("mov cr.eoi=r0;; srlz.d;;" ::: "memory");
715 }
716
717 static inline void
718 ia64_set_lrr0 (unsigned long val)
719 {
720 asm volatile ("mov cr.lrr0=%0;; srlz.d" :: "r"(val) : "memory");
721 }
722
723
724 static inline void
725 ia64_set_lrr1 (unsigned long val)
726 {
727 asm volatile ("mov cr.lrr1=%0;; srlz.d" :: "r"(val) : "memory");
728 }
729
730 static inline void
731 ia64_set_pmv (__u64 val)
732 {
733 asm volatile ("mov cr.pmv=%0" :: "r"(val) : "memory");
734 }
735
736 static inline __u64
737 ia64_get_pmc (__u64 regnum)
738 {
739 __u64 retval;
740
741 asm volatile ("mov %0=pmc[%1]" : "=r"(retval) : "r"(regnum));
742 return retval;
743 }
744
745 static inline void
746 ia64_set_pmc (__u64 regnum, __u64 value)
747 {
748 asm volatile ("mov pmc[%0]=%1" :: "r"(regnum), "r"(value));
749 }
750
751 static inline __u64
752 ia64_get_pmd (__u64 regnum)
753 {
754 __u64 retval;
755
756 asm volatile ("mov %0=pmd[%1]" : "=r"(retval) : "r"(regnum));
757 return retval;
758 }
759
760 static inline void
761 ia64_set_pmd (__u64 regnum, __u64 value)
762 {
763 asm volatile ("mov pmd[%0]=%1" :: "r"(regnum), "r"(value));
764 }
765
766 /*
767 * Given the address to which a spill occurred, return the unat bit
768 * number that corresponds to this address.
769 */
770 static inline __u64
771 ia64_unat_pos (void *spill_addr)
772 {
773 return ((__u64) spill_addr >> 3) & 0x3f;
774 }
775
776 /*
777 * Set the NaT bit of an integer register which was spilled at address
778 * SPILL_ADDR. UNAT is the mask to be updated.
779 */
780 static inline void
781 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
782 {
783 __u64 bit = ia64_unat_pos(spill_addr);
784 __u64 mask = 1UL << bit;
785
786 *unat = (*unat & ~mask) | (nat << bit);
787 }
788
789 /*
790 * Return saved PC of a blocked thread.
791 * Note that the only way T can block is through a call to schedule() -> switch_to().
792 */
793 static inline unsigned long
794 thread_saved_pc (struct thread_struct *t)
795 {
796 struct unw_frame_info info;
797 unsigned long ip;
798
799 /* XXX ouch: Linus, please pass the task pointer to thread_saved_pc() instead! */
800 struct task_struct *p = (void *) ((unsigned long) t - IA64_TASK_THREAD_OFFSET);
801
802 unw_init_from_blocked_task(&info, p);
803 if (unw_unwind(&info) < 0)
804 return 0;
805 unw_get_ip(&info, &ip);
806 return ip;
807 }
808
809 /*
810 * Get the current instruction/program counter value.
811 */
812 #define current_text_addr() \
813 ({ void *_pc; asm volatile ("mov %0=ip" : "=r" (_pc)); _pc; })
814
815 #define THREAD_SIZE IA64_STK_OFFSET
816 /* NOTE: The task struct and the stacks are allocated together. */
817 #define alloc_task_struct() \
818 ((struct task_struct *) __get_free_pages(GFP_KERNEL, IA64_TASK_STRUCT_LOG_NUM_PAGES))
819 #define free_task_struct(p) free_pages((unsigned long)(p), IA64_TASK_STRUCT_LOG_NUM_PAGES)
820 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
821
822 #define init_task (init_task_union.task)
823 #define init_stack (init_task_union.stack)
824
825 /*
826 * Set the correctable machine check vector register
827 */
828 static inline void
829 ia64_set_cmcv (__u64 val)
830 {
831 asm volatile ("mov cr.cmcv=%0" :: "r"(val) : "memory");
832 }
833
834 /*
835 * Read the correctable machine check vector register
836 */
837 static inline __u64
838 ia64_get_cmcv (void)
839 {
840 __u64 val;
841
842 asm volatile ("mov %0=cr.cmcv" : "=r"(val) :: "memory");
843 return val;
844 }
845
846 static inline __u64
847 ia64_get_ivr (void)
848 {
849 __u64 r;
850 asm volatile ("srlz.d;; mov %0=cr.ivr;; srlz.d;;" : "=r"(r));
851 return r;
852 }
853
854 static inline void
855 ia64_set_tpr (__u64 val)
856 {
857 asm volatile ("mov cr.tpr=%0" :: "r"(val));
858 }
859
860 static inline __u64
861 ia64_get_tpr (void)
862 {
863 __u64 r;
864 asm volatile ("mov %0=cr.tpr" : "=r"(r));
865 return r;
866 }
867
868 static inline void
869 ia64_set_irr0 (__u64 val)
870 {
871 asm volatile("mov cr.irr0=%0;;" :: "r"(val) : "memory");
872 ia64_srlz_d();
873 }
874
875 static inline __u64
876 ia64_get_irr0 (void)
877 {
878 __u64 val;
879
880 /* this is volatile because irr may change unbeknownst to gcc... */
881 asm volatile("mov %0=cr.irr0" : "=r"(val));
882 return val;
883 }
884
885 static inline void
886 ia64_set_irr1 (__u64 val)
887 {
888 asm volatile("mov cr.irr1=%0;;" :: "r"(val) : "memory");
889 ia64_srlz_d();
890 }
891
892 static inline __u64
893 ia64_get_irr1 (void)
894 {
895 __u64 val;
896
897 /* this is volatile because irr may change unbeknownst to gcc... */
898 asm volatile("mov %0=cr.irr1" : "=r"(val));
899 return val;
900 }
901
902 static inline void
903 ia64_set_irr2 (__u64 val)
904 {
905 asm volatile("mov cr.irr2=%0;;" :: "r"(val) : "memory");
906 ia64_srlz_d();
907 }
908
909 static inline __u64
910 ia64_get_irr2 (void)
911 {
912 __u64 val;
913
914 /* this is volatile because irr may change unbeknownst to gcc... */
915 asm volatile("mov %0=cr.irr2" : "=r"(val));
916 return val;
917 }
918
919 static inline void
920 ia64_set_irr3 (__u64 val)
921 {
922 asm volatile("mov cr.irr3=%0;;" :: "r"(val) : "memory");
923 ia64_srlz_d();
924 }
925
926 static inline __u64
927 ia64_get_irr3 (void)
928 {
929 __u64 val;
930
931 /* this is volatile because irr may change unbeknownst to gcc... */
932 asm volatile ("mov %0=cr.irr3" : "=r"(val));
933 return val;
934 }
935
936 static inline __u64
937 ia64_get_gp(void)
938 {
939 __u64 val;
940
941 asm ("mov %0=gp" : "=r"(val));
942 return val;
943 }
944
945 /* XXX remove the handcoded version once we have a sufficiently clever compiler... */
946 #ifdef SMART_COMPILER
947 # define ia64_rotr(w,n) \
948 ({ \
949 __u64 _w = (w), _n = (n); \
950 \
951 (_w >> _n) | (_w << (64 - _n)); \
952 })
953 #else
954 # define ia64_rotr(w,n) \
955 ({ \
956 __u64 result; \
957 asm ("shrp %0=%1,%1,%2" : "=r"(result) : "r"(w), "i"(n)); \
958 result; \
959 })
960 #endif
961
962 #define ia64_rotl(w,n) ia64_rotr((w),(64)-(n))
963
964 static inline __u64
965 ia64_thash (__u64 addr)
966 {
967 __u64 result;
968 asm ("thash %0=%1" : "=r"(result) : "r" (addr));
969 return result;
970 }
971
972
973 #define ARCH_HAS_PREFETCH
974 #define ARCH_HAS_PREFETCHW
975 #define ARCH_HAS_SPINLOCK_PREFETCH
976 #define PREFETCH_STRIDE 256
977
978 extern inline void prefetch(const void *x)
979 {
980 __asm__ __volatile__ ("lfetch [%0]" : : "r"(x));
981 }
982
983 extern inline void prefetchw(const void *x)
984 {
985 __asm__ __volatile__ ("lfetch.excl [%0]" : : "r"(x));
986 }
987
988 #define spin_lock_prefetch(x) prefetchw(x)
989
990
991 #endif /* !__ASSEMBLY__ */
992
993 #endif /* _ASM_IA64_PROCESSOR_H */
994