File: /usr/src/linux/include/asm-mips/io.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2000 FSMLabs, Inc.
10 */
11 #ifndef _ASM_IO_H
12 #define _ASM_IO_H
13
14 #include <linux/config.h>
15 #include <linux/pagemap.h>
16 #include <asm/addrspace.h>
17 #include <asm/byteorder.h>
18
19 /*
20 * Slowdown I/O port space accesses for antique hardware.
21 */
22 #undef CONF_SLOWDOWN_IO
23
24 /*
25 * Sane hardware offers swapping of I/O space accesses in hardware; less
26 * sane hardware forces software to fiddle with this ...
27 */
28 #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
29
30 #define __ioswab8(x) (x)
31 #define __ioswab16(x) swab16(x)
32 #define __ioswab32(x) swab32(x)
33
34 #else
35
36 #define __ioswab8(x) (x)
37 #define __ioswab16(x) (x)
38 #define __ioswab32(x) (x)
39
40 #endif
41
42 /*
43 * This file contains the definitions for the MIPS counterpart of the
44 * x86 in/out instructions. This heap of macros and C results in much
45 * better code than the approach of doing it in plain C. The macros
46 * result in code that is to fast for certain hardware. On the other
47 * side the performance of the string functions should be improved for
48 * sake of certain devices like EIDE disks that do highspeed polled I/O.
49 *
50 * Ralf
51 *
52 * This file contains the definitions for the x86 IO instructions
53 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
54 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
55 * versions of the single-IO instructions (inb_p/inw_p/..).
56 *
57 * This file is not meant to be obfuscating: it's just complicated
58 * to (a) handle it all in a way that makes gcc able to optimize it
59 * as well as possible and (b) trying to avoid writing the same thing
60 * over and over again with slight variations and possibly making a
61 * mistake somewhere.
62 */
63
64 /*
65 * On MIPS I/O ports are memory mapped, so we access them using normal
66 * load/store instructions. mips_io_port_base is the virtual address to
67 * which all ports are being mapped. For sake of efficiency some code
68 * assumes that this is an address that can be loaded with a single lui
69 * instruction, so the lower 16 bits must be zero. Should be true on
70 * on any sane architecture; generic code does not use this assumption.
71 */
72 extern unsigned long mips_io_port_base;
73
74 /*
75 * Thanks to James van Artsdalen for a better timing-fix than
76 * the two short jumps: using outb's to a nonexistent port seems
77 * to guarantee better timings even on fast machines.
78 *
79 * On the other hand, I'd like to be sure of a non-existent port:
80 * I feel a bit unsafe about using 0x80 (should be safe, though)
81 *
82 * Linus
83 *
84 */
85
86 #define __SLOW_DOWN_IO \
87 __asm__ __volatile__( \
88 "sb\t$0,0x80(%0)" \
89 : : "r" (mips_io_port_base));
90
91 #ifdef CONF_SLOWDOWN_IO
92 #ifdef REALLY_SLOW_IO
93 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
94 #else
95 #define SLOW_DOWN_IO __SLOW_DOWN_IO
96 #endif
97 #else
98 #define SLOW_DOWN_IO
99 #endif
100
101 /*
102 * Change virtual addresses to physical addresses and vv.
103 * These are trivial on the 1:1 Linux/MIPS mapping
104 */
105 extern inline unsigned long virt_to_phys(volatile void * address)
106 {
107 return PHYSADDR(address);
108 }
109
110 extern inline void * phys_to_virt(unsigned long address)
111 {
112 return (void *)KSEG0ADDR(address);
113 }
114
115 /*
116 * IO bus memory addresses are also 1:1 with the physical address
117 */
118 extern inline unsigned long virt_to_bus(volatile void * address)
119 {
120 return PHYSADDR(address);
121 }
122
123 extern inline void * bus_to_virt(unsigned long address)
124 {
125 return (void *)KSEG0ADDR(address);
126 }
127
128 /*
129 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
130 * for the processor.
131 */
132 extern unsigned long isa_slot_offset;
133
134 extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
135
136 extern inline void *ioremap(unsigned long offset, unsigned long size)
137 {
138 return __ioremap(offset, size, _CACHE_UNCACHED);
139 }
140
141 extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
142 {
143 return __ioremap(offset, size, _CACHE_UNCACHED);
144 }
145
146 extern void iounmap(void *addr);
147
148 /*
149 * XXX We need system specific versions of these to handle EISA address bits
150 * 24-31 on SNI.
151 * XXX more SNI hacks.
152 */
153 #define readb(addr) (*(volatile unsigned char *)(addr))
154 #define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
155 #define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
156 #define __raw_readb readb
157 #define __raw_readw readw
158 #define __raw_readl readl
159
160 #define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b)
161 #define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b))
162 #define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b))
163 #define __raw_writeb writeb
164 #define __raw_writew writew
165 #define __raw_writel writel
166
167 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
168 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
169 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
170
171 /* END SNI HACKS ... */
172
173 /*
174 * ISA space is 'always mapped' on currently supported MIPS systems, no need
175 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
176 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
177 * are physical addresses. The following constant pointer can be
178 * used as the IO-area pointer (it can be iounmapped as well, so the
179 * analogy with PCI is quite large):
180 */
181 #define __ISA_IO_base ((char *)(PAGE_OFFSET))
182
183 #define isa_readb(a) readb(a)
184 #define isa_readw(a) readw(a)
185 #define isa_readl(a) readl(a)
186 #define isa_writeb(b,a) writeb(b,a)
187 #define isa_writew(w,a) writew(w,a)
188 #define isa_writel(l,a) writel(l,a)
189
190 #define isa_memset_io(a,b,c) memset_io((a),(b),(c))
191 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
192 #define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
193
194 /*
195 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
196 * just copy it. The net code will then do the checksum later.
197 */
198 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
199 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
200
201 static inline int check_signature(unsigned long io_addr,
202 const unsigned char *signature, int length)
203 {
204 int retval = 0;
205 do {
206 if (readb(io_addr) != *signature)
207 goto out;
208 io_addr++;
209 signature++;
210 length--;
211 } while (length);
212 retval = 1;
213 out:
214 return retval;
215 }
216 #define isa_check_signature(io, s, l) check_signature(i,s,l)
217
218 /*
219 * Talk about misusing macros..
220 */
221
222 #define __OUT1(s) \
223 extern inline void __out##s(unsigned int value, unsigned int port) {
224
225 #define __OUT2(m) \
226 __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
227
228 #define __OUT(m,s,w) \
229 __OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
230 __OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
231 __OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
232 SLOW_DOWN_IO; } \
233 __OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
234 SLOW_DOWN_IO; }
235
236 #define __IN1(t,s) \
237 extern __inline__ t __in##s(unsigned int port) { t _v;
238
239 /*
240 * Required nops will be inserted by the assembler
241 */
242 #define __IN2(m) \
243 __asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
244
245 #define __IN(t,m,s,w) \
246 __IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
247 __IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
248 __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
249 __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
250
251 #define __INS1(s) \
252 extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
253
254 #define __INS2(m) \
255 if (count) \
256 __asm__ __volatile__ ( \
257 ".set\tnoreorder\n\t" \
258 ".set\tnoat\n" \
259 "1:\tl" #m "\t$1,%4(%5)\n\t" \
260 "subu\t%1,1\n\t" \
261 "s" #m "\t$1,(%0)\n\t" \
262 "bne\t$0,%1,1b\n\t" \
263 "addiu\t%0,%6\n\t" \
264 ".set\tat\n\t" \
265 ".set\treorder"
266
267 #define __INS(m,s,i) \
268 __INS1(s) __INS2(m) \
269 : "=r" (addr), "=r" (count) \
270 : "0" (addr), "1" (count), "i" (0), \
271 "r" (mips_io_port_base+port), "I" (i) \
272 : "$1");} \
273 __INS1(s##c) __INS2(m) \
274 : "=r" (addr), "=r" (count) \
275 : "0" (addr), "1" (count), "ir" (port), \
276 "r" (mips_io_port_base), "I" (i) \
277 : "$1");}
278
279 #define __OUTS1(s) \
280 extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
281
282 #define __OUTS2(m) \
283 if (count) \
284 __asm__ __volatile__ ( \
285 ".set\tnoreorder\n\t" \
286 ".set\tnoat\n" \
287 "1:\tl" #m "\t$1,(%0)\n\t" \
288 "subu\t%1,1\n\t" \
289 "s" #m "\t$1,%4(%5)\n\t" \
290 "bne\t$0,%1,1b\n\t" \
291 "addiu\t%0,%6\n\t" \
292 ".set\tat\n\t" \
293 ".set\treorder"
294
295 #define __OUTS(m,s,i) \
296 __OUTS1(s) __OUTS2(m) \
297 : "=r" (addr), "=r" (count) \
298 : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
299 : "$1");} \
300 __OUTS1(s##c) __OUTS2(m) \
301 : "=r" (addr), "=r" (count) \
302 : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
303 : "$1");}
304
305 __IN(unsigned char,b,b,8)
306 __IN(unsigned short,h,w,16)
307 __IN(unsigned int,w,l,32)
308
309 __OUT(b,b,8)
310 __OUT(h,w,16)
311 __OUT(w,l,32)
312
313 __INS(b,b,1)
314 __INS(h,w,2)
315 __INS(w,l,4)
316
317 __OUTS(b,b,1)
318 __OUTS(h,w,2)
319 __OUTS(w,l,4)
320
321
322 /*
323 * Note that due to the way __builtin_constant_p() works, you
324 * - can't use it inside an inline function (it will never be true)
325 * - you don't have to worry about side effects within the __builtin..
326 */
327 #define outb(val,port) \
328 ((__builtin_constant_p((port)) && (port) < 32768) ? \
329 __outbc((val),(port)) : \
330 __outb((val),(port)))
331
332 #define inb(port) \
333 ((__builtin_constant_p((port)) && (port) < 32768) ? \
334 __inbc(port) : \
335 __inb(port))
336
337 #define outb_p(val,port) \
338 ((__builtin_constant_p((port)) && (port) < 32768) ? \
339 __outbc_p((val),(port)) : \
340 __outb_p((val),(port)))
341
342 #define inb_p(port) \
343 ((__builtin_constant_p((port)) && (port) < 32768) ? \
344 __inbc_p(port) : \
345 __inb_p(port))
346
347 #define outw(val,port) \
348 ((__builtin_constant_p((port)) && (port) < 32768) ? \
349 __outwc((val),(port)) : \
350 __outw((val),(port)))
351
352 #define inw(port) \
353 ((__builtin_constant_p((port)) && (port) < 32768) ? \
354 __inwc(port) : \
355 __inw(port))
356
357 #define outw_p(val,port) \
358 ((__builtin_constant_p((port)) && (port) < 32768) ? \
359 __outwc_p((val),(port)) : \
360 __outw_p((val),(port)))
361
362 #define inw_p(port) \
363 ((__builtin_constant_p((port)) && (port) < 32768) ? \
364 __inwc_p(port) : \
365 __inw_p(port))
366
367 #define outl(val,port) \
368 ((__builtin_constant_p((port)) && (port) < 32768) ? \
369 __outlc((val),(port)) : \
370 __outl((val),(port)))
371
372 #define inl(port) \
373 ((__builtin_constant_p((port)) && (port) < 32768) ? \
374 __inlc(port) : \
375 __inl(port))
376
377 #define outl_p(val,port) \
378 ((__builtin_constant_p((port)) && (port) < 32768) ? \
379 __outlc_p((val),(port)) : \
380 __outl_p((val),(port)))
381
382 #define inl_p(port) \
383 ((__builtin_constant_p((port)) && (port) < 32768) ? \
384 __inlc_p(port) : \
385 __inl_p(port))
386
387
388 #define outsb(port,addr,count) \
389 ((__builtin_constant_p((port)) && (port) < 32768) ? \
390 __outsbc((port),(addr),(count)) : \
391 __outsb ((port),(addr),(count)))
392
393 #define insb(port,addr,count) \
394 ((__builtin_constant_p((port)) && (port) < 32768) ? \
395 __insbc((port),(addr),(count)) : \
396 __insb((port),(addr),(count)))
397
398 #define outsw(port,addr,count) \
399 ((__builtin_constant_p((port)) && (port) < 32768) ? \
400 __outswc((port),(addr),(count)) : \
401 __outsw ((port),(addr),(count)))
402
403 #define insw(port,addr,count) \
404 ((__builtin_constant_p((port)) && (port) < 32768) ? \
405 __inswc((port),(addr),(count)) : \
406 __insw((port),(addr),(count)))
407
408 #define outsl(port,addr,count) \
409 ((__builtin_constant_p((port)) && (port) < 32768) ? \
410 __outslc((port),(addr),(count)) : \
411 __outsl ((port),(addr),(count)))
412
413 #define insl(port,addr,count) \
414 ((__builtin_constant_p((port)) && (port) < 32768) ? \
415 __inslc((port),(addr),(count)) : \
416 __insl((port),(addr),(count)))
417
418 #define IO_SPACE_LIMIT 0xffff
419
420 /*
421 * The caches on some architectures aren't dma-coherent and have need to
422 * handle this in software. There are three types of operations that
423 * can be applied to dma buffers.
424 *
425 * - dma_cache_wback_inv(start, size) makes caches and coherent by
426 * writing the content of the caches back to memory, if necessary.
427 * The function also invalidates the affected part of the caches as
428 * necessary before DMA transfers from outside to memory.
429 * - dma_cache_wback(start, size) makes caches and coherent by
430 * writing the content of the caches back to memory, if necessary.
431 * The function also invalidates the affected part of the caches as
432 * necessary before DMA transfers from outside to memory.
433 * - dma_cache_inv(start, size) invalidates the affected parts of the
434 * caches. Dirty lines of the caches may be written back or simply
435 * be discarded. This operation is necessary before dma operations
436 * to the memory.
437 */
438 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
439 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
440 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
441
442 #define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
443 #define dma_cache_wback(start,size) _dma_cache_wback(start,size)
444 #define dma_cache_inv(start,size) _dma_cache_inv(start,size)
445
446 #endif /* _ASM_IO_H */
447