File: /usr/src/linux/include/asm-mips/mipsregs.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 */
12 #ifndef _ASM_MIPSREGS_H
13 #define _ASM_MIPSREGS_H
14
15 #include <linux/linkage.h>
16
17 /*
18 * The following macros are especially useful for __asm__
19 * inline assembler.
20 */
21 #ifndef __STR
22 #define __STR(x) #x
23 #endif
24 #ifndef STR
25 #define STR(x) __STR(x)
26 #endif
27
28 /*
29 * Coprocessor 0 register names
30 */
31 #define CP0_INDEX $0
32 #define CP0_RANDOM $1
33 #define CP0_ENTRYLO0 $2
34 #define CP0_ENTRYLO1 $3
35 #define CP0_CONF $3
36 #define CP0_CONTEXT $4
37 #define CP0_PAGEMASK $5
38 #define CP0_WIRED $6
39 #define CP0_INFO $7
40 #define CP0_BADVADDR $8
41 #define CP0_COUNT $9
42 #define CP0_ENTRYHI $10
43 #define CP0_COMPARE $11
44 #define CP0_STATUS $12
45 #define CP0_CAUSE $13
46 #define CP0_EPC $14
47 #define CP0_PRID $15
48 #define CP0_CONFIG $16
49 #define CP0_LLADDR $17
50 #define CP0_WATCHLO $18
51 #define CP0_WATCHHI $19
52 #define CP0_XCONTEXT $20
53 #define CP0_FRAMEMASK $21
54 #define CP0_DIAGNOSTIC $22
55 #define CP0_PERFORMANCE $25
56 #define CP0_ECC $26
57 #define CP0_CACHEERR $27
58 #define CP0_TAGLO $28
59 #define CP0_TAGHI $29
60 #define CP0_ERROREPC $30
61
62 /*
63 * R4640/R4650 cp0 register names. These registers are listed
64 * here only for completeness; without MMU these CPUs are not useable
65 * by Linux. A future ELKS port might take make Linux run on them
66 * though ...
67 */
68 #define CP0_IBASE $0
69 #define CP0_IBOUND $1
70 #define CP0_DBASE $2
71 #define CP0_DBOUND $3
72 #define CP0_CALG $17
73 #define CP0_IWATCH $18
74 #define CP0_DWATCH $19
75
76 /*
77 * Coprocessor 0 Set 1 register names
78 */
79 #define CP0_S1_DERRADDR0 $26
80 #define CP0_S1_DERRADDR1 $27
81 #define CP0_S1_INTCONTROL $20
82 /*
83 * Coprocessor 1 (FPU) register names
84 */
85 #define CP1_REVISION $0
86 #define CP1_STATUS $31
87
88 /*
89 * FPU Status Register Values
90 */
91 /*
92 * Status Register Values
93 */
94
95 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
96 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
97 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
98 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
99 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
100 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
101 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
102 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
103 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
104 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
105
106 /*
107 * X the exception cause indicator
108 * E the exception enable
109 * S the sticky/flag bit
110 */
111 #define FPU_CSR_ALL_X 0x0003f000
112 #define FPU_CSR_UNI_X 0x00020000
113 #define FPU_CSR_INV_X 0x00010000
114 #define FPU_CSR_DIV_X 0x00008000
115 #define FPU_CSR_OVF_X 0x00004000
116 #define FPU_CSR_UDF_X 0x00002000
117 #define FPU_CSR_INE_X 0x00001000
118
119 #define FPU_CSR_ALL_E 0x00000f80
120 #define FPU_CSR_INV_E 0x00000800
121 #define FPU_CSR_DIV_E 0x00000400
122 #define FPU_CSR_OVF_E 0x00000200
123 #define FPU_CSR_UDF_E 0x00000100
124 #define FPU_CSR_INE_E 0x00000080
125
126 #define FPU_CSR_ALL_S 0x0000007c
127 #define FPU_CSR_INV_S 0x00000040
128 #define FPU_CSR_DIV_S 0x00000020
129 #define FPU_CSR_OVF_S 0x00000010
130 #define FPU_CSR_UDF_S 0x00000008
131 #define FPU_CSR_INE_S 0x00000004
132
133 /* rounding mode */
134 #define FPU_CSR_RN 0x0 /* nearest */
135 #define FPU_CSR_RZ 0x1 /* towards zero */
136 #define FPU_CSR_RU 0x2 /* towards +Infinity */
137 #define FPU_CSR_RD 0x3 /* towards -Infinity */
138
139
140 /*
141 * Values for PageMask register
142 */
143 #include <linux/config.h>
144 #ifdef CONFIG_CPU_VR41XX
145 #define PM_1K 0x00000000
146 #define PM_4K 0x00001800
147 #define PM_16K 0x00007800
148 #define PM_64K 0x0001f800
149 #define PM_256K 0x0007f800
150 #else
151 #define PM_4K 0x00000000
152 #define PM_16K 0x00006000
153 #define PM_64K 0x0001e000
154 #define PM_256K 0x0007e000
155 #define PM_1M 0x001fe000
156 #define PM_4M 0x007fe000
157 #define PM_16M 0x01ffe000
158 #endif
159
160 /*
161 * Values used for computation of new tlb entries
162 */
163 #define PL_4K 12
164 #define PL_16K 14
165 #define PL_64K 16
166 #define PL_256K 18
167 #define PL_1M 20
168 #define PL_4M 22
169 #define PL_16M 24
170
171 /*
172 * Macros to access the system control coprocessor
173 */
174 #define read_32bit_cp0_register(source) \
175 ({ int __res; \
176 __asm__ __volatile__( \
177 ".set\tpush\n\t" \
178 ".set\treorder\n\t" \
179 "mfc0\t%0,"STR(source)"\n\t" \
180 ".set\tpop" \
181 : "=r" (__res)); \
182 __res;})
183
184 #define read_32bit_cp0_set1_register(source) \
185 ({ int __res; \
186 __asm__ __volatile__( \
187 ".set\tpush\n\t" \
188 ".set\treorder\n\t" \
189 "cfc0\t%0,"STR(source)"\n\t" \
190 ".set\tpop" \
191 : "=r" (__res)); \
192 __res;})
193
194 /*
195 * For now use this only with interrupts disabled!
196 */
197 #define read_64bit_cp0_register(source) \
198 ({ int __res; \
199 __asm__ __volatile__( \
200 ".set\tmips3\n\t" \
201 "dmfc0\t%0,"STR(source)"\n\t" \
202 ".set\tmips0" \
203 : "=r" (__res)); \
204 __res;})
205
206 #define write_32bit_cp0_register(register,value) \
207 __asm__ __volatile__( \
208 "mtc0\t%0,"STR(register)"\n\t" \
209 "nop" \
210 : : "r" (value));
211
212 #define write_32bit_cp0_set1_register(register,value) \
213 __asm__ __volatile__( \
214 "ctc0\t%0,"STR(register)"\n\t" \
215 "nop" \
216 : : "r" (value));
217
218 #define write_64bit_cp0_register(register,value) \
219 __asm__ __volatile__( \
220 ".set\tmips3\n\t" \
221 "dmtc0\t%0,"STR(register)"\n\t" \
222 ".set\tmips0" \
223 : : "r" (value))
224
225 /*
226 * This should be changed when we get a compiler that support the MIPS32 ISA.
227 */
228 #define read_mips32_cp0_config1() \
229 ({ int __res; \
230 __asm__ __volatile__( \
231 ".set\tnoreorder\n\t" \
232 ".set\tnoat\n\t" \
233 ".word\t0x40018001\n\t" \
234 "move\t%0,$1\n\t" \
235 ".set\tat\n\t" \
236 ".set\treorder" \
237 :"=r" (__res)); \
238 __res;})
239
240 /*
241 * R4x00 interrupt enable / cause bits
242 */
243 #define IE_SW0 (1<< 8)
244 #define IE_SW1 (1<< 9)
245 #define IE_IRQ0 (1<<10)
246 #define IE_IRQ1 (1<<11)
247 #define IE_IRQ2 (1<<12)
248 #define IE_IRQ3 (1<<13)
249 #define IE_IRQ4 (1<<14)
250 #define IE_IRQ5 (1<<15)
251
252 /*
253 * R4x00 interrupt cause bits
254 */
255 #define C_SW0 (1<< 8)
256 #define C_SW1 (1<< 9)
257 #define C_IRQ0 (1<<10)
258 #define C_IRQ1 (1<<11)
259 #define C_IRQ2 (1<<12)
260 #define C_IRQ3 (1<<13)
261 #define C_IRQ4 (1<<14)
262 #define C_IRQ5 (1<<15)
263
264 #ifndef _LANGUAGE_ASSEMBLY
265 /*
266 * Manipulate the status register.
267 * Mostly used to access the interrupt bits.
268 */
269 #define __BUILD_SET_CP0(name,register) \
270 extern __inline__ unsigned int \
271 set_cp0_##name(unsigned int set) \
272 { \
273 unsigned int res; \
274 \
275 res = read_32bit_cp0_register(register); \
276 res |= set; \
277 write_32bit_cp0_register(register, res); \
278 \
279 return res; \
280 } \
281 \
282 extern __inline__ unsigned int \
283 clear_cp0_##name(unsigned int clear) \
284 { \
285 unsigned int res; \
286 \
287 res = read_32bit_cp0_register(register); \
288 res &= ~clear; \
289 write_32bit_cp0_register(register, res); \
290 \
291 return res; \
292 } \
293 \
294 extern __inline__ unsigned int \
295 change_cp0_##name(unsigned int change, unsigned int new) \
296 { \
297 unsigned int res; \
298 \
299 res = read_32bit_cp0_register(register); \
300 res &= ~change; \
301 res |= (new & change); \
302 if(change) \
303 write_32bit_cp0_register(register, res); \
304 \
305 return res; \
306 }
307
308 __BUILD_SET_CP0(status,CP0_STATUS)
309 __BUILD_SET_CP0(cause,CP0_CAUSE)
310 __BUILD_SET_CP0(config,CP0_CONFIG)
311
312 #endif /* defined (_LANGUAGE_ASSEMBLY) */
313
314 /*
315 * Bitfields in the R4xx0 cp0 status register
316 */
317 #define ST0_IE 0x00000001
318 #define ST0_EXL 0x00000002
319 #define ST0_ERL 0x00000004
320 #define ST0_KSU 0x00000018
321 # define KSU_USER 0x00000010
322 # define KSU_SUPERVISOR 0x00000008
323 # define KSU_KERNEL 0x00000000
324 #define ST0_UX 0x00000020
325 #define ST0_SX 0x00000040
326 #define ST0_KX 0x00000080
327 #define ST0_DE 0x00010000
328 #define ST0_CE 0x00020000
329
330 /*
331 * Bitfields in the R[23]000 cp0 status register.
332 */
333 #define ST0_IEC 0x00000001
334 #define ST0_KUC 0x00000002
335 #define ST0_IEP 0x00000004
336 #define ST0_KUP 0x00000008
337 #define ST0_IEO 0x00000010
338 #define ST0_KUO 0x00000020
339 /* bits 6 & 7 are reserved on R[23]000 */
340 #define ST0_ISC 0x00010000
341 #define ST0_SWC 0x00020000
342 #define ST0_CM 0x00080000
343
344 /*
345 * Bits specific to the R4640/R4650
346 */
347 #define ST0_UM (1 << 4)
348 #define ST0_IL (1 << 23)
349 #define ST0_DL (1 << 24)
350
351 /*
352 * Bitfields in the TX39 family CP0 Configuration Register 3
353 */
354 #define TX39_CONF_ICS_SHIFT 19
355 #define TX39_CONF_ICS_MASK 0x00380000
356 #define TX39_CONF_ICS_1KB 0x00000000
357 #define TX39_CONF_ICS_2KB 0x00080000
358 #define TX39_CONF_ICS_4KB 0x00100000
359 #define TX39_CONF_ICS_8KB 0x00180000
360 #define TX39_CONF_ICS_16KB 0x00200000
361
362 #define TX39_CONF_DCS_SHIFT 16
363 #define TX39_CONF_DCS_MASK 0x00070000
364 #define TX39_CONF_DCS_1KB 0x00000000
365 #define TX39_CONF_DCS_2KB 0x00010000
366 #define TX39_CONF_DCS_4KB 0x00020000
367 #define TX39_CONF_DCS_8KB 0x00030000
368 #define TX39_CONF_DCS_16KB 0x00040000
369
370 #define TX39_CONF_CWFON 0x00004000
371 #define TX39_CONF_WBON 0x00002000
372 #define TX39_CONF_RF_SHIFT 10
373 #define TX39_CONF_RF_MASK 0x00000c00
374 #define TX39_CONF_DOZE 0x00000200
375 #define TX39_CONF_HALT 0x00000100
376 #define TX39_CONF_LOCK 0x00000080
377 #define TX39_CONF_ICE 0x00000020
378 #define TX39_CONF_DCE 0x00000010
379 #define TX39_CONF_IRSIZE_SHIFT 2
380 #define TX39_CONF_IRSIZE_MASK 0x0000000c
381 #define TX39_CONF_DRSIZE_SHIFT 0
382 #define TX39_CONF_DRSIZE_MASK 0x00000003
383
384 /*
385 * Status register bits available in all MIPS CPUs.
386 */
387 #define ST0_IM 0x0000ff00
388 #define STATUSB_IP0 8
389 #define STATUSF_IP0 (1 << 8)
390 #define STATUSB_IP1 9
391 #define STATUSF_IP1 (1 << 9)
392 #define STATUSB_IP2 10
393 #define STATUSF_IP2 (1 << 10)
394 #define STATUSB_IP3 11
395 #define STATUSF_IP3 (1 << 11)
396 #define STATUSB_IP4 12
397 #define STATUSF_IP4 (1 << 12)
398 #define STATUSB_IP5 13
399 #define STATUSF_IP5 (1 << 13)
400 #define STATUSB_IP6 14
401 #define STATUSF_IP6 (1 << 14)
402 #define STATUSB_IP7 15
403 #define STATUSF_IP7 (1 << 15)
404 #define STATUSB_IP8 0
405 #define STATUSF_IP8 (1 << 0)
406 #define STATUSB_IP9 1
407 #define STATUSF_IP9 (1 << 1)
408 #define STATUSB_IP10 2
409 #define STATUSF_IP10 (1 << 2)
410 #define STATUSB_IP11 3
411 #define STATUSF_IP11 (1 << 3)
412 #define STATUSB_IP12 4
413 #define STATUSF_IP12 (1 << 4)
414 #define STATUSB_IP13 5
415 #define STATUSF_IP13 (1 << 5)
416 #define STATUSB_IP14 6
417 #define STATUSF_IP14 (1 << 6)
418 #define STATUSB_IP15 7
419 #define STATUSF_IP15 (1 << 7)
420 #define ST0_CH 0x00040000
421 #define ST0_SR 0x00100000
422 #define ST0_BEV 0x00400000
423 #define ST0_RE 0x02000000
424 #define ST0_FR 0x04000000
425 #define ST0_CU 0xf0000000
426 #define ST0_CU0 0x10000000
427 #define ST0_CU1 0x20000000
428 #define ST0_CU2 0x40000000
429 #define ST0_CU3 0x80000000
430 #define ST0_XX 0x80000000 /* MIPS IV naming */
431
432 /*
433 * Bitfields and bit numbers in the coprocessor 0 cause register.
434 *
435 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
436 */
437 #define CAUSEB_EXCCODE 2
438 #define CAUSEF_EXCCODE (31 << 2)
439 #define CAUSEB_IP 8
440 #define CAUSEF_IP (255 << 8)
441 #define CAUSEB_IP0 8
442 #define CAUSEF_IP0 (1 << 8)
443 #define CAUSEB_IP1 9
444 #define CAUSEF_IP1 (1 << 9)
445 #define CAUSEB_IP2 10
446 #define CAUSEF_IP2 (1 << 10)
447 #define CAUSEB_IP3 11
448 #define CAUSEF_IP3 (1 << 11)
449 #define CAUSEB_IP4 12
450 #define CAUSEF_IP4 (1 << 12)
451 #define CAUSEB_IP5 13
452 #define CAUSEF_IP5 (1 << 13)
453 #define CAUSEB_IP6 14
454 #define CAUSEF_IP6 (1 << 14)
455 #define CAUSEB_IP7 15
456 #define CAUSEF_IP7 (1 << 15)
457 #define CAUSEB_IV 23
458 #define CAUSEF_IV (1 << 23)
459 #define CAUSEB_CE 28
460 #define CAUSEF_CE (3 << 28)
461 #define CAUSEB_BD 31
462 #define CAUSEF_BD (1 << 31)
463
464 /*
465 * Bits in the coprozessor 0 config register.
466 */
467 #define CONF_CM_CACHABLE_NO_WA 0
468 #define CONF_CM_CACHABLE_WA 1
469 #define CONF_CM_UNCACHED 2
470 #define CONF_CM_CACHABLE_NONCOHERENT 3
471 #define CONF_CM_CACHABLE_CE 4
472 #define CONF_CM_CACHABLE_COW 5
473 #define CONF_CM_CACHABLE_CUW 6
474 #define CONF_CM_CACHABLE_ACCELERATED 7
475 #define CONF_CM_CMASK 7
476 #define CONF_DB (1 << 4)
477 #define CONF_IB (1 << 5)
478 #define CONF_SC (1 << 17)
479 #define CONF_AC (1 << 23)
480 #define CONF_HALT (1 << 25)
481
482 /*
483 * R10000 performance counter definitions.
484 *
485 * FIXME: The R10000 performance counter opens a nice way to implement CPU
486 * time accounting with a precission of one cycle. I don't have
487 * R10000 silicon but just a manual, so ...
488 */
489
490 /*
491 * Events counted by counter #0
492 */
493 #define CE0_CYCLES 0
494 #define CE0_INSN_ISSUED 1
495 #define CE0_LPSC_ISSUED 2
496 #define CE0_S_ISSUED 3
497 #define CE0_SC_ISSUED 4
498 #define CE0_SC_FAILED 5
499 #define CE0_BRANCH_DECODED 6
500 #define CE0_QW_WB_SECONDARY 7
501 #define CE0_CORRECTED_ECC_ERRORS 8
502 #define CE0_ICACHE_MISSES 9
503 #define CE0_SCACHE_I_MISSES 10
504 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
505 #define CE0_EXT_INTERVENTIONS_REQ 12
506 #define CE0_EXT_INVALIDATE_REQ 13
507 #define CE0_VIRTUAL_COHERENCY_COND 14
508 #define CE0_INSN_GRADUATED 15
509
510 /*
511 * Events counted by counter #1
512 */
513 #define CE1_CYCLES 0
514 #define CE1_INSN_GRADUATED 1
515 #define CE1_LPSC_GRADUATED 2
516 #define CE1_S_GRADUATED 3
517 #define CE1_SC_GRADUATED 4
518 #define CE1_FP_INSN_GRADUATED 5
519 #define CE1_QW_WB_PRIMARY 6
520 #define CE1_TLB_REFILL 7
521 #define CE1_BRANCH_MISSPREDICTED 8
522 #define CE1_DCACHE_MISS 9
523 #define CE1_SCACHE_D_MISSES 10
524 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
525 #define CE1_EXT_INTERVENTION_HITS 12
526 #define CE1_EXT_INVALIDATE_REQ 13
527 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
528 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
529
530 /*
531 * These flags define in which priviledge mode the counters count events
532 */
533 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
534 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
535 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
536 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
537
538 #endif /* _ASM_MIPSREGS_H */
539