File: /usr/src/linux/include/asm-parisc/pci.h
1 #ifndef __ASM_PARISC_PCI_H
2 #define __ASM_PARISC_PCI_H
3
4 #include <asm/scatterlist.h>
5
6 #define MIN_PCI_PORT 0x000000
7 #define MAX_PCI_PORT 0xffffff
8
9 /*
10 ** HP PCI platforms generally support multiple bus adapters.
11 ** (workstations 1-~4, servers 2-~32)
12 **
13 ** Newer platforms number the busses across PCI bus adapters *sparsely*.
14 ** E.g. 0, 8, 16, ...
15 **
16 ** Under a PCI bus, most HP platforms support PPBs up to two or three
17 ** levels deep. See "Bit3" product line.
18 */
19 #define PCI_MAX_BUSSES 256
20
21 /* [soapbox on]
22 ** Who the hell can develope stuff without ASSERT or VASSERT?
23 ** No one understands all the modules across all platforms.
24 ** For linux add another dimension - processor architectures.
25 **
26 ** This should be a standard/global macro used liberally
27 ** in all code. Every respectable engineer I know in HP
28 ** would support this argument. - grant
29 ** [soapbox off]
30 */
31 #ifdef PCI_DEBUG
32 #define ASSERT(expr) \
33 if(!(expr)) { \
34 printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
35 panic(#expr); \
36 }
37 #else
38 #define ASSERT(expr)
39 #endif
40
41
42 /*
43 ** pci_hba_data (aka H2P_OBJECT in HP/UX)
44 **
45 ** This is the "common" or "base" data structure which HBA drivers
46 ** (eg Dino or LBA) are required to place at the top of their own
47 ** dev->sysdata structure. I've heard this called "C inheritance" too.
48 **
49 ** Data needed by pcibios layer belongs here.
50 */
51 struct pci_hba_data {
52 struct pci_hba_data *next; /* global chain of HBAs */
53 char *base_addr; /* aka Host Physical Address */
54 struct hp_device *iodc_info; /* Info from PA bus walk */
55 struct pci_bus *hba_bus; /* primary PCI bus below HBA */
56 int hba_num; /* I/O port space access "key" */
57 struct resource bus_num; /* PCI bus numbers */
58 struct resource io_space; /* PIOP */
59 struct resource mem_space; /* LMMIO */
60 unsigned long mem_space_offset; /* VCLASS support */
61 /* REVISIT - spinlock to protect resources? */
62 };
63
64
65 /*
66 ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
67 ** (This eliminates some of the warnings).
68 */
69 struct pci_bus;
70 struct pci_dev;
71
72 /*
73 ** Most PCI devices (eg Tulip, NCR720) also export the same registers
74 ** to both MMIO and I/O port space. Due to poor performance of I/O Port
75 ** access under HP PCI bus adapters, strongly reccomend use of MMIO
76 ** address space.
77 **
78 ** While I'm at it more PA programming notes:
79 **
80 ** 1) MMIO stores (writes) are posted operations. This means the processor
81 ** gets an "ACK" before the write actually gets to the device. A read
82 ** to the same device (or typically the bus adapter above it) will
83 ** force in-flight write transaction(s) out to the targeted device
84 ** before the read can complete.
85 **
86 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
87 ** respect to DMA on all platforms. Ie PIO data can reach the processor
88 ** before in-flight DMA reaches memory. Since most SMP PA platforms
89 ** are I/O coherent, it generally doesn't matter...but sometimes
90 ** it does.
91 **
92 ** I've helped device driver writers debug both types of problems.
93 */
94 struct pci_port_ops {
95 u8 (*inb) (struct pci_hba_data *hba, u16 port);
96 u16 (*inw) (struct pci_hba_data *hba, u16 port);
97 u32 (*inl) (struct pci_hba_data *hba, u16 port);
98 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
99 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
100 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
101 };
102
103
104 struct pci_bios_ops {
105 void (*init)(void);
106 void (*fixup_bus)(struct pci_bus *bus);
107 };
108
109 extern void pcibios_size_bridge(struct pci_bus *, struct pbus_set_ranges_data *);
110
111
112 /*
113 ** See Documentation/DMA-mapping.txt
114 */
115 struct pci_dma_ops {
116 int (*dma_supported)(struct pci_dev *dev, dma_addr_t mask);
117 void *(*alloc_consistent)(struct pci_dev *dev, size_t size, dma_addr_t *iova);
118 void (*free_consistent)(struct pci_dev *dev, size_t size, void *vaddr, dma_addr_t iova);
119 dma_addr_t (*map_single)(struct pci_dev *dev, void *addr, size_t size, int direction);
120 void (*unmap_single)(struct pci_dev *dev, dma_addr_t iova, size_t size, int direction);
121 int (*map_sg)(struct pci_dev *dev, struct scatterlist *sg, int nents, int direction);
122 void (*unmap_sg)(struct pci_dev *dev, struct scatterlist *sg, int nhwents, int direction);
123 void (*dma_sync_single)(struct pci_dev *dev, dma_addr_t iova, size_t size, int direction);
124 void (*dma_sync_sg)(struct pci_dev *dev, struct scatterlist *sg, int nelems, int direction);
125 };
126
127
128 /*
129 ** We could live without the hppa_dma_ops indirection if we didn't want
130 ** to support 4 different dma models with one binary or they were
131 ** all loadable modules:
132 ** I/O MMU consistent method dma_sync behavior
133 ** ============= ====================== =======================
134 ** a) PA-7x00LC uncachable host memory flush/purge
135 ** b) U2/Uturn cachable host memory NOP
136 ** c) Ike/Astro cachable host memory NOP
137 ** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel
138 **
139 ** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU.
140 **
141 ** Systems (eg PCX-T workstations) that don't fall into the above
142 ** categories will need to modify the needed drivers to perform
143 ** flush/purge and allocate "regular" cacheable pages for everything.
144 */
145
146 extern struct pci_dma_ops *hppa_dma_ops;
147 extern struct pci_dma_ops pcxl_dma_ops;
148 extern struct pci_dma_ops pcx_dma_ops;
149
150 /*
151 ** Oops hard if we haven't setup hppa_dma_ops by the time the first driver
152 ** attempts to initialize.
153 ** Since panic() is a (void)(), pci_dma_panic() is needed to satisfy
154 ** the (int)() required by pci_dma_supported() interface.
155 */
156 static inline int pci_dma_panic(char *msg)
157 {
158 panic(msg);
159 return -1;
160 }
161
162 #define pci_dma_supported(p, m) ( \
163 (NULL == hppa_dma_ops) \
164 ? pci_dma_panic("Dynamic DMA support missing...OOPS!\n(Hint: was Astro/Ike/U2/Uturn not claimed?)\n") \
165 : hppa_dma_ops->dma_supported(p,m) \
166 )
167
168 #define pci_alloc_consistent(p, s, a) hppa_dma_ops->alloc_consistent(p,s,a)
169 #define pci_free_consistent(p, s, v, a) hppa_dma_ops->free_consistent(p,s,v,a)
170 #define pci_map_single(p, v, s, d) hppa_dma_ops->map_single(p, v, s, d)
171 #define pci_unmap_single(p, a, s, d) hppa_dma_ops->unmap_single(p, a, s, d)
172 #define pci_map_sg(p, sg, n, d) hppa_dma_ops->map_sg(p, sg, n, d)
173 #define pci_unmap_sg(p, sg, n, d) hppa_dma_ops->unmap_sg(p, sg, n, d)
174
175 /* For U2/Astro/Ike based platforms (which are fully I/O coherent)
176 ** dma_sync is a NOP. Let's keep the performance path short here.
177 */
178 #define pci_dma_sync_single(p, a, s, d) { if (hppa_dma_ops->dma_sync_single) \
179 hppa_dma_ops->dma_sync_single(p, a, s, d); \
180 }
181 #define pci_dma_sync_sg(p, sg, n, d) { if (hppa_dma_ops->dma_sync_sg) \
182 hppa_dma_ops->dma_sync_sg(p, sg, n, d); \
183 }
184
185 /*
186 ** Stuff declared in arch/parisc/kernel/pci.c
187 */
188 extern struct pci_port_ops *pci_port;
189 extern struct pci_bios_ops *pci_bios;
190 extern int pci_post_reset_delay; /* delay after de-asserting #RESET */
191
192 extern void pcibios_register_hba(struct pci_hba_data *);
193 extern void pcibios_assign_unassigned_resources(struct pci_bus *);
194
195
196 /*
197 ** used by drivers/pci/pci.c:pci_do_scan_bus()
198 ** 0 == check if bridge is numbered before re-numbering.
199 ** 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
200 **
201 ** REVISIT:
202 ** To date, only alpha sets this to one. We'll need to set this
203 ** to zero for legacy platforms and one for PAT platforms.
204 */
205 #ifdef __LP64__
206 extern int pdc_pat; /* arch/parisc/kernel/inventory.c */
207 #define pcibios_assign_all_busses() pdc_pat
208 #else
209 #define pcibios_assign_all_busses() 0
210 #endif
211
212 #define PCIBIOS_MIN_IO 0x10
213 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
214
215 /* Return the index of the PCI controller for device PDEV. */
216 #define pci_controller_num(PDEV) (0)
217
218 #endif /* __ASM_PARISC_PCI_H */
219