File: /usr/src/linux/include/asm-sh/irq.h
1 #ifndef __ASM_SH_IRQ_H
2 #define __ASM_SH_IRQ_H
3
4 /*
5 *
6 * linux/include/asm-sh/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 *
11 */
12
13 #include <linux/config.h>
14 #include <asm/machvec.h>
15 #include <asm/ptrace.h> /* for pt_regs */
16
17 #if defined(__sh3__)
18 #define INTC_IPRA 0xfffffee2UL
19 #define INTC_IPRB 0xfffffee4UL
20 #elif defined(__SH4__)
21 #define INTC_IPRA 0xffd00004UL
22 #define INTC_IPRB 0xffd00008UL
23 #define INTC_IPRC 0xffd0000cUL
24 #endif
25
26 #define TIMER_IRQ 16
27 #define TIMER_IPR_ADDR INTC_IPRA
28 #define TIMER_IPR_POS 3
29 #define TIMER_PRIORITY 2
30
31 #define RTC_IRQ 22
32 #define RTC_IPR_ADDR INTC_IPRA
33 #define RTC_IPR_POS 0
34 #define RTC_PRIORITY TIMER_PRIORITY
35
36 #if defined(__sh3__)
37 #define DMTE0_IRQ 48
38 #define DMTE1_IRQ 49
39 #define DMTE2_IRQ 50
40 #define DMTE3_IRQ 51
41 #define DMA_IPR_ADDR INTC_IPRE
42 #define DMA_IPR_POS 3
43 #define DMA_PRIORITY 7
44 #elif defined(__SH4__)
45 #define DMTE0_IRQ 34
46 #define DMTE1_IRQ 35
47 #define DMTE2_IRQ 36
48 #define DMTE3_IRQ 37
49 #define DMAE_IRQ 38
50 #define DMA_IPR_ADDR INTC_IPRC
51 #define DMA_IPR_POS 2
52 #define DMA_PRIORITY 7
53 #endif
54
55 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
56 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
57 defined (CONFIG_CPU_SUBTYPE_SH7751)
58 #define SCI_ERI_IRQ 23
59 #define SCI_RXI_IRQ 24
60 #define SCI_TXI_IRQ 25
61 #define SCI_IPR_ADDR INTC_IPRB
62 #define SCI_IPR_POS 1
63 #define SCI_PRIORITY 3
64 #endif
65
66 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
67 #define SCIF_ERI_IRQ 56
68 #define SCIF_RXI_IRQ 57
69 #define SCIF_BRI_IRQ 58
70 #define SCIF_TXI_IRQ 59
71 #define SCIF_IPR_ADDR INTC_IPRE
72 #define SCIF_IPR_POS 1
73 #define SCIF_PRIORITY 3
74
75 #define IRDA_ERI_IRQ 52
76 #define IRDA_RXI_IRQ 53
77 #define IRDA_BRI_IRQ 54
78 #define IRDA_TXI_IRQ 55
79 #define IRDA_IPR_ADDR INTC_IPRE
80 #define IRDA_IPR_POS 2
81 #define IRDA_PRIORITY 3
82 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
83 defined(CONFIG_CPU_SUBTYPE_ST40STB1)
84 #define SCIF_ERI_IRQ 40
85 #define SCIF_RXI_IRQ 41
86 #define SCIF_BRI_IRQ 42
87 #define SCIF_TXI_IRQ 43
88 #define SCIF_IPR_ADDR INTC_IPRC
89 #define SCIF_IPR_POS 1
90 #define SCIF_PRIORITY 3
91 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
92 #define SCIF1_ERI_IRQ 23
93 #define SCIF1_RXI_IRQ 24
94 #define SCIF1_BRI_IRQ 25
95 #define SCIF1_TXI_IRQ 26
96 #define SCIF1_IPR_ADDR INTC_IPRB
97 #define SCIF1_IPR_POS 1
98 #define SCIF1_PRIORITY 3
99 #endif
100 #endif
101
102 /* NR_IRQS is made from three components:
103 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
104 * 2. PINT_NR_IRQS - number of PINT interrupts
105 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
106 */
107
108 /* 1. ONCHIP_NR_IRQS */
109 #ifdef CONFIG_SH_GENERIC
110 # define ONCHIP_NR_IRQS 144
111 #else
112 # if defined(CONFIG_CPU_SUBTYPE_SH7707)
113 # define ONCHIP_NR_IRQS 64
114 # define PINT_NR_IRQS 16
115 # elif defined(CONFIG_CPU_SUBTYPE_SH7708)
116 # define ONCHIP_NR_IRQS 32
117 # elif defined(CONFIG_CPU_SUBTYPE_SH7709)
118 # define ONCHIP_NR_IRQS 64 // Actually 61
119 # define PINT_NR_IRQS 16
120 # elif defined(CONFIG_CPU_SUBTYPE_SH7750)
121 # define ONCHIP_NR_IRQS 48 // Actually 44
122 # elif defined(CONFIG_CPU_SUBTYPE_SH7751)
123 # define ONCHIP_NR_IRQS 72
124 # elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
125 # define ONCHIP_NR_IRQS 144
126 # endif
127 #endif
128
129 /* 2. PINT_NR_IRQS */
130 #ifdef CONFIG_SH_GENERIC
131 # define PINT_NR_IRQS 16
132 #else
133 # ifndef PINT_NR_IRQS
134 # define PINT_NR_IRQS 0
135 # endif
136 #endif
137
138 #if PINT_NR_IRQS > 0
139 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
140 #endif
141
142 /* 3. OFFCHIP_NR_IRQS */
143 #ifdef CONFIG_SH_GENERIC
144 # define OFFCHIP_NR_IRQS 16
145 #else
146 # if defined(CONFIG_HD64461)
147 # define OFFCHIP_NR_IRQS 16
148 # elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
149 # define OFFCHIP_NR_IRQS 48
150 # elif defined(CONFIG_HD64465)
151 # define OFFCHIP_NR_IRQS 16
152 # elif defined (CONFIG_SH_EC3104)
153 # define OFFCHIP_NR_IRQS 16
154 # elif defined (CONFIG_SH_DREAMCAST)
155 # define OFFCHIP_NR_IRQS 96
156 # else
157 # define OFFCHIP_NR_IRQS 0
158 # endif
159 #endif
160
161 #if OFFCHIP_NR_IRQS > 0
162 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
163 #endif
164
165 /* NR_IRQS. 1+2+3 */
166 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
167
168 /* In a generic kernel, NR_IRQS is an upper bound, and we should use
169 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
170 */
171 #ifdef CONFIG_SH_GENERIC
172 # define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
173 #else
174 # define ACTUAL_NR_IRQS NR_IRQS
175 #endif
176
177
178 extern void disable_irq(unsigned int);
179 extern void disable_irq_nosync(unsigned int);
180 extern void enable_irq(unsigned int);
181
182 /*
183 * Simple Mask Register Support
184 */
185 extern void make_maskreg_irq(unsigned int irq);
186 extern unsigned short *irq_mask_register;
187
188 /*
189 * Function for "on chip support modules".
190 */
191 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
192 int pos, int priority);
193 extern void make_imask_irq(unsigned int irq);
194
195 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
196 #define INTC_IRR0 0xa4000004UL
197 #define INTC_IRR1 0xa4000006UL
198 #define INTC_IRR2 0xa4000008UL
199
200 #define INTC_ICR0 0xfffffee0UL
201 #define INTC_ICR1 0xa4000010UL
202 #define INTC_ICR2 0xa4000012UL
203 #define INTC_INTER 0xa4000014UL
204
205 #define INTC_IPRC 0xa4000016UL
206 #define INTC_IPRD 0xa4000018UL
207 #define INTC_IPRE 0xa400001aUL
208 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
209 #define INTC_IPRF 0xa400001cUL
210 #endif
211
212 #define PORT_PACR 0xa4000100UL
213 #define PORT_PBCR 0xa4000102UL
214 #define PORT_PCCR 0xa4000104UL
215 #define PORT_PFCR 0xa400010aUL
216 #define PORT_PADR 0xa4000120UL
217 #define PORT_PBDR 0xa4000122UL
218 #define PORT_PCDR 0xa4000124UL
219 #define PORT_PFDR 0xa400012aUL
220
221 #define IRQ0_IRQ 32
222 #define IRQ1_IRQ 33
223 #define IRQ2_IRQ 34
224 #define IRQ3_IRQ 35
225 #define IRQ4_IRQ 36
226 #define IRQ5_IRQ 37
227
228 #define IRQ0_IPR_ADDR INTC_IPRC
229 #define IRQ1_IPR_ADDR INTC_IPRC
230 #define IRQ2_IPR_ADDR INTC_IPRC
231 #define IRQ3_IPR_ADDR INTC_IPRC
232 #define IRQ4_IPR_ADDR INTC_IPRD
233 #define IRQ5_IPR_ADDR INTC_IPRD
234
235 #define IRQ0_IPR_POS 0
236 #define IRQ1_IPR_POS 1
237 #define IRQ2_IPR_POS 2
238 #define IRQ3_IPR_POS 3
239 #define IRQ4_IPR_POS 0
240 #define IRQ5_IPR_POS 1
241
242 #define IRQ0_PRIORITY 1
243 #define IRQ1_PRIORITY 1
244 #define IRQ2_PRIORITY 1
245 #define IRQ3_PRIORITY 1
246 #define IRQ4_PRIORITY 1
247 #define IRQ5_PRIORITY 1
248
249 #define PINT0_IRQ 40
250 #define PINT8_IRQ 41
251
252 #define PINT0_IPR_ADDR INTC_IPRD
253 #define PINT8_IPR_ADDR INTC_IPRD
254
255 #define PINT0_IPR_POS 3
256 #define PINT8_IPR_POS 2
257 #define PINT0_PRIORITY 2
258 #define PINT8_PRIORITY 2
259
260 extern int ipr_irq_demux(int irq);
261 #define __irq_demux(irq) ipr_irq_demux(irq)
262
263 #else
264 #define __irq_demux(irq) irq
265 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
266
267 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
268 defined(CONFIG_CPU_SUBTYPE_ST40STB1)
269 #define INTC_ICR 0xffd00000
270 #define INTC_ICR_NMIL (1<<15)
271 #define INTC_ICR_MAI (1<<14)
272 #define INTC_ICR_NMIB (1<<9)
273 #define INTC_ICR_NMIE (1<<8)
274 #define INTC_ICR_IRLM (1<<7)
275 #endif
276
277 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
278 #define INTC2_FIRST_IRQ 64
279 #define NR_INTC2_IRQS 25
280
281 #define INTC2_BASE0 0xfe080000
282 #define INTC2_INTC2MODE (INTC2_BASE0+0x80)
283
284 #define INTC2_INTPRI_OFFSET 0x00
285 #define INTC2_INTREQ_OFFSET 0x20
286 #define INTC2_INTMSK_OFFSET 0x40
287 #define INTC2_INTMSKCLR_OFFSET 0x60
288
289 extern void make_intc2_irq(unsigned int irq,unsigned int addr,
290 unsigned int group,int pos,int priority);
291
292 #endif
293
294 #ifdef CONFIG_SH_GENERIC
295
296 static __inline__ int irq_demux(int irq)
297 {
298 if (sh_mv.mv_irq_demux) {
299 irq = sh_mv.mv_irq_demux(irq);
300 }
301 return __irq_demux(irq);
302 }
303
304 #elif defined(CONFIG_SH_BIGSUR)
305
306 extern int bigsur_irq_demux(int irq);
307 #define irq_demux(irq) bigsur_irq_demux(irq)
308
309 #elif defined(CONFIG_HD64461)
310
311 extern int hd64461_irq_demux(int irq);
312 #define irq_demux(irq) hd64461_irq_demux(irq)
313
314 #elif defined(CONFIG_HD64465)
315
316 extern int hd64465_irq_demux(int irq);
317 #define irq_demux(irq) hd64465_irq_demux(irq)
318
319 #elif defined(CONFIG_SH_EC3104)
320
321 extern int ec3104_irq_demux(int irq);
322 #define irq_demux ec3104_irq_demux
323
324 #elif defined(CONFIG_SH_CAT68701)
325
326 extern int cat68701_irq_demux(int irq);
327 #define irq_demux cat68701_irq_demux
328
329 #elif defined(CONFIG_SH_DREAMCAST)
330
331 extern int systemasic_irq_demux(int irq);
332 #define irq_demux systemasic_irq_demux
333
334 #else
335
336 #define irq_demux(irq) __irq_demux(irq)
337
338 #endif
339
340
341
342 #endif /* __ASM_SH_IRQ_H */
343