File: /usr/src/linux/arch/ia64/sn/io/pci.c
1 /*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * SNI64 specific PCI support for SNI IO.
8 *
9 * Copyright (C) 1997, 1998, 2000 Colin Ngam
10 */
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/config.h>
14 #include <linux/pci.h>
15 #include <asm/sn/types.h>
16 #include <asm/sn/sgi.h>
17 #include <asm/sn/iobus.h>
18 #include <asm/sn/iograph.h>
19 #include <asm/param.h>
20 #include <asm/sn/pio.h>
21 #include <asm/sn/xtalk/xwidget.h>
22 #include <asm/sn/sn_private.h>
23 #include <asm/sn/addrs.h>
24 #include <asm/sn/invent.h>
25 #include <asm/sn/hcl.h>
26 #include <asm/sn/hcl_util.h>
27 #include <asm/sn/pci/pciio.h>
28 #include <asm/sn/pci/pcibr.h>
29 #include <asm/sn/pci/pcibr_private.h>
30 #include <asm/sn/pci/bridge.h>
31
32 #ifdef DEBUG_CONFIG
33 #define DBG(x...) printk(x)
34 #else
35 #define DBG(x...)
36 #endif
37
38
39
40 #ifdef CONFIG_PCI
41
42 extern devfs_handle_t pci_bus_to_vertex(unsigned char);
43 extern devfs_handle_t devfn_to_vertex(unsigned char bus, unsigned char devfn);
44
45 /*
46 * snia64_read_config_byte - Read a byte from the config area of the device.
47 */
48 static int snia64_read_config_byte (struct pci_dev *dev,
49 int where, unsigned char *val)
50 {
51 unsigned long res = 0;
52 unsigned size = 1;
53 devfs_handle_t device_vertex;
54
55 if ( (dev == (struct pci_dev *)0) || (val == (unsigned char *)0) ) {
56 return PCIBIOS_DEVICE_NOT_FOUND;
57 }
58 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn);
59 if (!device_vertex) {
60 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n",
61 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
62 return(-1);
63 }
64 res = pciio_config_get(device_vertex, (unsigned) where, size);
65 *val = (unsigned char) res;
66 return PCIBIOS_SUCCESSFUL;
67 }
68
69 /*
70 * snia64_read_config_word - Read 2 bytes from the config area of the device.
71 */
72 static int snia64_read_config_word (struct pci_dev *dev,
73 int where, unsigned short *val)
74 {
75 unsigned long res = 0;
76 unsigned size = 2; /* 2 bytes */
77 devfs_handle_t device_vertex;
78
79 if ( (dev == (struct pci_dev *)0) || (val == (unsigned short *)0) ) {
80 return PCIBIOS_DEVICE_NOT_FOUND;
81 }
82 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn);
83 if (!device_vertex) {
84 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n",
85 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
86 return(-1);
87 }
88 res = pciio_config_get(device_vertex, (unsigned) where, size);
89 *val = (unsigned short) res;
90 return PCIBIOS_SUCCESSFUL;
91 }
92
93 /*
94 * snia64_read_config_dword - Read 4 bytes from the config area of the device.
95 */
96 static int snia64_read_config_dword (struct pci_dev *dev,
97 int where, unsigned int *val)
98 {
99 unsigned long res = 0;
100 unsigned size = 4; /* 4 bytes */
101 devfs_handle_t device_vertex;
102
103 if (where & 3) {
104 return PCIBIOS_BAD_REGISTER_NUMBER;
105 }
106 if ( (dev == (struct pci_dev *)0) || (val == (unsigned int *)0) ) {
107 return PCIBIOS_DEVICE_NOT_FOUND;
108 }
109
110 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn);
111 if (!device_vertex) {
112 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n",
113 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
114 return(-1);
115 }
116 res = pciio_config_get(device_vertex, (unsigned) where, size);
117 *val = (unsigned int) res;
118 return PCIBIOS_SUCCESSFUL;
119 }
120
121 /*
122 * snia64_write_config_byte - Writes 1 byte to the config area of the device.
123 */
124 static int snia64_write_config_byte (struct pci_dev *dev,
125 int where, unsigned char val)
126 {
127 devfs_handle_t device_vertex;
128
129 if ( dev == (struct pci_dev *)0 ) {
130 return PCIBIOS_DEVICE_NOT_FOUND;
131 }
132 /*
133 * if it's an IOC3 then we bail out, we special
134 * case them with pci_fixup_ioc3
135 */
136 if (dev->vendor == PCI_VENDOR_ID_SGI &&
137 dev->device == PCI_DEVICE_ID_SGI_IOC3 )
138 return PCIBIOS_SUCCESSFUL;
139
140 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn);
141 if (!device_vertex) {
142 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n",
143 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
144 return(-1);
145 }
146 pciio_config_set( device_vertex, (unsigned)where, 1, (uint64_t) val);
147
148 return PCIBIOS_SUCCESSFUL;
149 }
150
151 /*
152 * snia64_write_config_word - Writes 2 bytes to the config area of the device.
153 */
154 static int snia64_write_config_word (struct pci_dev *dev,
155 int where, unsigned short val)
156 {
157 devfs_handle_t device_vertex = NULL;
158
159 if (where & 1) {
160 return PCIBIOS_BAD_REGISTER_NUMBER;
161 }
162 if ( dev == (struct pci_dev *)0 ) {
163 return PCIBIOS_DEVICE_NOT_FOUND;
164 }
165 /*
166 * if it's an IOC3 then we bail out, we special
167 * case them with pci_fixup_ioc3
168 */
169 if (dev->vendor == PCI_VENDOR_ID_SGI &&
170 dev->device == PCI_DEVICE_ID_SGI_IOC3)
171 return PCIBIOS_SUCCESSFUL;
172
173 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn);
174 if (!device_vertex) {
175 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n",
176 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
177 return(-1);
178 }
179 pciio_config_set( device_vertex, (unsigned)where, 2, (uint64_t) val);
180
181 return PCIBIOS_SUCCESSFUL;
182 }
183
184 /*
185 * snia64_write_config_dword - Writes 4 bytes to the config area of the device.
186 */
187 static int snia64_write_config_dword (struct pci_dev *dev,
188 int where, unsigned int val)
189 {
190 devfs_handle_t device_vertex;
191
192 if (where & 3) {
193 return PCIBIOS_BAD_REGISTER_NUMBER;
194 }
195 if ( dev == (struct pci_dev *)0 ) {
196 return PCIBIOS_DEVICE_NOT_FOUND;
197 }
198 /*
199 * if it's an IOC3 then we bail out, we special
200 * case them with pci_fixup_ioc3
201 */
202 if (dev->vendor == PCI_VENDOR_ID_SGI &&
203 dev->device == PCI_DEVICE_ID_SGI_IOC3)
204 return PCIBIOS_SUCCESSFUL;
205
206 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn);
207 if (!device_vertex) {
208 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n",
209 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
210 return(-1);
211 }
212 pciio_config_set( device_vertex, (unsigned)where, 4, (uint64_t) val);
213
214 return PCIBIOS_SUCCESSFUL;
215 }
216
217 static struct pci_ops snia64_pci_ops = {
218 snia64_read_config_byte,
219 snia64_read_config_word,
220 snia64_read_config_dword,
221 snia64_write_config_byte,
222 snia64_write_config_word,
223 snia64_write_config_dword
224 };
225
226 /*
227 * snia64_pci_find_bios - SNIA64 pci_find_bios() platform specific code.
228 */
229 void __init
230 sn1_pci_find_bios(void)
231 {
232 extern struct pci_ops pci_conf;
233 /*
234 * Go initialize our IO Infrastructure ..
235 */
236 extern void sgi_master_io_infr_init(void);
237
238 sgi_master_io_infr_init();
239
240 #ifdef BRINGUP
241 if ( IS_RUNNING_ON_SIMULATOR() )
242 return;
243 #endif
244 /* sn1_io_infrastructure_init(); */
245 pci_conf = snia64_pci_ops;
246 }
247
248 void
249 pci_fixup_ioc3(struct pci_dev *d)
250 {
251 int i;
252 unsigned int size;
253
254 devfs_handle_t bridge_vhdl = pci_bus_to_vertex(d->bus->number);
255
256 /* IOC3 only decodes 0x20 bytes of the config space, reading
257 * beyond that is relatively benign but writing beyond that
258 * (especially the base address registers) will shut down the
259 * pci bus...so avoid doing so.
260 * NOTE: this means we can't program the intr_pin into the device,
261 * currently we hack this with special code in
262 * sgi_pci_intr_support()
263 */
264 DBG("pci_fixup_ioc3: Fixing base addresses for ioc3 device %s\n", d->slot_name);
265
266 /* I happen to know from the spec that the ioc3 needs only 0xfffff
267 * The standard pci trick of writing ~0 to the baddr and seeing
268 * what comes back doesn't work with the ioc3
269 */
270 size = 0xfffff;
271 d->resource[0].end = (unsigned long) d->resource[0].start + (unsigned long) size;
272
273 /*
274 * Zero out the resource structure .. because we did not go through
275 * the normal PCI Infrastructure Init, garbbage are left in these
276 * fileds.
277 */
278 for (i = 1; i <= PCI_ROM_RESOURCE; i++) {
279 d->resource[i].start = 0UL;
280 d->resource[i].end = 0UL;
281 d->resource[i].flags = 0UL;
282 }
283
284 /*
285 * Hardcode Device 4 register(IOC3 is in Slot 4) to set the
286 * DEV_DIRECT bit. This will not work if IOC3 is not on Slot
287 * 4.
288 */
289 DBG("pci_fixup_ioc3: FIXME .. need to take NASID into account when setting IOC3 devreg 0x%x\n", *(volatile u32 *)0xc0000a000f000220);
290
291 *(volatile u32 *)0xc0000a000f000220 |= 0x90000;
292
293 d->subsystem_vendor = 0;
294 d->subsystem_device = 0;
295
296 }
297
298 #endif /* CONFIG_PCI */
299