File: /usr/src/linux/include/asm-sparc/atomic.h
1 /* atomic.h: These still suck, but the I-cache hit rate is higher.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
4 * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
5 */
6
7 #ifndef __ARCH_SPARC_ATOMIC__
8 #define __ARCH_SPARC_ATOMIC__
9
10 #include <linux/config.h>
11
12 typedef struct { volatile int counter; } atomic_t;
13
14 #ifdef __KERNEL__
15 #ifndef CONFIG_SMP
16
17 #define ATOMIC_INIT(i) { (i) }
18 #define atomic_read(v) ((v)->counter)
19 #define atomic_set(v, i) (((v)->counter) = i)
20
21 #else
22 /* We do the bulk of the actual work out of line in two common
23 * routines in assembler, see arch/sparc/lib/atomic.S for the
24 * "fun" details.
25 *
26 * For SMP the trick is you embed the spin lock byte within
27 * the word, use the low byte so signedness is easily retained
28 * via a quick arithmetic shift. It looks like this:
29 *
30 * ----------------------------------------
31 * | signed 24-bit counter value | lock | atomic_t
32 * ----------------------------------------
33 * 31 8 7 0
34 */
35
36 #define ATOMIC_INIT(i) { (i << 8) }
37
38 static __inline__ int atomic_read(atomic_t *v)
39 {
40 int ret = v->counter;
41
42 while(ret & 0xff)
43 ret = v->counter;
44
45 return ret >> 8;
46 }
47
48 #define atomic_set(v, i) (((v)->counter) = ((i) << 8))
49 #endif
50
51 static __inline__ int __atomic_add(int i, atomic_t *v)
52 {
53 register volatile int *ptr asm("g1");
54 register int increment asm("g2");
55
56 ptr = &v->counter;
57 increment = i;
58
59 __asm__ __volatile__("
60 mov %%o7, %%g4
61 call ___atomic_add
62 add %%o7, 8, %%o7
63 " : "=&r" (increment)
64 : "0" (increment), "r" (ptr)
65 : "g3", "g4", "g7", "memory", "cc");
66
67 return increment;
68 }
69
70 static __inline__ int __atomic_sub(int i, atomic_t *v)
71 {
72 register volatile int *ptr asm("g1");
73 register int increment asm("g2");
74
75 ptr = &v->counter;
76 increment = i;
77
78 __asm__ __volatile__("
79 mov %%o7, %%g4
80 call ___atomic_sub
81 add %%o7, 8, %%o7
82 " : "=&r" (increment)
83 : "0" (increment), "r" (ptr)
84 : "g3", "g4", "g7", "memory", "cc");
85
86 return increment;
87 }
88
89 #define atomic_add(i, v) ((void)__atomic_add((i), (v)))
90 #define atomic_sub(i, v) ((void)__atomic_sub((i), (v)))
91
92 #define atomic_dec_return(v) __atomic_sub(1, (v))
93 #define atomic_inc_return(v) __atomic_add(1, (v))
94
95 #define atomic_sub_and_test(i, v) (__atomic_sub((i), (v)) == 0)
96 #define atomic_dec_and_test(v) (__atomic_sub(1, (v)) == 0)
97
98 #define atomic_inc(v) ((void)__atomic_add(1, (v)))
99 #define atomic_dec(v) ((void)__atomic_sub(1, (v)))
100
101 #define atomic_add_negative(i, v) (__atomic_add((i), (v)) < 0)
102
103 /* Atomic operations are already serializing */
104 #define smp_mb__before_atomic_dec() barrier()
105 #define smp_mb__after_atomic_dec() barrier()
106 #define smp_mb__before_atomic_inc() barrier()
107 #define smp_mb__after_atomic_inc() barrier()
108
109 #endif /* !(__KERNEL__) */
110
111 #endif /* !(__ARCH_SPARC_ATOMIC__) */
112