File: /usr/src/linux/include/asm-sparc64/pgtable.h
1 /* $Id: pgtable.h,v 1.146 2001/09/11 02:20:23 kanoj Exp $
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
10
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
15 #include <asm/spitfire.h>
16 #include <asm/asi.h>
17 #include <asm/mmu_context.h>
18 #include <asm/system.h>
19 #include <asm/page.h>
20 #include <asm/processor.h>
21
22 /* XXX All of this needs to be rethought so we can take advantage
23 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
24 * XXX in the middle like on spitfire. -DaveM
25 */
26 /*
27 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
28 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
29 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
30 * table is a single page long). The next higher PMD_BITS determine pmd#
31 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
32 * since the pmd entries are 4 bytes, and each pmd page is a single page
33 * long). Finally, the higher few bits determine pgde#.
34 */
35
36 /* PMD_SHIFT determines the size of the area a second-level page table can map */
37 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
38 #define PMD_SIZE (1UL << PMD_SHIFT)
39 #define PMD_MASK (~(PMD_SIZE-1))
40 #define PMD_BITS 11
41
42 /* PGDIR_SHIFT determines what a third-level page table entry can map */
43 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
44 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
45 #define PGDIR_MASK (~(PGDIR_SIZE-1))
46
47 #ifndef __ASSEMBLY__
48
49 #define PG_dcache_dirty PG_arch_1
50
51 /* Certain architectures need to do special things when pte's
52 * within a page table are directly modified. Thus, the following
53 * hook is made available.
54 */
55 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
56
57 /* Entries per page directory level. */
58 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
59
60 /* We the first one in this file, what we export to the kernel
61 * is different so we can optimize correctly for 32-bit tasks.
62 */
63 #define REAL_PTRS_PER_PMD (1UL << PMD_BITS)
64 #define PTRS_PER_PMD ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \
65 (1UL << (32 - (PAGE_SHIFT-3) - PAGE_SHIFT)) : (REAL_PTRS_PER_PMD)))
66
67 /*
68 * We cannot use the top address range because VPTE table lives there. This
69 * formula finds the total legal virtual space in the processor, subtracts the
70 * vpte size, then aligns it to the number of bytes mapped by one pgde, and
71 * thus calculates the number of pgdes needed.
72 */
73 #define PTRS_PER_PGD (((1UL << VA_BITS) - VPTE_SIZE + (1UL << (PAGE_SHIFT + \
74 (PAGE_SHIFT-3) + PMD_BITS)) - 1) / (1UL << (PAGE_SHIFT + \
75 (PAGE_SHIFT-3) + PMD_BITS)))
76
77 /* Kernel has a separate 44bit address space. */
78 #define USER_PTRS_PER_PGD ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \
79 (1) : (PTRS_PER_PGD)))
80 #define FIRST_USER_PGD_NR 0
81
82 /* NOTE: TLB miss handlers depend heavily upon where this is. */
83 #define VMALLOC_START 0x0000000140000000UL
84 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
85 #define VMALLOC_END 0x0000000200000000UL
86
87 #define pte_ERROR(e) __builtin_trap()
88 #define pmd_ERROR(e) __builtin_trap()
89 #define pgd_ERROR(e) __builtin_trap()
90
91 #endif /* !(__ASSEMBLY__) */
92
93 /* Spitfire/Cheetah TTE bits. */
94 #define _PAGE_VALID 0x8000000000000000 /* Valid TTE */
95 #define _PAGE_R 0x8000000000000000 /* Used to keep ref bit up to date */
96 #define _PAGE_SZ4MB 0x6000000000000000 /* 4MB Page */
97 #define _PAGE_SZ512K 0x4000000000000000 /* 512K Page */
98 #define _PAGE_SZ64K 0x2000000000000000 /* 64K Page */
99 #define _PAGE_SZ8K 0x0000000000000000 /* 8K Page */
100 #define _PAGE_NFO 0x1000000000000000 /* No Fault Only */
101 #define _PAGE_IE 0x0800000000000000 /* Invert Endianness */
102 #define _PAGE_SN 0x0000800000000000 /* (Cheetah) Snoop */
103 #define _PAGE_PADDR_SF 0x000001FFFFFFE000 /* (Spitfire) Phys Address [40:13] */
104 #define _PAGE_PADDR 0x000007FFFFFFE000 /* (Cheetah) Phys Address [42:13] */
105 #define _PAGE_SOFT 0x0000000000001F80 /* Software bits */
106 #define _PAGE_L 0x0000000000000040 /* Locked TTE */
107 #define _PAGE_CP 0x0000000000000020 /* Cacheable in Physical Cache */
108 #define _PAGE_CV 0x0000000000000010 /* Cacheable in Virtual Cache */
109 #define _PAGE_E 0x0000000000000008 /* side-Effect */
110 #define _PAGE_P 0x0000000000000004 /* Privileged Page */
111 #define _PAGE_W 0x0000000000000002 /* Writable */
112 #define _PAGE_G 0x0000000000000001 /* Global */
113
114 /* Here are the SpitFire software bits we use in the TTE's. */
115 #define _PAGE_MODIFIED 0x0000000000000800 /* Modified Page (ie. dirty) */
116 #define _PAGE_ACCESSED 0x0000000000000400 /* Accessed Page (ie. referenced) */
117 #define _PAGE_READ 0x0000000000000200 /* Readable SW Bit */
118 #define _PAGE_WRITE 0x0000000000000100 /* Writable SW Bit */
119 #define _PAGE_PRESENT 0x0000000000000080 /* Present Page (ie. not swapped out) */
120
121 #if PAGE_SHIFT == 13
122 #define _PAGE_SZBITS _PAGE_SZ8K
123 #elif PAGE_SHIFT == 16
124 #define _PAGE_SZBITS _PAGE_SZ64K
125 #elif PAGE_SHIFT == 19
126 #define _PAGE_SZBITS _PAGE_SZ512K
127 #elif PAGE_SHIFT == 22
128 #define _PAGE_SZBITS _PAGE_SZ4M
129 #else
130 #error Wrong PAGE_SHIFT specified
131 #endif
132
133 #define _PAGE_CACHE (_PAGE_CP | _PAGE_CV)
134
135 #define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W)
136 #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
137 #define __PRIV_BITS _PAGE_P
138
139 #define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED)
140
141 /* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */
142 #define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
143 __ACCESS_BITS | _PAGE_WRITE)
144
145 #define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
146 __ACCESS_BITS)
147
148 #define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
149 __ACCESS_BITS)
150
151 #define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
152 __PRIV_BITS | __ACCESS_BITS | __DIRTY_BITS)
153
154 #define PAGE_INVALID __pgprot (0)
155
156 #define _PFN_MASK _PAGE_PADDR
157
158 #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_MODIFIED | _PAGE_ACCESSED | _PAGE_PRESENT | _PAGE_SZBITS)
159
160 #define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | __ACCESS_BITS | _PAGE_E)
161
162 #define __P000 PAGE_NONE
163 #define __P001 PAGE_READONLY
164 #define __P010 PAGE_COPY
165 #define __P011 PAGE_COPY
166 #define __P100 PAGE_READONLY
167 #define __P101 PAGE_READONLY
168 #define __P110 PAGE_COPY
169 #define __P111 PAGE_COPY
170
171 #define __S000 PAGE_NONE
172 #define __S001 PAGE_READONLY
173 #define __S010 PAGE_SHARED
174 #define __S011 PAGE_SHARED
175 #define __S100 PAGE_READONLY
176 #define __S101 PAGE_READONLY
177 #define __S110 PAGE_SHARED
178 #define __S111 PAGE_SHARED
179
180 #ifndef __ASSEMBLY__
181
182 extern unsigned long phys_base;
183
184 extern struct page *mem_map_zero;
185 #define ZERO_PAGE(vaddr) (mem_map_zero)
186
187 /* Warning: These take pointers to page structs now... */
188 #define mk_pte(page, pgprot) \
189 __pte((((page - mem_map) << PAGE_SHIFT)+phys_base) | pgprot_val(pgprot) | _PAGE_SZBITS)
190 #define page_pte_prot(page, prot) mk_pte(page, prot)
191 #define page_pte(page) page_pte_prot(page, __pgprot(0))
192
193 #define mk_pte_phys(physpage, pgprot) (__pte((physpage) | pgprot_val(pgprot) | _PAGE_SZBITS))
194
195 extern inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
196 {
197 pte_t __pte;
198
199 pte_val(__pte) = (pte_val(orig_pte) & _PAGE_CHG_MASK) |
200 pgprot_val(new_prot);
201
202 return __pte;
203 }
204 #define pmd_set(pmdp, ptep) \
205 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
206 #define pgd_set(pgdp, pmdp) \
207 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
208 #define pmd_page(pmd) ((unsigned long) __va((pmd_val(pmd)<<11UL)))
209 #define pgd_page(pgd) ((unsigned long) __va((pgd_val(pgd)<<11UL)))
210 #define pte_none(pte) (!pte_val(pte))
211 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
212 #define pte_clear(pte) (pte_val(*(pte)) = 0UL)
213 #define pmd_none(pmd) (!pmd_val(pmd))
214 #define pmd_bad(pmd) (0)
215 #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
216 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
217 #define pgd_none(pgd) (!pgd_val(pgd))
218 #define pgd_bad(pgd) (0)
219 #define pgd_present(pgd) (pgd_val(pgd) != 0UL)
220 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
221
222 /* The following only work if pte_present() is true.
223 * Undefined behaviour if not..
224 */
225 #define pte_read(pte) (pte_val(pte) & _PAGE_READ)
226 #define pte_exec(pte) pte_read(pte)
227 #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
228 #define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
229 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
230 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
231 #define pte_rdprotect(pte) (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
232 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
233 #define pte_mkold(pte) (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
234
235 /* Permanent address of a page. */
236 #define __page_address(page) ((page)->virtual)
237 #define page_address(page) ({ __page_address(page); })
238
239 #define pte_page(x) (mem_map+(((pte_val(x)&_PAGE_PADDR)-phys_base)>>PAGE_SHIFT))
240
241 /* Be very careful when you change these three, they are delicate. */
242 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
243 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE))
244 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
245
246 /* to find an entry in a page-table-directory. */
247 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD))
248 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
249
250 /* to find an entry in a kernel page-table-directory */
251 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
252
253 /* Find an entry in the second-level page table.. */
254 #define pmd_offset(dir, address) ((pmd_t *) pgd_page(*(dir)) + \
255 ((address >> PMD_SHIFT) & (REAL_PTRS_PER_PMD-1)))
256
257 /* Find an entry in the third-level page table.. */
258 #define pte_offset(dir, address) ((pte_t *) pmd_page(*(dir)) + \
259 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
260
261 extern pgd_t swapper_pg_dir[1];
262
263 /* These do nothing with the way I have things setup. */
264 #define mmu_lockarea(vaddr, len) (vaddr)
265 #define mmu_unlockarea(vaddr, len) do { } while(0)
266
267 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
268
269 #define flush_icache_page(vma, pg) do { } while(0)
270
271 /* Make a non-present pseudo-TTE. */
272 extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
273 {
274 pte_t pte;
275 pte_val(pte) = ((page) | pgprot_val(prot) | _PAGE_E) & ~(unsigned long)_PAGE_CACHE;
276 pte_val(pte) |= (((unsigned long)space) << 32);
277 return pte;
278 }
279
280 /* Encode and de-code a swap entry */
281 #define SWP_TYPE(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
282 #define SWP_OFFSET(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
283 #define SWP_ENTRY(type, offset) \
284 ( (swp_entry_t) \
285 { \
286 (((long)(type) << PAGE_SHIFT) | \
287 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
288 } )
289 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
290 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
291
292 extern __inline__ unsigned long
293 sun4u_get_pte (unsigned long addr)
294 {
295 pgd_t *pgdp;
296 pmd_t *pmdp;
297 pte_t *ptep;
298
299 if (addr >= PAGE_OFFSET)
300 return addr & _PAGE_PADDR;
301 pgdp = pgd_offset_k (addr);
302 pmdp = pmd_offset (pgdp, addr);
303 ptep = pte_offset (pmdp, addr);
304 return pte_val (*ptep) & _PAGE_PADDR;
305 }
306
307 extern __inline__ unsigned long
308 __get_phys (unsigned long addr)
309 {
310 return sun4u_get_pte (addr);
311 }
312
313 extern __inline__ int
314 __get_iospace (unsigned long addr)
315 {
316 return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
317 }
318
319 extern unsigned long *sparc64_valid_addr_bitmap;
320
321 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
322 #define kern_addr_valid(addr) \
323 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
324
325 extern int io_remap_page_range(unsigned long from, unsigned long offset,
326 unsigned long size, pgprot_t prot, int space);
327
328 #include <asm-generic/pgtable.h>
329
330 /* We provide our own get_unmapped_area to cope with VA holes for userland */
331 #define HAVE_ARCH_UNMAPPED_AREA
332
333 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
334 * the largest alignment possible such that larget PTEs can be used.
335 */
336 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, unsigned long, unsigned long, unsigned long);
337 #define HAVE_ARCH_FB_UNMAPPED_AREA
338
339 #endif /* !(__ASSEMBLY__) */
340
341 #endif /* !(_SPARC64_PGTABLE_H) */
342