File: /usr/src/linux/include/asm/msr.h

1     #ifndef __ASM_MSR_H
2     #define __ASM_MSR_H
3     
4     /*
5      * Access to machine-specific registers (available on 586 and better only)
6      * Note: the rd* operations modify the parameters directly (without using
7      * pointer indirection), this allows gcc to optimize better
8      */
9     
10     #define rdmsr(msr,val1,val2) \
11          __asm__ __volatile__("rdmsr" \
12     			  : "=a" (val1), "=d" (val2) \
13     			  : "c" (msr))
14     
15     #define wrmsr(msr,val1,val2) \
16          __asm__ __volatile__("wrmsr" \
17     			  : /* no outputs */ \
18     			  : "c" (msr), "a" (val1), "d" (val2))
19     
20     #define rdtsc(low,high) \
21          __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
22     
23     #define rdtscl(low) \
24          __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
25     
26     #define rdtscll(val) \
27          __asm__ __volatile__("rdtsc" : "=A" (val))
28     
29     #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
30     
31     #define rdpmc(counter,low,high) \
32          __asm__ __volatile__("rdpmc" \
33     			  : "=a" (low), "=d" (high) \
34     			  : "c" (counter))
35     
36     /* symbolic names for some interesting MSRs */
37     /* Intel defined MSRs. */
38     #define MSR_IA32_P5_MC_ADDR		0
39     #define MSR_IA32_P5_MC_TYPE		1
40     #define MSR_IA32_PLATFORM_ID		0x17
41     #define MSR_IA32_EBL_CR_POWERON		0x2a
42     
43     #define MSR_IA32_APICBASE		0x1b
44     #define MSR_IA32_APICBASE_BSP		(1<<8)
45     #define MSR_IA32_APICBASE_ENABLE	(1<<11)
46     #define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
47     
48     #define MSR_IA32_UCODE_WRITE		0x79
49     #define MSR_IA32_UCODE_REV		0x8b
50     
51     #define MSR_IA32_PERFCTR0		0xc1
52     #define MSR_IA32_PERFCTR1		0xc2
53     
54     #define MSR_IA32_BBL_CR_CTL		0x119
55     
56     #define MSR_IA32_MCG_CAP		0x179
57     #define MSR_IA32_MCG_STATUS		0x17a
58     #define MSR_IA32_MCG_CTL		0x17b
59     
60     #define MSR_IA32_EVNTSEL0		0x186
61     #define MSR_IA32_EVNTSEL1		0x187
62     
63     #define MSR_IA32_DEBUGCTLMSR		0x1d9
64     #define MSR_IA32_LASTBRANCHFROMIP	0x1db
65     #define MSR_IA32_LASTBRANCHTOIP		0x1dc
66     #define MSR_IA32_LASTINTFROMIP		0x1dd
67     #define MSR_IA32_LASTINTTOIP		0x1de
68     
69     #define MSR_IA32_MC0_CTL		0x400
70     #define MSR_IA32_MC0_STATUS		0x401
71     #define MSR_IA32_MC0_ADDR		0x402
72     #define MSR_IA32_MC0_MISC		0x403
73     
74     /* AMD Defined MSRs */
75     #define MSR_K6_EFER			0xC0000080
76     #define MSR_K6_STAR			0xC0000081
77     #define MSR_K6_WHCR			0xC0000082
78     #define MSR_K6_UWCCR			0xC0000085
79     #define MSR_K6_PSOR			0xC0000087
80     #define MSR_K6_PFIR			0xC0000088
81     
82     #define MSR_K7_EVNTSEL0			0xC0010000
83     #define MSR_K7_PERFCTR0			0xC0010004
84     
85     /* Centaur-Hauls/IDT defined MSRs. */
86     #define MSR_IDT_FCR1			0x107
87     #define MSR_IDT_FCR2			0x108
88     #define MSR_IDT_FCR3			0x109
89     #define MSR_IDT_FCR4			0x10a
90     
91     #define MSR_IDT_MCR0			0x110
92     #define MSR_IDT_MCR1			0x111
93     #define MSR_IDT_MCR2			0x112
94     #define MSR_IDT_MCR3			0x113
95     #define MSR_IDT_MCR4			0x114
96     #define MSR_IDT_MCR5			0x115
97     #define MSR_IDT_MCR6			0x116
98     #define MSR_IDT_MCR7			0x117
99     #define MSR_IDT_MCR_CTRL		0x120
100     
101     /* VIA Cyrix defined MSRs*/
102     #define MSR_VIA_FCR			0x1107
103     
104     #endif /* __ASM_MSR_H */
105