File: /usr/src/linux/include/asm-i386/processor.h
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <linux/cache.h>
18 #include <linux/config.h>
19 #include <linux/threads.h>
20
21 /*
22 * Default implementation of macro that returns current
23 * instruction pointer ("program counter").
24 */
25 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
26
27 /*
28 * CPU type and hardware bug flags. Kept separately for each CPU.
29 * Members of this structure are referenced in head.S, so think twice
30 * before touching them. [mj]
31 */
32
33 struct cpuinfo_x86 {
34 __u8 x86; /* CPU family */
35 __u8 x86_vendor; /* CPU vendor */
36 __u8 x86_model;
37 __u8 x86_mask;
38 char wp_works_ok; /* It doesn't on 386's */
39 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
40 char hard_math;
41 char rfu;
42 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
43 __u32 x86_capability[NCAPINTS];
44 char x86_vendor_id[16];
45 char x86_model_id[64];
46 int x86_cache_size; /* in KB - valid for CPUS which support this
47 call */
48 int fdiv_bug;
49 int f00f_bug;
50 int coma_bug;
51 unsigned long loops_per_jiffy;
52 unsigned long *pgd_quick;
53 unsigned long *pmd_quick;
54 unsigned long *pte_quick;
55 unsigned long pgtable_cache_sz;
56 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
57
58 #define X86_VENDOR_INTEL 0
59 #define X86_VENDOR_CYRIX 1
60 #define X86_VENDOR_AMD 2
61 #define X86_VENDOR_UMC 3
62 #define X86_VENDOR_NEXGEN 4
63 #define X86_VENDOR_CENTAUR 5
64 #define X86_VENDOR_RISE 6
65 #define X86_VENDOR_TRANSMETA 7
66 #define X86_VENDOR_UNKNOWN 0xff
67
68 /*
69 * capabilities of CPUs
70 */
71
72 extern struct cpuinfo_x86 boot_cpu_data;
73 extern struct tss_struct init_tss[NR_CPUS];
74
75 #ifdef CONFIG_SMP
76 extern struct cpuinfo_x86 cpu_data[];
77 #define current_cpu_data cpu_data[smp_processor_id()]
78 #else
79 #define cpu_data &boot_cpu_data
80 #define current_cpu_data boot_cpu_data
81 #endif
82
83 #define cpu_has_pge (test_bit(X86_FEATURE_PGE, boot_cpu_data.x86_capability))
84 #define cpu_has_pse (test_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability))
85 #define cpu_has_pae (test_bit(X86_FEATURE_PAE, boot_cpu_data.x86_capability))
86 #define cpu_has_tsc (test_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability))
87 #define cpu_has_de (test_bit(X86_FEATURE_DE, boot_cpu_data.x86_capability))
88 #define cpu_has_vme (test_bit(X86_FEATURE_VME, boot_cpu_data.x86_capability))
89 #define cpu_has_fxsr (test_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability))
90 #define cpu_has_xmm (test_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability))
91 #define cpu_has_fpu (test_bit(X86_FEATURE_FPU, boot_cpu_data.x86_capability))
92 #define cpu_has_apic (test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability))
93
94 extern char ignore_irq13;
95
96 extern void identify_cpu(struct cpuinfo_x86 *);
97 extern void print_cpu_info(struct cpuinfo_x86 *);
98 extern void dodgy_tsc(void);
99
100 /*
101 * EFLAGS bits
102 */
103 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
104 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
105 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
106 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
107 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
108 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
109 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
110 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
111 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
112 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
113 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
114 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
115 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
116 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
117 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
118 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
119 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
120
121 /*
122 * Generic CPUID function
123 */
124 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
125 {
126 __asm__("cpuid"
127 : "=a" (*eax),
128 "=b" (*ebx),
129 "=c" (*ecx),
130 "=d" (*edx)
131 : "0" (op));
132 }
133
134 /*
135 * CPUID functions returning a single datum
136 */
137 static inline unsigned int cpuid_eax(unsigned int op)
138 {
139 unsigned int eax;
140
141 __asm__("cpuid"
142 : "=a" (eax)
143 : "0" (op)
144 : "bx", "cx", "dx");
145 return eax;
146 }
147 static inline unsigned int cpuid_ebx(unsigned int op)
148 {
149 unsigned int eax, ebx;
150
151 __asm__("cpuid"
152 : "=a" (eax), "=b" (ebx)
153 : "0" (op)
154 : "cx", "dx" );
155 return ebx;
156 }
157 static inline unsigned int cpuid_ecx(unsigned int op)
158 {
159 unsigned int eax, ecx;
160
161 __asm__("cpuid"
162 : "=a" (eax), "=c" (ecx)
163 : "0" (op)
164 : "bx", "dx" );
165 return ecx;
166 }
167 static inline unsigned int cpuid_edx(unsigned int op)
168 {
169 unsigned int eax, edx;
170
171 __asm__("cpuid"
172 : "=a" (eax), "=d" (edx)
173 : "0" (op)
174 : "bx", "cx");
175 return edx;
176 }
177
178 /*
179 * Intel CPU features in CR4
180 */
181 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
182 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
183 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
184 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
185 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
186 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
187 #define X86_CR4_MCE 0x0040 /* Machine check enable */
188 #define X86_CR4_PGE 0x0080 /* enable global pages */
189 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
190 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
191 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
192
193 /*
194 * Save the cr4 feature set we're using (ie
195 * Pentium 4MB enable and PPro Global page
196 * enable), so that any CPU's that boot up
197 * after us can get the correct flags.
198 */
199 extern unsigned long mmu_cr4_features;
200
201 static inline void set_in_cr4 (unsigned long mask)
202 {
203 mmu_cr4_features |= mask;
204 __asm__("movl %%cr4,%%eax\n\t"
205 "orl %0,%%eax\n\t"
206 "movl %%eax,%%cr4\n"
207 : : "irg" (mask)
208 :"ax");
209 }
210
211 static inline void clear_in_cr4 (unsigned long mask)
212 {
213 mmu_cr4_features &= ~mask;
214 __asm__("movl %%cr4,%%eax\n\t"
215 "andl %0,%%eax\n\t"
216 "movl %%eax,%%cr4\n"
217 : : "irg" (~mask)
218 :"ax");
219 }
220
221 /*
222 * Cyrix CPU configuration register indexes
223 */
224 #define CX86_CCR0 0xc0
225 #define CX86_CCR1 0xc1
226 #define CX86_CCR2 0xc2
227 #define CX86_CCR3 0xc3
228 #define CX86_CCR4 0xe8
229 #define CX86_CCR5 0xe9
230 #define CX86_CCR6 0xea
231 #define CX86_CCR7 0xeb
232 #define CX86_DIR0 0xfe
233 #define CX86_DIR1 0xff
234 #define CX86_ARR_BASE 0xc4
235 #define CX86_RCR_BASE 0xdc
236
237 /*
238 * Cyrix CPU indexed register access macros
239 */
240
241 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
242
243 #define setCx86(reg, data) do { \
244 outb((reg), 0x22); \
245 outb((data), 0x23); \
246 } while (0)
247
248 /*
249 * Bus types (default is ISA, but people can check others with these..)
250 */
251 #ifdef CONFIG_EISA
252 extern int EISA_bus;
253 #else
254 #define EISA_bus (0)
255 #endif
256 extern int MCA_bus;
257
258 /* from system description table in BIOS. Mostly for MCA use, but
259 others may find it useful. */
260 extern unsigned int machine_id;
261 extern unsigned int machine_submodel_id;
262 extern unsigned int BIOS_revision;
263 extern unsigned int mca_pentium_flag;
264
265 /*
266 * User space process size: 3GB (default).
267 */
268 #define TASK_SIZE (PAGE_OFFSET)
269
270 /* This decides where the kernel will search for a free chunk of vm
271 * space during mmap's.
272 */
273 #define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
274
275 /*
276 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
277 */
278 #define IO_BITMAP_SIZE 32
279 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
280 #define INVALID_IO_BITMAP_OFFSET 0x8000
281
282 struct i387_fsave_struct {
283 long cwd;
284 long swd;
285 long twd;
286 long fip;
287 long fcs;
288 long foo;
289 long fos;
290 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
291 long status; /* software status information */
292 };
293
294 struct i387_fxsave_struct {
295 unsigned short cwd;
296 unsigned short swd;
297 unsigned short twd;
298 unsigned short fop;
299 long fip;
300 long fcs;
301 long foo;
302 long fos;
303 long mxcsr;
304 long reserved;
305 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
306 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
307 long padding[56];
308 } __attribute__ ((aligned (16)));
309
310 struct i387_soft_struct {
311 long cwd;
312 long swd;
313 long twd;
314 long fip;
315 long fcs;
316 long foo;
317 long fos;
318 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
319 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
320 struct info *info;
321 unsigned long entry_eip;
322 };
323
324 union i387_union {
325 struct i387_fsave_struct fsave;
326 struct i387_fxsave_struct fxsave;
327 struct i387_soft_struct soft;
328 };
329
330 typedef struct {
331 unsigned long seg;
332 } mm_segment_t;
333
334 struct tss_struct {
335 unsigned short back_link,__blh;
336 unsigned long esp0;
337 unsigned short ss0,__ss0h;
338 unsigned long esp1;
339 unsigned short ss1,__ss1h;
340 unsigned long esp2;
341 unsigned short ss2,__ss2h;
342 unsigned long __cr3;
343 unsigned long eip;
344 unsigned long eflags;
345 unsigned long eax,ecx,edx,ebx;
346 unsigned long esp;
347 unsigned long ebp;
348 unsigned long esi;
349 unsigned long edi;
350 unsigned short es, __esh;
351 unsigned short cs, __csh;
352 unsigned short ss, __ssh;
353 unsigned short ds, __dsh;
354 unsigned short fs, __fsh;
355 unsigned short gs, __gsh;
356 unsigned short ldt, __ldth;
357 unsigned short trace, bitmap;
358 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
359 /*
360 * pads the TSS to be cacheline-aligned (size is 0x100)
361 */
362 unsigned long __cacheline_filler[5];
363 };
364
365 struct thread_struct {
366 unsigned long esp0;
367 unsigned long eip;
368 unsigned long esp;
369 unsigned long fs;
370 unsigned long gs;
371 /* Hardware debugging registers */
372 unsigned long debugreg[8]; /* %%db0-7 debug registers */
373 /* fault info */
374 unsigned long cr2, trap_no, error_code;
375 /* floating point info */
376 union i387_union i387;
377 /* virtual 86 mode info */
378 struct vm86_struct * vm86_info;
379 unsigned long screen_bitmap;
380 unsigned long v86flags, v86mask, v86mode, saved_esp0;
381 /* IO permissions */
382 int ioperm;
383 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
384 };
385
386 #define INIT_THREAD { \
387 0, \
388 0, 0, 0, 0, \
389 { [0 ... 7] = 0 }, /* debugging registers */ \
390 0, 0, 0, \
391 { { 0, }, }, /* 387 state */ \
392 0,0,0,0,0,0, \
393 0,{~0,} /* io permissions */ \
394 }
395
396 #define INIT_TSS { \
397 0,0, /* back_link, __blh */ \
398 sizeof(init_stack) + (long) &init_stack, /* esp0 */ \
399 __KERNEL_DS, 0, /* ss0 */ \
400 0,0,0,0,0,0, /* stack1, stack2 */ \
401 0, /* cr3 */ \
402 0,0, /* eip,eflags */ \
403 0,0,0,0, /* eax,ecx,edx,ebx */ \
404 0,0,0,0, /* esp,ebp,esi,edi */ \
405 0,0,0,0,0,0, /* es,cs,ss */ \
406 0,0,0,0,0,0, /* ds,fs,gs */ \
407 __LDT(0),0, /* ldt */ \
408 0, INVALID_IO_BITMAP_OFFSET, /* tace, bitmap */ \
409 {~0, } /* ioperm */ \
410 }
411
412 #define start_thread(regs, new_eip, new_esp) do { \
413 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
414 set_fs(USER_DS); \
415 regs->xds = __USER_DS; \
416 regs->xes = __USER_DS; \
417 regs->xss = __USER_DS; \
418 regs->xcs = __USER_CS; \
419 regs->eip = new_eip; \
420 regs->esp = new_esp; \
421 } while (0)
422
423 /* Forward declaration, a strange C thing */
424 struct task_struct;
425 struct mm_struct;
426
427 /* Free all resources held by a thread. */
428 extern void release_thread(struct task_struct *);
429 /*
430 * create a kernel thread without removing it from tasklists
431 */
432 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
433
434 /* Copy and release all segment info associated with a VM */
435 extern void copy_segments(struct task_struct *p, struct mm_struct * mm);
436 extern void release_segments(struct mm_struct * mm);
437
438 /*
439 * Return saved PC of a blocked thread.
440 */
441 static inline unsigned long thread_saved_pc(struct thread_struct *t)
442 {
443 return ((unsigned long *)t->esp)[3];
444 }
445
446 unsigned long get_wchan(struct task_struct *p);
447 #define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
448 #define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
449
450 #define THREAD_SIZE (2*PAGE_SIZE)
451 #define alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
452 #define free_task_struct(p) free_pages((unsigned long) (p), 1)
453 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
454
455 #define init_task (init_task_union.task)
456 #define init_stack (init_task_union.stack)
457
458 struct microcode {
459 unsigned int hdrver;
460 unsigned int rev;
461 unsigned int date;
462 unsigned int sig;
463 unsigned int cksum;
464 unsigned int ldrver;
465 unsigned int pf;
466 unsigned int reserved[5];
467 unsigned int bits[500];
468 };
469
470 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
471 #define MICROCODE_IOCFREE _IO('6',0)
472
473 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
474 static inline void rep_nop(void)
475 {
476 __asm__ __volatile__("rep;nop");
477 }
478
479 /* Prefetch instructions for Pentium III and AMD Athlon */
480 #ifdef CONFIG_MPENTIUMIII
481
482 #define ARCH_HAS_PREFETCH
483 extern inline void prefetch(const void *x)
484 {
485 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
486 }
487
488 #elif CONFIG_X86_USE_3DNOW
489
490 #define ARCH_HAS_PREFETCH
491 #define ARCH_HAS_PREFETCHW
492 #define ARCH_HAS_SPINLOCK_PREFETCH
493
494 extern inline void prefetch(const void *x)
495 {
496 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
497 }
498
499 extern inline void prefetchw(const void *x)
500 {
501 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
502 }
503 #define spin_lock_prefetch(x) prefetchw(x)
504
505 #endif
506
507 #endif /* __ASM_I386_PROCESSOR_H */
508