File: /usr/src/linux/include/linux/synclink.h
1 /*
2 * SyncLink Multiprotocol Serial Adapter Driver
3 *
4 * $Id: synclink.h,v 3.5 2001/03/26 17:04:36 ez Exp $
5 *
6 * Copyright (C) 1998-2000 by Microgate Corporation
7 *
8 * Redistribution of this file is permitted under
9 * the terms of the GNU Public License (GPL)
10 */
11
12 #ifndef _SYNCLINK_H_
13 #define _SYNCLINK_H_
14 #define SYNCLINK_H_VERSION 3.5
15
16 #define BOOLEAN int
17 #define TRUE 1
18 #define FALSE 0
19
20 #define BIT0 0x0001
21 #define BIT1 0x0002
22 #define BIT2 0x0004
23 #define BIT3 0x0008
24 #define BIT4 0x0010
25 #define BIT5 0x0020
26 #define BIT6 0x0040
27 #define BIT7 0x0080
28 #define BIT8 0x0100
29 #define BIT9 0x0200
30 #define BIT10 0x0400
31 #define BIT11 0x0800
32 #define BIT12 0x1000
33 #define BIT13 0x2000
34 #define BIT14 0x4000
35 #define BIT15 0x8000
36 #define BIT16 0x00010000
37 #define BIT17 0x00020000
38 #define BIT18 0x00040000
39 #define BIT19 0x00080000
40 #define BIT20 0x00100000
41 #define BIT21 0x00200000
42 #define BIT22 0x00400000
43 #define BIT23 0x00800000
44 #define BIT24 0x01000000
45 #define BIT25 0x02000000
46 #define BIT26 0x04000000
47 #define BIT27 0x08000000
48 #define BIT28 0x10000000
49 #define BIT29 0x20000000
50 #define BIT30 0x40000000
51 #define BIT31 0x80000000
52
53
54 #define HDLC_MAX_FRAME_SIZE 65535
55 #define MAX_ASYNC_TRANSMIT 4096
56 #define MAX_ASYNC_BUFFER_SIZE 4096
57
58 #define ASYNC_PARITY_NONE 0
59 #define ASYNC_PARITY_EVEN 1
60 #define ASYNC_PARITY_ODD 2
61 #define ASYNC_PARITY_SPACE 3
62
63 #define HDLC_FLAG_UNDERRUN_ABORT7 0x0000
64 #define HDLC_FLAG_UNDERRUN_ABORT15 0x0001
65 #define HDLC_FLAG_UNDERRUN_FLAG 0x0002
66 #define HDLC_FLAG_UNDERRUN_CRC 0x0004
67 #define HDLC_FLAG_SHARE_ZERO 0x0010
68 #define HDLC_FLAG_AUTO_CTS 0x0020
69 #define HDLC_FLAG_AUTO_DCD 0x0040
70 #define HDLC_FLAG_AUTO_RTS 0x0080
71 #define HDLC_FLAG_RXC_DPLL 0x0100
72 #define HDLC_FLAG_RXC_BRG 0x0200
73 #define HDLC_FLAG_RXC_TXCPIN 0x8000
74 #define HDLC_FLAG_RXC_RXCPIN 0x0000
75 #define HDLC_FLAG_TXC_DPLL 0x0400
76 #define HDLC_FLAG_TXC_BRG 0x0800
77 #define HDLC_FLAG_TXC_TXCPIN 0x0000
78 #define HDLC_FLAG_TXC_RXCPIN 0x0008
79 #define HDLC_FLAG_DPLL_DIV8 0x1000
80 #define HDLC_FLAG_DPLL_DIV16 0x2000
81 #define HDLC_FLAG_DPLL_DIV32 0x0000
82 #define HDLC_FLAG_HDLC_LOOPMODE 0x4000
83
84 #define HDLC_CRC_NONE 0
85 #define HDLC_CRC_16_CCITT 1
86 #define HDLC_CRC_32_CCITT 2
87 #define HDLC_CRC_MASK 0x00ff
88 #define HDLC_CRC_RETURN_EX 0x8000
89
90 #define RX_OK 0
91 #define RX_CRC_ERROR 1
92
93 #define HDLC_TXIDLE_FLAGS 0
94 #define HDLC_TXIDLE_ALT_ZEROS_ONES 1
95 #define HDLC_TXIDLE_ZEROS 2
96 #define HDLC_TXIDLE_ONES 3
97 #define HDLC_TXIDLE_ALT_MARK_SPACE 4
98 #define HDLC_TXIDLE_SPACE 5
99 #define HDLC_TXIDLE_MARK 6
100
101 #define HDLC_ENCODING_NRZ 0
102 #define HDLC_ENCODING_NRZB 1
103 #define HDLC_ENCODING_NRZI_MARK 2
104 #define HDLC_ENCODING_NRZI_SPACE 3
105 #define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE
106 #define HDLC_ENCODING_BIPHASE_MARK 4
107 #define HDLC_ENCODING_BIPHASE_SPACE 5
108 #define HDLC_ENCODING_BIPHASE_LEVEL 6
109 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7
110
111 #define HDLC_PREAMBLE_LENGTH_8BITS 0
112 #define HDLC_PREAMBLE_LENGTH_16BITS 1
113 #define HDLC_PREAMBLE_LENGTH_32BITS 2
114 #define HDLC_PREAMBLE_LENGTH_64BITS 3
115
116 #define HDLC_PREAMBLE_PATTERN_NONE 0
117 #define HDLC_PREAMBLE_PATTERN_ZEROS 1
118 #define HDLC_PREAMBLE_PATTERN_FLAGS 2
119 #define HDLC_PREAMBLE_PATTERN_10 3
120 #define HDLC_PREAMBLE_PATTERN_01 4
121 #define HDLC_PREAMBLE_PATTERN_ONES 5
122
123 #define MGSL_MODE_ASYNC 1
124 #define MGSL_MODE_HDLC 2
125 #define MGSL_MODE_RAW 6
126
127 #define MGSL_BUS_TYPE_ISA 1
128 #define MGSL_BUS_TYPE_EISA 2
129 #define MGSL_BUS_TYPE_PCI 5
130
131 typedef struct _MGSL_PARAMS
132 {
133 /* Common */
134
135 unsigned long mode; /* Asynchronous or HDLC */
136 unsigned char loopback; /* internal loopback mode */
137
138 /* HDLC Only */
139
140 unsigned short flags;
141 unsigned char encoding; /* NRZ, NRZI, etc. */
142 unsigned long clock_speed; /* external clock speed in bits per second */
143 unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */
144 unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */
145 unsigned char preamble_length;
146 unsigned char preamble;
147
148 /* Async Only */
149
150 unsigned long data_rate; /* bits per second */
151 unsigned char data_bits; /* 7 or 8 data bits */
152 unsigned char stop_bits; /* 1 or 2 stop bits */
153 unsigned char parity; /* none, even, or odd */
154
155 } MGSL_PARAMS, *PMGSL_PARAMS;
156
157 #define MICROGATE_VENDOR_ID 0x13c0
158 #define SYNCLINK_DEVICE_ID 0x0010
159 #define MGSCC_DEVICE_ID 0x0020
160 #define SYNCLINK_SCA_DEVICE_ID 0x0030
161 #define MGSL_MAX_SERIAL_NUMBER 30
162
163 /*
164 ** device diagnostics status
165 */
166
167 #define DiagStatus_OK 0
168 #define DiagStatus_AddressFailure 1
169 #define DiagStatus_AddressConflict 2
170 #define DiagStatus_IrqFailure 3
171 #define DiagStatus_IrqConflict 4
172 #define DiagStatus_DmaFailure 5
173 #define DiagStatus_DmaConflict 6
174 #define DiagStatus_PciAdapterNotFound 7
175 #define DiagStatus_CantAssignPciResources 8
176 #define DiagStatus_CantAssignPciMemAddr 9
177 #define DiagStatus_CantAssignPciIoAddr 10
178 #define DiagStatus_CantAssignPciIrq 11
179 #define DiagStatus_MemoryError 12
180
181 #define SerialSignal_DCD 0x01 /* Data Carrier Detect */
182 #define SerialSignal_TXD 0x02 /* Transmit Data */
183 #define SerialSignal_RI 0x04 /* Ring Indicator */
184 #define SerialSignal_RXD 0x08 /* Receive Data */
185 #define SerialSignal_CTS 0x10 /* Clear to Send */
186 #define SerialSignal_RTS 0x20 /* Request to Send */
187 #define SerialSignal_DSR 0x40 /* Data Set Ready */
188 #define SerialSignal_DTR 0x80 /* Data Terminal Ready */
189
190
191 /*
192 * Counters of the input lines (CTS, DSR, RI, CD) interrupts
193 */
194 struct mgsl_icount {
195 __u32 cts, dsr, rng, dcd, tx, rx;
196 __u32 frame, parity, overrun, brk;
197 __u32 buf_overrun;
198 __u32 txok;
199 __u32 txunder;
200 __u32 txabort;
201 __u32 txtimeout;
202 __u32 rxshort;
203 __u32 rxlong;
204 __u32 rxabort;
205 __u32 rxover;
206 __u32 rxcrc;
207 __u32 rxok;
208 __u32 exithunt;
209 __u32 rxidle;
210 };
211
212
213 #define DEBUG_LEVEL_DATA 1
214 #define DEBUG_LEVEL_ERROR 2
215 #define DEBUG_LEVEL_INFO 3
216 #define DEBUG_LEVEL_BH 4
217 #define DEBUG_LEVEL_ISR 5
218
219 /*
220 ** Event bit flags for use with MgslWaitEvent
221 */
222
223 #define MgslEvent_DsrActive 0x0001
224 #define MgslEvent_DsrInactive 0x0002
225 #define MgslEvent_Dsr 0x0003
226 #define MgslEvent_CtsActive 0x0004
227 #define MgslEvent_CtsInactive 0x0008
228 #define MgslEvent_Cts 0x000c
229 #define MgslEvent_DcdActive 0x0010
230 #define MgslEvent_DcdInactive 0x0020
231 #define MgslEvent_Dcd 0x0030
232 #define MgslEvent_RiActive 0x0040
233 #define MgslEvent_RiInactive 0x0080
234 #define MgslEvent_Ri 0x00c0
235 #define MgslEvent_ExitHuntMode 0x0100
236 #define MgslEvent_IdleReceived 0x0200
237
238 /* Private IOCTL codes:
239 *
240 * MGSL_IOCSPARAMS set MGSL_PARAMS structure values
241 * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values
242 * MGSL_IOCSTXIDLE set current transmit idle mode
243 * MGSL_IOCGTXIDLE get current transmit idle mode
244 * MGSL_IOCTXENABLE enable or disable transmitter
245 * MGSL_IOCRXENABLE enable or disable receiver
246 * MGSL_IOCTXABORT abort transmitting frame (HDLC)
247 * MGSL_IOCGSTATS return current statistics
248 * MGSL_IOCWAITEVENT wait for specified event to occur
249 * MGSL_LOOPTXDONE transmit in HDLC LoopMode done
250 */
251 #define MGSL_MAGIC_IOC 'm'
252 #define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS)
253 #define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS)
254 #define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2)
255 #define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3)
256 #define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4)
257 #define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5)
258 #define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6)
259 #define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7)
260 #define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int)
261 #define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15)
262 #define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9)
263
264 #endif /* _SYNCLINK_H_ */
265