File: /usr/src/linux/include/asm-mips64/mipsregs.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 1999 by Ralf Baechle
7 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 */
10 #ifndef _ASM_MIPSREGS_H
11 #define _ASM_MIPSREGS_H
12
13 #include <linux/linkage.h>
14
15 /*
16 * The following macros are especially useful for __asm__
17 * inline assembler.
18 */
19 #ifndef __STR
20 #define __STR(x) #x
21 #endif
22 #ifndef STR
23 #define STR(x) __STR(x)
24 #endif
25
26 /*
27 * Coprocessor 0 register names
28 */
29 #define CP0_INDEX $0
30 #define CP0_RANDOM $1
31 #define CP0_ENTRYLO0 $2
32 #define CP0_ENTRYLO1 $3
33 #define CP0_CONTEXT $4
34 #define CP0_PAGEMASK $5
35 #define CP0_WIRED $6
36 #define CP0_INFO $7
37 #define CP0_BADVADDR $8
38 #define CP0_COUNT $9
39 #define CP0_ENTRYHI $10
40 #define CP0_COMPARE $11
41 #define CP0_STATUS $12
42 #define CP0_CAUSE $13
43 #define CP0_EPC $14
44 #define CP0_PRID $15
45 #define CP0_CONFIG $16
46 #define CP0_LLADDR $17
47 #define CP0_WATCHLO $18
48 #define CP0_WATCHHI $19
49 #define CP0_XCONTEXT $20
50 #define CP0_FRAMEMASK $21
51 #define CP0_DIAGNOSTIC $22
52 #define CP0_PERFORMANCE $25
53 #define CP0_ECC $26
54 #define CP0_CACHEERR $27
55 #define CP0_TAGLO $28
56 #define CP0_TAGHI $29
57 #define CP0_ERROREPC $30
58
59 /*
60 * Coprocessor 1 (FPU) register names
61 */
62 #define CP1_REVISION $0
63 #define CP1_STATUS $31
64
65 /*
66 * Values for PageMask register
67 */
68 #define PM_4K 0x00000000
69 #define PM_16K 0x00006000
70 #define PM_64K 0x0001e000
71 #define PM_256K 0x0007e000
72 #define PM_1M 0x001fe000
73 #define PM_4M 0x007fe000
74 #define PM_16M 0x01ffe000
75
76 /*
77 * Values used for computation of new tlb entries
78 */
79 #define PL_4K 12
80 #define PL_16K 14
81 #define PL_64K 16
82 #define PL_256K 18
83 #define PL_1M 20
84 #define PL_4M 22
85 #define PL_16M 24
86
87 /*
88 * Macros to access the system control coprocessor
89 */
90 #define read_32bit_cp0_register(source) \
91 ({ int __res; \
92 __asm__ __volatile__( \
93 "mfc0\t%0,"STR(source) \
94 : "=r" (__res)); \
95 __res;})
96
97 #define read_64bit_cp0_register(source) \
98 ({ int __res; \
99 __asm__ __volatile__( \
100 ".set\tmips3\n\t" \
101 "dmfc0\t%0,"STR(source)"\n\t" \
102 ".set\tmips0" \
103 : "=r" (__res)); \
104 __res;})
105
106 #define write_32bit_cp0_register(register,value) \
107 __asm__ __volatile__( \
108 "mtc0\t%0,"STR(register) \
109 : : "r" (value));
110
111 #define write_64bit_cp0_register(register,value) \
112 __asm__ __volatile__( \
113 ".set\tmips3\n\t" \
114 "dmtc0\t%0,"STR(register)"\n\t" \
115 ".set\tmips0" \
116 : : "r" (value))
117
118 /*
119 * R4x00 interrupt enable / cause bits
120 */
121 #define IE_SW0 (1<< 8)
122 #define IE_SW1 (1<< 9)
123 #define IE_IRQ0 (1<<10)
124 #define IE_IRQ1 (1<<11)
125 #define IE_IRQ2 (1<<12)
126 #define IE_IRQ3 (1<<13)
127 #define IE_IRQ4 (1<<14)
128 #define IE_IRQ5 (1<<15)
129
130 /*
131 * R4x00 interrupt cause bits
132 */
133 #define C_SW0 (1<< 8)
134 #define C_SW1 (1<< 9)
135 #define C_IRQ0 (1<<10)
136 #define C_IRQ1 (1<<11)
137 #define C_IRQ2 (1<<12)
138 #define C_IRQ3 (1<<13)
139 #define C_IRQ4 (1<<14)
140 #define C_IRQ5 (1<<15)
141
142 #ifndef _LANGUAGE_ASSEMBLY
143 /*
144 * Manipulate the status register.
145 * Mostly used to access the interrupt bits.
146 */
147 #define __BUILD_SET_CP0(name,register) \
148 extern __inline__ unsigned int \
149 set_cp0_##name(unsigned int change, unsigned int new) \
150 { \
151 unsigned int res; \
152 \
153 res = read_32bit_cp0_register(register); \
154 res &= ~change; \
155 res |= (new & change); \
156 write_32bit_cp0_register(register, res); \
157 \
158 return res; \
159 }
160
161 __BUILD_SET_CP0(status,CP0_STATUS)
162 __BUILD_SET_CP0(cause,CP0_CAUSE)
163 __BUILD_SET_CP0(config,CP0_CONFIG)
164
165 #endif /* defined (_LANGUAGE_ASSEMBLY) */
166
167 /*
168 * Bitfields in the R4xx0 cp0 status register
169 */
170 #define ST0_IE 0x00000001
171 #define ST0_EXL 0x00000002
172 #define ST0_ERL 0x00000004
173 #define ST0_KSU 0x00000018
174 # define KSU_USER 0x00000010
175 # define KSU_SUPERVISOR 0x00000008
176 # define KSU_KERNEL 0x00000000
177 #define ST0_UX 0x00000020
178 #define ST0_SX 0x00000040
179 #define ST0_KX 0x00000080
180 #define ST0_DE 0x00010000
181 #define ST0_CE 0x00020000
182
183 /*
184 * Status register bits available in all MIPS CPUs.
185 */
186 #define ST0_IM 0x0000ff00
187 #define STATUSB_IP0 8
188 #define STATUSF_IP0 (1 << 8)
189 #define STATUSB_IP1 9
190 #define STATUSF_IP1 (1 << 9)
191 #define STATUSB_IP2 10
192 #define STATUSF_IP2 (1 << 10)
193 #define STATUSB_IP3 11
194 #define STATUSF_IP3 (1 << 11)
195 #define STATUSB_IP4 12
196 #define STATUSF_IP4 (1 << 12)
197 #define STATUSB_IP5 13
198 #define STATUSF_IP5 (1 << 13)
199 #define STATUSB_IP6 14
200 #define STATUSF_IP6 (1 << 14)
201 #define STATUSB_IP7 15
202 #define STATUSF_IP7 (1 << 15)
203 #define ST0_CH 0x00040000
204 #define ST0_SR 0x00100000
205 #define ST0_TS 0x00200000
206 #define ST0_BEV 0x00400000
207 #define ST0_RE 0x02000000
208 #define ST0_FR 0x04000000
209 #define ST0_CU 0xf0000000
210 #define ST0_CU0 0x10000000
211 #define ST0_CU1 0x20000000
212 #define ST0_CU2 0x40000000
213 #define ST0_CU3 0x80000000
214 #define ST0_XX 0x80000000 /* MIPS IV naming */
215
216 /*
217 * Bitfields and bit numbers in the coprocessor 0 cause register.
218 *
219 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
220 */
221 #define CAUSEB_EXCCODE 2
222 #define CAUSEF_EXCCODE (31 << 2)
223 #define CAUSEB_IP 8
224 #define CAUSEF_IP (255 << 8)
225 #define CAUSEB_IP0 8
226 #define CAUSEF_IP0 (1 << 8)
227 #define CAUSEB_IP1 9
228 #define CAUSEF_IP1 (1 << 9)
229 #define CAUSEB_IP2 10
230 #define CAUSEF_IP2 (1 << 10)
231 #define CAUSEB_IP3 11
232 #define CAUSEF_IP3 (1 << 11)
233 #define CAUSEB_IP4 12
234 #define CAUSEF_IP4 (1 << 12)
235 #define CAUSEB_IP5 13
236 #define CAUSEF_IP5 (1 << 13)
237 #define CAUSEB_IP6 14
238 #define CAUSEF_IP6 (1 << 14)
239 #define CAUSEB_IP7 15
240 #define CAUSEF_IP7 (1 << 15)
241 #define CAUSEB_IV 23
242 #define CAUSEF_IV (1 << 23)
243 #define CAUSEB_CE 28
244 #define CAUSEF_CE (3 << 28)
245 #define CAUSEB_BD 31
246 #define CAUSEF_BD (1 << 31)
247
248 /*
249 * Bits in the coprocessor 0 config register.
250 */
251 #define CONF_CM_CACHABLE_NO_WA 0
252 #define CONF_CM_CACHABLE_WA 1
253 #define CONF_CM_UNCACHED 2
254 #define CONF_CM_CACHABLE_NONCOHERENT 3
255 #define CONF_CM_CACHABLE_CE 4
256 #define CONF_CM_CACHABLE_COW 5
257 #define CONF_CM_CACHABLE_CUW 6
258 #define CONF_CM_CACHABLE_ACCELERATED 7
259 #define CONF_CM_CMASK 7
260 #define CONF_DB (1 << 4)
261 #define CONF_IB (1 << 5)
262 #define CONF_SC (1 << 17)
263
264 /*
265 * R10000 performance counter definitions.
266 *
267 * FIXME: The R10000 performance counter opens a nice way to implement CPU
268 * time accounting with a precision of one cycle. I don't have
269 * R10000 silicon but just a manual, so ...
270 */
271
272 /*
273 * Events counted by counter #0
274 */
275 #define CE0_CYCLES 0
276 #define CE0_INSN_ISSUED 1
277 #define CE0_LPSC_ISSUED 2
278 #define CE0_S_ISSUED 3
279 #define CE0_SC_ISSUED 4
280 #define CE0_SC_FAILED 5
281 #define CE0_BRANCH_DECODED 6
282 #define CE0_QW_WB_SECONDARY 7
283 #define CE0_CORRECTED_ECC_ERRORS 8
284 #define CE0_ICACHE_MISSES 9
285 #define CE0_SCACHE_I_MISSES 10
286 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
287 #define CE0_EXT_INTERVENTIONS_REQ 12
288 #define CE0_EXT_INVALIDATE_REQ 13
289 #define CE0_VIRTUAL_COHERENCY_COND 14
290 #define CE0_INSN_GRADUATED 15
291
292 /*
293 * Events counted by counter #1
294 */
295 #define CE1_CYCLES 0
296 #define CE1_INSN_GRADUATED 1
297 #define CE1_LPSC_GRADUATED 2
298 #define CE1_S_GRADUATED 3
299 #define CE1_SC_GRADUATED 4
300 #define CE1_FP_INSN_GRADUATED 5
301 #define CE1_QW_WB_PRIMARY 6
302 #define CE1_TLB_REFILL 7
303 #define CE1_BRANCH_MISSPREDICTED 8
304 #define CE1_DCACHE_MISS 9
305 #define CE1_SCACHE_D_MISSES 10
306 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
307 #define CE1_EXT_INTERVENTION_HITS 12
308 #define CE1_EXT_INVALIDATE_REQ 13
309 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
310 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
311
312 /*
313 * These flags define in which priviledge mode the counters count events
314 */
315 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
316 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
317 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
318 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
319
320 #ifndef _LANGUAGE_ASSEMBLY
321 /*
322 * Functions to access the performance counter and control registers
323 */
324 extern asmlinkage unsigned int read_perf_cntr(unsigned int counter);
325 extern asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val);
326 extern asmlinkage unsigned int read_perf_cntl(unsigned int counter);
327 extern asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val);
328 #endif
329
330 #endif /* _ASM_MIPSREGS_H */
331