File: /usr/src/linux/arch/mips/ddb5074/irq.c
1 /*
2 * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7 #include <linux/config.h>
8 #include <linux/init.h>
9 #include <linux/signal.h>
10 #include <linux/sched.h>
11 #include <linux/types.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
14
15 #include <asm/io.h>
16 #include <asm/irq.h>
17 #include <asm/ptrace.h>
18 #include <asm/nile4.h>
19 #include <asm/ddb5074.h>
20
21
22 extern void __init i8259_init(void);
23 extern void i8259_disable_irq(unsigned int irq_nr);
24 extern void i8259_enable_irq(unsigned int irq_nr);
25
26 extern asmlinkage void ddbIRQ(void);
27 extern asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs);
28 extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
29
30
31 void no_action(int cpl, void *dev_id, struct pt_regs *regs)
32 {
33 }
34
35
36 #define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
37 #define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
38 #define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
39
40 #define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
41 #define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
42 #define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
43
44 #define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
45 #define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
46
47 #define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
48 #define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
49
50 #define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
51 #define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
52
53
54 static void m1543_irq_setup(void)
55 {
56 /*
57 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
58 * the possible IO sources in the M1543 are in use by us. We will
59 * use the following mapping:
60 *
61 * IRQ1 - keyboard (default set by M1543)
62 * IRQ3 - reserved for UART B (default set by M1543) (note that
63 * the schematics for the DDB Vrc-5074 board seem to
64 * indicate that IRQ3 is connected to the DS1386
65 * watchdog timer interrupt output so we might have
66 * a conflict)
67 * IRQ4 - reserved for UART A (default set by M1543)
68 * IRQ5 - parallel (default set by M1543)
69 * IRQ8 - DS1386 time of day (RTC) interrupt
70 * IRQ12 - mouse
71 */
72
73 /*
74 * Assing mouse interrupt to IRQ12
75 */
76
77 /* Enter configuration mode */
78 outb(0x51, M1543_PNP_CONFIG);
79 outb(0x23, M1543_PNP_CONFIG);
80
81 /* Select logical device 7 (Keyboard) */
82 outb(0x07, M1543_PNP_INDEX);
83 outb(0x07, M1543_PNP_DATA);
84
85 /* Select IRQ12 */
86 outb(0x72, M1543_PNP_INDEX);
87 outb(0x0c, M1543_PNP_DATA);
88
89 /* Leave configration mode */
90 outb(0xbb, M1543_PNP_CONFIG);
91
92
93 /* Initialize the 8259 PIC in the M1543 */
94 i8259_init();
95
96 /* Enable the interrupt cascade */
97 nile4_enable_irq(NILE4_INT_INTE);
98
99 request_region(M1543_PNP_CONFIG, 2, "M1543 config");
100 request_region(M1543_INT1_MASTER_ELCR, 2, "pic ELCR");
101 }
102
103 static void nile4_irq_setup(void)
104 {
105 int i;
106
107 /* Map all interrupts to CPU int #0 */
108 nile4_map_irq_all(0);
109
110 /* PCI INTA#-E# must be level triggered */
111 nile4_set_pci_irq_level_or_edge(0, 1);
112 nile4_set_pci_irq_level_or_edge(1, 1);
113 nile4_set_pci_irq_level_or_edge(2, 1);
114 nile4_set_pci_irq_level_or_edge(3, 1);
115 nile4_set_pci_irq_level_or_edge(4, 1);
116
117 /* PCI INTA#-D# must be active low, INTE# must be active high */
118 nile4_set_pci_irq_polarity(0, 0);
119 nile4_set_pci_irq_polarity(1, 0);
120 nile4_set_pci_irq_polarity(2, 0);
121 nile4_set_pci_irq_polarity(3, 0);
122 nile4_set_pci_irq_polarity(4, 1);
123
124 for (i = 0; i < 16; i++)
125 nile4_clear_irq(i);
126
127 /* Enable CPU int #0 */
128 nile4_enable_irq_output(0);
129
130 request_mem_region(NILE4_BASE, NILE4_SIZE, "Nile 4");
131 }
132
133
134 /*
135 * IRQ2 is cascade interrupt to second interrupt controller
136 */
137 static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL };
138
139
140 void disable_irq(unsigned int irq_nr)
141 {
142 if (is_i8259_irq(irq_nr))
143 i8259_disable_irq(irq_nr);
144 else
145 nile4_disable_irq(irq_to_nile4(irq_nr));
146 }
147
148 void enable_irq(unsigned int irq_nr)
149 {
150 if (is_i8259_irq(irq_nr))
151 i8259_enable_irq(irq_nr);
152 else
153 nile4_enable_irq(irq_to_nile4(irq_nr));
154 }
155
156 int table[16] = { 0, };
157
158 void ddb_local0_irqdispatch(struct pt_regs *regs)
159 {
160 u32 mask;
161 int nile4_irq;
162 #if 1
163 volatile static int nesting = 0;
164 if (nesting++ == 0)
165 ddb5074_led_d3(1);
166 ddb5074_led_hex(nesting < 16 ? nesting : 15);
167 #endif
168
169 mask = nile4_get_irq_stat(0);
170 nile4_clear_irq_mask(mask);
171
172 /* Handle the timer interrupt first */
173 if (mask & (1 << NILE4_INT_GPT)) {
174 nile4_disable_irq(NILE4_INT_GPT);
175 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
176 nile4_enable_irq(NILE4_INT_GPT);
177 mask &= ~(1 << NILE4_INT_GPT);
178 }
179 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
180 if (mask & 1) {
181 nile4_disable_irq(nile4_irq);
182 if (nile4_irq == NILE4_INT_INTE) {
183 int i8259_irq = nile4_i8259_iack();
184 i8259_do_irq(i8259_irq, regs);
185 } else
186 do_IRQ(nile4_to_irq(nile4_irq), regs);
187 nile4_enable_irq(nile4_irq);
188 }
189 #if 1
190 if (--nesting == 0)
191 ddb5074_led_d3(0);
192 ddb5074_led_hex(nesting < 16 ? nesting : 15);
193 #endif
194 }
195
196 void ddb_local1_irqdispatch(void)
197 {
198 printk("ddb_local1_irqdispatch called\n");
199 }
200
201 void ddb_buserror_irq(void)
202 {
203 printk("ddb_buserror_irq called\n");
204 }
205
206 void ddb_8254timer_irq(void)
207 {
208 printk("ddb_8254timer_irq called\n");
209 }
210
211 void __init ddb_irq_setup(void)
212 {
213 #ifdef CONFIG_REMOTE_DEBUG
214 if (remote_debug)
215 set_debug_traps();
216 breakpoint(); /* you may move this line to whereever you want :-) */
217 #endif
218 request_region(0x20, 0x20, "pic1");
219 request_region(0xa0, 0x20, "pic2");
220 i8259_setup_irq(2, &irq2);
221
222 nile4_irq_setup();
223 m1543_irq_setup();
224
225 set_except_vector(0, ddbIRQ);
226 }
227