File: /usr/src/linux/arch/mips/ddb5074/pci.c
1 /*
2 * arch/mips/ddb5074/pci.c -- NEC DDB Vrc-5074 PCI access routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Albert Dorofeev <albert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 */
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/types.h>
12 #include <linux/sched.h>
13 #include <linux/ioport.h>
14
15 #include <asm/nile4.h>
16
17
18 static u32 nile4_pre_pci_access0(int slot_num)
19 {
20 u32 pci_addr = 0;
21 u32 virt_addr = NILE4_PCI_CFG_BASE;
22
23 /* Set window 1 address 8000000 - 64 bit - 2 MB (PCI config space) */
24 nile4_set_pdar(NILE4_PCIW1, PHYSADDR(virt_addr), 0x00200000, 64, 0,
25 0);
26 if (slot_num > 2)
27 pci_addr = 0x00040000 << slot_num;
28 else
29 virt_addr += 0x00040000 << slot_num;
30 nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, pci_addr);
31 return virt_addr;
32 }
33
34 static void nile4_post_pci_access0(void)
35 {
36 /*
37 * Set window 1 back to address 8000000 - 64 bit - 128 MB
38 * (PCI IO space)
39 */
40 nile4_set_pdar(NILE4_PCIW1, PHYSADDR(NILE4_PCI_MEM_BASE),
41 0x08000000, 64, 1, 1);
42 nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
43 }
44
45
46 static int nile4_pci_read_config_dword(struct pci_dev *dev,
47 int where, u32 * val)
48 {
49 int slot_num, func_num;
50 u32 base;
51
52 /*
53 * For starters let's do configuration cycle 0 only (one bus only)
54 */
55 if (dev->bus->number)
56 return PCIBIOS_FUNC_NOT_SUPPORTED;
57
58 slot_num = PCI_SLOT(dev->devfn);
59 func_num = PCI_FUNC(dev->devfn);
60 if (slot_num == 5) {
61 /*
62 * This is Nile 4 and it will crash if we access it like other
63 * devices
64 */
65 *val = nile4_in32(NILE4_PCI_BASE + where);
66 return PCIBIOS_SUCCESSFUL;
67 }
68 base = nile4_pre_pci_access0(slot_num);
69 *val =
70 *((volatile u32 *) (base + (func_num << 8) + (where & 0xfc)));
71 nile4_post_pci_access0();
72 return PCIBIOS_SUCCESSFUL;
73 }
74
75 static int nile4_pci_write_config_dword(struct pci_dev *dev, int where,
76 u32 val)
77 {
78 int slot_num, func_num;
79 u32 base;
80
81 /*
82 * For starters let's do configuration cycle 0 only (one bus only)
83 */
84 if (dev->bus->number)
85 return PCIBIOS_FUNC_NOT_SUPPORTED;
86
87 slot_num = PCI_SLOT(dev->devfn);
88 func_num = PCI_FUNC(dev->devfn);
89 if (slot_num == 5) {
90 /*
91 * This is Nile 4 and it will crash if we access it like other
92 * devices
93 */
94 nile4_out32(NILE4_PCI_BASE + where, val);
95 return PCIBIOS_SUCCESSFUL;
96 }
97 base = nile4_pre_pci_access0(slot_num);
98 *((volatile u32 *) (base + (func_num << 8) + (where & 0xfc))) =
99 val;
100 nile4_post_pci_access0();
101 return PCIBIOS_SUCCESSFUL;
102 }
103
104 static int nile4_pci_read_config_word(struct pci_dev *dev, int where,
105 u16 * val)
106 {
107 int status;
108 u32 result;
109
110 status = nile4_pci_read_config_dword(dev, where, &result);
111 if (status != PCIBIOS_SUCCESSFUL)
112 return status;
113 if (where & 2)
114 result >>= 16;
115 *val = result & 0xffff;
116 return PCIBIOS_SUCCESSFUL;
117 }
118
119 static int nile4_pci_read_config_byte(struct pci_dev *dev, int where,
120 u8 * val)
121 {
122 int status;
123 u32 result;
124
125 status = nile4_pci_read_config_dword(dev, where, &result);
126 if (status != PCIBIOS_SUCCESSFUL)
127 return status;
128 if (where & 1)
129 result >>= 8;
130 if (where & 2)
131 result >>= 16;
132 *val = result & 0xff;
133 return PCIBIOS_SUCCESSFUL;
134 }
135
136 static int nile4_pci_write_config_word(struct pci_dev *dev, int where,
137 u16 val)
138 {
139 int status, shift = 0;
140 u32 result;
141
142 status = nile4_pci_read_config_dword(dev, where, &result);
143 if (status != PCIBIOS_SUCCESSFUL)
144 return status;
145 if (where & 2)
146 shift += 16;
147 result &= ~(0xffff << shift);
148 result |= val << shift;
149 return nile4_pci_write_config_dword(dev, where, result);
150 }
151
152 static int nile4_pci_write_config_byte(struct pci_dev *dev, int where,
153 u8 val)
154 {
155 int status, shift = 0;
156 u32 result;
157
158 status = nile4_pci_read_config_dword(dev, where, &result);
159 if (status != PCIBIOS_SUCCESSFUL)
160 return status;
161 if (where & 2)
162 shift += 16;
163 if (where & 1)
164 shift += 8;
165 result &= ~(0xff << shift);
166 result |= val << shift;
167 return nile4_pci_write_config_dword(dev, where, result);
168 }
169
170 struct pci_ops nile4_pci_ops = {
171 nile4_pci_read_config_byte,
172 nile4_pci_read_config_word,
173 nile4_pci_read_config_dword,
174 nile4_pci_write_config_byte,
175 nile4_pci_write_config_word,
176 nile4_pci_write_config_dword
177 };
178
179 struct {
180 struct resource ram;
181 struct resource flash;
182 struct resource isa_io;
183 struct resource pci_io;
184 struct resource isa_mem;
185 struct resource pci_mem;
186 struct resource nile4;
187 struct resource boot;
188 } ddb5074_resources = {
189 { "RAM", 0x00000000, 0x03ffffff,
190 IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64},
191 { "Flash ROM", 0x04000000, 0x043fffff},
192 { "Nile4 ISA I/O", 0x06000000, 0x060fffff},
193 { "Nile4 PCI I/O", 0x06100000, 0x07ffffff},
194 { "Nile4 ISA mem", 0x08000000, 0x08ffffff, IORESOURCE_MEM},
195 { "Nile4 PCI mem", 0x09000000, 0x0fffffff, IORESOURCE_MEM},
196 { "Nile4 ctrl", 0x1fa00000, 0x1fbfffff,
197 IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64},
198 { "Boot ROM", 0x1fc00000, 0x1fffffff}
199 };
200
201 static void __init ddb5074_pci_fixup(void)
202 {
203 struct pci_dev *dev;
204
205 pci_for_each_dev(dev) {
206 if (dev->vendor == PCI_VENDOR_ID_NEC &&
207 dev->device == PCI_DEVICE_ID_NEC_NILE4) {
208 /*
209 * The first 64-bit PCI base register should point to
210 * the Nile4 control registers. Unfortunately this
211 * isn't the case, so we fix it ourselves. This allows
212 * the serial driver to find the UART.
213 */
214 dev->resource[0] = ddb5074_resources.nile4;
215 request_resource(&iomem_resource,
216 &dev->resource[0]);
217 /*
218 * The second 64-bit PCI base register points to the
219 * first memory bank. Unfortunately the address is
220 * wrong, so we fix it (again).
221 */
222 dev->resource[2] = ddb5074_resources.ram;
223 request_resource(&iomem_resource,
224 &dev->resource[2]);
225 } else if (dev->vendor == PCI_VENDOR_ID_AL
226 && dev->device == PCI_DEVICE_ID_AL_M7101) {
227 /*
228 * It's nice to have the LEDs on the GPIO pins
229 * available for debugging
230 */
231 extern struct pci_dev *pci_pmu;
232 u8 t8;
233
234 pci_pmu = dev; /* for LEDs D2 and D3 */
235 /* Program the lines for LEDs D2 and D3 to output */
236 nile4_pci_read_config_byte(dev, 0x7d, &t8);
237 t8 |= 0xc0;
238 nile4_pci_write_config_byte(dev, 0x7d, t8);
239 /* Turn LEDs D2 and D3 off */
240 nile4_pci_read_config_byte(dev, 0x7e, &t8);
241 t8 |= 0xc0;
242 nile4_pci_write_config_byte(dev, 0x7e, t8);
243 }
244 }
245 }
246
247 static void __init pcibios_fixup_irqs(void)
248 {
249 struct pci_dev *dev;
250 int slot_num;
251
252 pci_for_each_dev(dev) {
253 slot_num = PCI_SLOT(dev->devfn);
254 switch (slot_num) {
255 case 0:
256 dev->irq = nile4_to_irq(NILE4_INT_INTE);
257 break;
258 case 1:
259 dev->irq = nile4_to_irq(NILE4_INT_INTA);
260 break;
261 case 2: /* slot 1 */
262 dev->irq = nile4_to_irq(NILE4_INT_INTA);
263 break;
264 case 3: /* slot 2 */
265 dev->irq = nile4_to_irq(NILE4_INT_INTB);
266 break;
267 case 4: /* slot 3 */
268 dev->irq = nile4_to_irq(NILE4_INT_INTC);
269 break;
270 case 5:
271 /*
272 * Fixup so the serial driver can use the UART
273 */
274 dev->irq = nile4_to_irq(NILE4_INT_UART);
275 break;
276 case 13:
277 dev->irq = nile4_to_irq(NILE4_INT_INTE);
278 break;
279 default:
280 break;
281 }
282 }
283 }
284
285 void __init pcibios_init(void)
286 {
287 printk("PCI: Probing PCI hardware\n");
288 ioport_resource.end = 0x1ffffff; /* 32 MB */
289 iomem_resource.end = 0x1fffffff; /* 512 MB */
290 /* `ram' and `nile4' are requested through the Nile4 pci_dev */
291 request_resource(&iomem_resource, &ddb5074_resources.flash);
292 request_resource(&iomem_resource, &ddb5074_resources.isa_io);
293 request_resource(&iomem_resource, &ddb5074_resources.pci_io);
294 request_resource(&iomem_resource, &ddb5074_resources.isa_mem);
295 request_resource(&iomem_resource, &ddb5074_resources.pci_mem);
296 request_resource(&iomem_resource, &ddb5074_resources.boot);
297
298 pci_scan_bus(0, &nile4_pci_ops, NULL);
299 ddb5074_pci_fixup();
300 pci_assign_unassigned_resources();
301 pcibios_fixup_irqs();
302 }
303
304 void __init pcibios_fixup_bus(struct pci_bus *bus)
305 {
306 bus->resource[1] = &ddb5074_resources.pci_mem;
307 }
308
309 char *pcibios_setup(char *str)
310 {
311 return str;
312 }
313
314 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
315 {
316 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
317 }
318
319 void __init pcibios_fixup_pbus_ranges(struct pci_bus *bus,
320 struct pbus_set_ranges_data *ranges)
321 {
322 ranges->io_start -= bus->resource[0]->start;
323 ranges->io_end -= bus->resource[0]->start;
324 ranges->mem_start -= bus->resource[1]->start;
325 ranges->mem_end -= bus->resource[1]->start;
326 }
327
328 int pcibios_enable_resources(struct pci_dev *dev)
329 {
330 u16 cmd, old_cmd;
331 int idx;
332 struct resource *r;
333
334 /*
335 * Don't touch the Nile 4
336 */
337 if (dev->vendor == PCI_VENDOR_ID_NEC &&
338 dev->device == PCI_DEVICE_ID_NEC_NILE4) return 0;
339
340 pci_read_config_word(dev, PCI_COMMAND, &cmd);
341 old_cmd = cmd;
342 for (idx = 0; idx < 6; idx++) {
343 r = &dev->resource[idx];
344 if (!r->start && r->end) {
345 printk(KERN_ERR "PCI: Device %s not available because "
346 "of resource collisions\n", dev->slot_name);
347 return -EINVAL;
348 }
349 if (r->flags & IORESOURCE_IO)
350 cmd |= PCI_COMMAND_IO;
351 if (r->flags & IORESOURCE_MEM)
352 cmd |= PCI_COMMAND_MEMORY;
353 }
354 if (cmd != old_cmd) {
355 printk("PCI: Enabling device %s (%04x -> %04x)\n",
356 dev->slot_name, old_cmd, cmd);
357 pci_write_config_word(dev, PCI_COMMAND, cmd);
358 }
359 return 0;
360 }
361
362 int pcibios_enable_device(struct pci_dev *dev)
363 {
364 return pcibios_enable_resources(dev);
365 }
366
367 void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
368 struct resource *res, int resource)
369 {
370 u32 new, check;
371 int reg;
372
373 new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
374 if (resource < 6) {
375 reg = PCI_BASE_ADDRESS_0 + 4 * resource;
376 } else if (resource == PCI_ROM_RESOURCE) {
377 res->flags |= PCI_ROM_ADDRESS_ENABLE;
378 reg = dev->rom_base_reg;
379 } else {
380 /*
381 * Somebody might have asked allocation of a non-standard
382 * resource
383 */
384 return;
385 }
386
387 pci_write_config_dword(dev, reg, new);
388 pci_read_config_dword(dev, reg, &check);
389 if ((new ^ check) &
390 ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
391 PCI_BASE_ADDRESS_MEM_MASK)) {
392 printk(KERN_ERR "PCI: Error while updating region "
393 "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
394 new, check);
395 }
396 }
397
398 void pcibios_align_resource(void *data, struct resource *res,
399 unsigned long size)
400 {
401 struct pci_dev *dev = data;
402
403 if (res->flags & IORESOURCE_IO) {
404 unsigned long start = res->start;
405
406 /* We need to avoid collisions with `mirrored' VGA ports
407 and other strange ISA hardware, so we always want the
408 addresses kilobyte aligned. */
409 if (size > 0x100) {
410 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
411 " (%ld bytes)\n", dev->slot_name,
412 dev->resource - res, size);
413 }
414
415 start = (start + 1024 - 1) & ~(1024 - 1);
416 res->start = start;
417 }
418 }
419
420 unsigned __init int pcibios_assign_all_busses(void)
421 {
422 return 1;
423 }
424
425 struct pci_fixup pcibios_fixups[] = { };
426