File: /usr/src/linux/arch/mips/ddb5074/setup.c
1 /*
2 * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7 #include <linux/config.h>
8 #include <linux/init.h>
9 #include <linux/kbd_ll.h>
10 #include <linux/kernel.h>
11 #include <linux/kdev_t.h>
12 #include <linux/types.h>
13 #include <linux/console.h>
14 #include <linux/sched.h>
15 #include <linux/mc146818rtc.h>
16 #include <linux/pc_keyb.h>
17 #include <linux/pci.h>
18 #include <linux/ide.h>
19
20 #include <asm/addrspace.h>
21 #include <asm/bcache.h>
22 #include <asm/keyboard.h>
23 #include <asm/irq.h>
24 #include <asm/reboot.h>
25 #include <asm/gdb-stub.h>
26 #include <asm/nile4.h>
27 #include <asm/ddb5074.h>
28
29
30 #ifdef CONFIG_REMOTE_DEBUG
31 extern void rs_kgdb_hook(int);
32 extern void breakpoint(void);
33 #endif
34
35 #if defined(CONFIG_SERIAL_CONSOLE)
36 extern void console_setup(char *);
37 #endif
38
39 extern struct ide_ops std_ide_ops;
40 extern struct rtc_ops ddb_rtc_ops;
41
42 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
43
44 static void ddb_machine_restart(char *command)
45 {
46 u32 t;
47
48 /* PCI cold reset */
49 t = nile4_in32(NILE4_PCICTRL + 4);
50 t |= 0x40000000;
51 nile4_out32(NILE4_PCICTRL + 4, t);
52 /* CPU cold reset */
53 t = nile4_in32(NILE4_CPUSTAT);
54 t |= 1;
55 nile4_out32(NILE4_CPUSTAT, t);
56 /* Call the PROM */
57 back_to_prom();
58 }
59
60 static void ddb_machine_halt(void)
61 {
62 printk("DDB Vrc-5074 halted.\n");
63 do {
64 } while (1);
65 }
66
67 static void ddb_machine_power_off(void)
68 {
69 printk("DDB Vrc-5074 halted. Please turn off the power.\n");
70 do {
71 } while (1);
72 }
73
74 extern void ddb_irq_setup(void);
75
76 void (*board_time_init) (struct irqaction * irq);
77
78
79 static void __init ddb_time_init(struct irqaction *irq)
80 {
81 /* set the clock to 1 Hz */
82 nile4_out32(NILE4_T2CTRL, 1000000);
83 /* enable the General-Purpose Timer */
84 nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
85 /* reset timer */
86 nile4_out32(NILE4_T2CNTR, 0);
87 /* enable interrupt */
88 nile4_enable_irq(NILE4_INT_GPT);
89 i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
90 change_cp0_status(ST0_IM,
91 IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
92 }
93
94 void __init ddb_setup(void)
95 {
96 extern int panic_timeout;
97
98 irq_setup = ddb_irq_setup;
99 mips_io_port_base = NILE4_PCI_IO_BASE;
100 isa_slot_offset = NILE4_PCI_MEM_BASE;
101 request_region(0x00, 0x20, "dma1");
102 request_region(0x40, 0x20, "timer");
103 request_region(0x70, 0x10, "rtc");
104 request_region(0x80, 0x10, "dma page reg");
105 request_region(0xc0, 0x20, "dma2");
106 board_time_init = ddb_time_init;
107
108 _machine_restart = ddb_machine_restart;
109 _machine_halt = ddb_machine_halt;
110 _machine_power_off = ddb_machine_power_off;
111
112 #ifdef CONFIG_BLK_DEV_IDE
113 ide_ops = &std_ide_ops;
114 #endif
115 rtc_ops = &ddb_rtc_ops;
116
117 /* Reboot on panic */
118 panic_timeout = 180;
119 }
120
121
122 #define USE_NILE4_SERIAL 0
123
124 #if USE_NILE4_SERIAL
125 #define ns16550_in(reg) nile4_in8((reg)*8)
126 #define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
127 #else
128 #define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
129 static inline u8 ns16550_in(u32 reg)
130 {
131 return *(volatile u8 *) (NS16550_BASE + reg);
132 }
133
134 static inline void ns16550_out(u32 reg, u8 val)
135 {
136 *(volatile u8 *) (NS16550_BASE + reg) = val;
137 }
138 #endif
139
140 #define NS16550_RBR 0
141 #define NS16550_THR 0
142 #define NS16550_DLL 0
143 #define NS16550_IER 1
144 #define NS16550_DLM 1
145 #define NS16550_FCR 2
146 #define NS16550_IIR 2
147 #define NS16550_LCR 3
148 #define NS16550_MCR 4
149 #define NS16550_LSR 5
150 #define NS16550_MSR 6
151 #define NS16550_SCR 7
152
153 #define NS16550_LSR_DR 0x01 /* Data ready */
154 #define NS16550_LSR_OE 0x02 /* Overrun */
155 #define NS16550_LSR_PE 0x04 /* Parity error */
156 #define NS16550_LSR_FE 0x08 /* Framing error */
157 #define NS16550_LSR_BI 0x10 /* Break */
158 #define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
159 #define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
160 #define NS16550_LSR_ERR 0x80 /* Error */
161
162
163 void _serinit(void)
164 {
165 #if USE_NILE4_SERIAL
166 ns16550_out(NS16550_LCR, 0x80);
167 ns16550_out(NS16550_DLM, 0x00);
168 ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
169 ns16550_out(NS16550_LCR, 0x00);
170 ns16550_out(NS16550_LCR, 0x03);
171 ns16550_out(NS16550_FCR, 0x47);
172 #else
173 /* done by PMON */
174 #endif
175 }
176
177 void _putc(char c)
178 {
179 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
180 ns16550_out(NS16550_THR, c);
181 if (c == '\n') {
182 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
183 ns16550_out(NS16550_THR, '\r');
184 }
185 }
186
187 void _puts(const char *s)
188 {
189 char c;
190 while ((c = *s++))
191 _putc(c);
192 }
193
194 char _getc(void)
195 {
196 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
197 return ns16550_in(NS16550_RBR);
198 }
199
200 int _testc(void)
201 {
202 return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
203 }
204
205
206 /*
207 * Hexadecimal 7-segment LED
208 */
209 void ddb5074_led_hex(int hex)
210 {
211 outb(hex, 0x80);
212 }
213
214
215 /*
216 * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
217 */
218 struct pci_dev *pci_pmu = NULL;
219
220 void ddb5074_led_d2(int on)
221 {
222 u8 t;
223
224 if (pci_pmu) {
225 pci_read_config_byte(pci_pmu, 0x7e, &t);
226 if (on)
227 t &= 0x7f;
228 else
229 t |= 0x80;
230 pci_write_config_byte(pci_pmu, 0x7e, t);
231 }
232 }
233
234 void ddb5074_led_d3(int on)
235 {
236 u8 t;
237
238 if (pci_pmu) {
239 pci_read_config_byte(pci_pmu, 0x7e, &t);
240 if (on)
241 t &= 0xbf;
242 else
243 t |= 0x40;
244 pci_write_config_byte(pci_pmu, 0x7e, t);
245 }
246 }
247