File: /usr/src/linux/arch/mips/ddb5476/irq.c
1 /*
2 * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7 #include <linux/config.h>
8 #include <linux/init.h>
9 #include <linux/signal.h>
10 #include <linux/sched.h>
11 #include <linux/types.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
14
15 #include <asm/io.h>
16 #include <asm/irq.h>
17 #include <asm/ptrace.h>
18 #include <asm/nile4.h>
19
20 extern void __init i8259_init(void);
21 extern void i8259_disable_irq(unsigned int irq_nr);
22 extern void i8259_enable_irq(unsigned int irq_nr);
23
24 extern asmlinkage void ddbIRQ(void);
25 extern asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs);
26 extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
27
28
29 void no_action(int cpl, void *dev_id, struct pt_regs *regs)
30 {
31 }
32
33
34 #define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
35 #define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
36 #define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
37
38 #define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
39 #define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
40 #define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
41
42 #define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
43 #define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
44
45 #define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
46 #define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
47
48 #define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
49 #define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
50
51 static struct {
52 struct resource m1543_config;
53 struct resource pic_elcr;
54 } m1543_ioport = {
55 { "M1543 config", M1543_PNP_CONFIG, M1543_PNP_CONFIG + 1,
56 IORESOURCE_BUSY},
57 { "pic ELCR", M1543_INT1_MASTER_ELCR, M1543_INT1_MASTER_ELCR + 1,
58 IORESOURCE_BUSY}
59 };
60
61 static void m1543_irq_setup(void)
62 {
63 /*
64 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
65 * the possible IO sources in the M1543 are in use by us. We will
66 * use the following mapping:
67 *
68 * IRQ1 - keyboard (default set by M1543)
69 * IRQ3 - reserved for UART B (default set by M1543) (note that
70 * the schematics for the DDB Vrc-5476 board seem to
71 * indicate that IRQ3 is connected to the DS1386
72 * watchdog timer interrupt output so we might have
73 * a conflict)
74 * IRQ4 - reserved for UART A (default set by M1543)
75 * IRQ5 - parallel (default set by M1543)
76 * IRQ8 - DS1386 time of day (RTC) interrupt
77 * IRQ9 - USB (hardwired in ddb_setup)
78 * IRQ10 - PMU (hardwired in ddb_setup)
79 * IRQ12 - mouse
80 * IRQ14,15 - IDE controller (need to be confirmed, jsun)
81 */
82
83 /*
84 * Assing mouse interrupt to IRQ12
85 */
86
87 /* Enter configuration mode */
88 outb(0x51, M1543_PNP_CONFIG);
89 outb(0x23, M1543_PNP_CONFIG);
90
91 /* Select logical device 7 (Keyboard) */
92 outb(0x07, M1543_PNP_INDEX);
93 outb(0x07, M1543_PNP_DATA);
94
95 /* Select IRQ12 */
96 outb(0x72, M1543_PNP_INDEX);
97 outb(0x0c, M1543_PNP_DATA);
98
99 /* Leave configration mode */
100 outb(0xbb, M1543_PNP_CONFIG);
101
102
103 /* Initialize the 8259 PIC in the M1543 */
104 i8259_init();
105
106 /* Enable the interrupt cascade from M1543 */
107 nile4_enable_irq(NILE4_INT_INTC);
108
109 /* request io ports */
110 if (request_resource(&ioport_resource, &m1543_ioport.m1543_config)
111 || request_resource(&ioport_resource, &m1543_ioport.pic_elcr)) {
112 printk("m1543_irq_setup : requesting io ports failed.\n");
113 for (;;);
114 }
115 }
116
117 static void nile4_irq_setup(void)
118 {
119 int i;
120
121 /* Map all interrupts to CPU int #0 */
122 nile4_map_irq_all(0);
123
124 /* PCI INTA#-E# must be level triggered */
125 nile4_set_pci_irq_level_or_edge(0, 1);
126 nile4_set_pci_irq_level_or_edge(1, 1);
127 nile4_set_pci_irq_level_or_edge(2, 1);
128 nile4_set_pci_irq_level_or_edge(3, 1);
129
130 /* PCI INTA#, B#, D# must be active low, INTC# must be active high */
131 nile4_set_pci_irq_polarity(0, 0);
132 nile4_set_pci_irq_polarity(1, 0);
133 nile4_set_pci_irq_polarity(2, 1);
134 nile4_set_pci_irq_polarity(3, 0);
135
136 for (i = 0; i < 16; i++)
137 nile4_clear_irq(i);
138
139 /* Enable CPU int #0 */
140 nile4_enable_irq_output(0);
141
142 /* memory resource acquire in ddb_setup */
143 }
144
145
146 /*
147 * IRQ2 is cascade interrupt to second interrupt controller
148 */
149 static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL };
150
151
152 void disable_irq(unsigned int irq_nr)
153 {
154 if (is_i8259_irq(irq_nr))
155 i8259_disable_irq(irq_nr);
156 else
157 nile4_disable_irq(irq_to_nile4(irq_nr));
158 }
159
160 void enable_irq(unsigned int irq_nr)
161 {
162 if (is_i8259_irq(irq_nr))
163 i8259_enable_irq(irq_nr);
164 else
165 nile4_enable_irq(irq_to_nile4(irq_nr));
166 }
167
168 int table[16] = { 0, };
169
170 void ddb_local0_irqdispatch(struct pt_regs *regs)
171 {
172 u32 mask;
173 int nile4_irq;
174 #if 0
175 volatile static int nesting = 0;
176 if (nesting++ == 0)
177 ddb5476_led_d3(1);
178 ddb5476_led_hex(nesting < 16 ? nesting : 15);
179 #endif
180
181 mask = nile4_get_irq_stat(0);
182 nile4_clear_irq_mask(mask);
183
184 /* Handle the timer interrupt first */
185 if (mask & (1 << NILE4_INT_GPT)) {
186 nile4_disable_irq(NILE4_INT_GPT);
187 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
188 nile4_enable_irq(NILE4_INT_GPT);
189 mask &= ~(1 << NILE4_INT_GPT);
190 }
191 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
192 if (mask & 1) {
193 nile4_disable_irq(nile4_irq);
194 if (nile4_irq == NILE4_INT_INTC) {
195 int i8259_irq = nile4_i8259_iack();
196 i8259_do_irq(i8259_irq, regs);
197 } else {
198 do_IRQ(nile4_to_irq(nile4_irq), regs);
199 }
200 nile4_enable_irq(nile4_irq);
201 }
202 #if 0
203 if (--nesting == 0)
204 ddb5476_led_d3(0);
205 ddb5476_led_hex(nesting < 16 ? nesting : 15);
206 #endif
207 }
208
209 void ddb_local1_irqdispatch(void)
210 {
211 printk("ddb_local1_irqdispatch called\n");
212 }
213
214 void ddb_buserror_irq(void)
215 {
216 printk("ddb_buserror_irq called\n");
217 }
218
219 void ddb_8254timer_irq(void)
220 {
221 printk("ddb_8254timer_irq called\n");
222 }
223
224 void ddb_phantom_irq(unsigned long cause)
225 {
226 printk("phantom interrupts detected : \n");
227 printk("\tcause \t\t0x%08x\n", cause);
228 printk("\tcause reg\t0x%08x\n",
229 read_32bit_cp0_register(CP0_CAUSE));
230 printk("\tstatus reg\t0x%08x\n",
231 read_32bit_cp0_register(CP0_STATUS));
232 }
233
234 void __init ddb_irq_setup(void)
235 {
236 #ifdef CONFIG_REMOTE_DEBUG
237 printk("Wait for gdb client connection ...\n");
238 set_debug_traps();
239 breakpoint(); /* you may move this line to whereever you want :-) */
240 #endif
241 i8259_setup_irq(2, &irq2);
242
243 nile4_irq_setup();
244 m1543_irq_setup();
245
246 /* we pin #0 - #4 (no internal timer) */
247 change_cp0_status(ST0_IM,
248 IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
249
250 set_except_vector(0, ddbIRQ);
251 }
252