File: /usr/src/linux/arch/mips/ddb5476/setup.c
1 /*
2 * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7 #include <linux/config.h>
8 #include <linux/init.h>
9 #include <linux/kbd_ll.h>
10 #include <linux/kernel.h>
11 #include <linux/kdev_t.h>
12 #include <linux/types.h>
13 #include <linux/console.h>
14 #include <linux/sched.h>
15 #include <linux/mc146818rtc.h>
16 #include <linux/pc_keyb.h>
17 #include <linux/pci.h>
18 #include <linux/ide.h>
19
20 #include <asm/addrspace.h>
21 #include <asm/bcache.h>
22 #include <asm/keyboard.h>
23 #include <asm/irq.h>
24 #include <asm/reboot.h>
25 #include <asm/gdb-stub.h>
26 #include <asm/nile4.h>
27 #include <asm/time.h>
28
29
30 #ifdef CONFIG_REMOTE_DEBUG
31 extern void rs_kgdb_hook(int);
32 extern void breakpoint(void);
33 #endif
34
35 #if defined(CONFIG_SERIAL_CONSOLE)
36 extern void console_setup(char *);
37 #endif
38
39 extern struct ide_ops std_ide_ops;
40 extern struct rtc_ops ddb_rtc_ops;
41 extern struct kbd_ops std_kbd_ops;
42
43 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
44
45 static void ddb_machine_restart(char *command)
46 {
47 u32 t;
48
49 /* PCI cold reset */
50 t = nile4_in32(NILE4_PCICTRL + 4);
51 t |= 0x40000000;
52 nile4_out32(NILE4_PCICTRL + 4, t);
53 /* CPU cold reset */
54 t = nile4_in32(NILE4_CPUSTAT);
55 t |= 1;
56 nile4_out32(NILE4_CPUSTAT, t);
57 /* Call the PROM */
58 back_to_prom();
59 }
60
61 static void ddb_machine_halt(void)
62 {
63 printk("DDB Vrc-5476 halted.\n");
64 while (1);
65 }
66
67 static void ddb_machine_power_off(void)
68 {
69 printk("DDB Vrc-5476 halted. Please turn off the power.\n");
70 while (1);
71 }
72
73 extern void ddb_irq_setup(void);
74
75 static void __init ddb_time_init(struct irqaction *irq)
76 {
77 printk("ddb_time_init invoked.\n");
78 mips_counter_frequency = 83000000;
79 }
80
81 static void __init ddb_timer_setup(struct irqaction *irq)
82 {
83 unsigned int count;
84
85 /* we are using the cpu counter for timer interrupts */
86 i8259_setup_irq(0, irq);
87 set_cp0_status(IE_IRQ5);
88
89 /* to generate the first timer interrupt */
90 count = read_32bit_cp0_register(CP0_COUNT);
91 write_32bit_cp0_register(CP0_COMPARE, count + 1000);
92
93 #if 0 /* the old way to do timer interrupt */
94 /* set the clock to 100 Hz */
95 nile4_out32(NILE4_T2CTRL, 830000);
96 /* enable the General-Purpose Timer */
97 nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
98 /* reset timer */
99 nile4_out32(NILE4_T2CNTR, 0);
100 /* enable interrupt */
101 nile4_enable_irq(NILE4_INT_GPT);
102 i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
103 #endif
104 }
105
106 static struct {
107 struct resource dma1;
108 struct resource pic1;
109 struct resource timer;
110 struct resource rtc;
111 struct resource dma_page_reg;
112 struct resource pic2;
113 struct resource dma2;
114 } ddb5476_ioport = {
115 {
116 "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
117 "pic1", 0x20, 0x3f, IORESOURCE_BUSY}, {
118 "timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
119 "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
120 "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
121 "pic2", 0xa0, 0xbf, IORESOURCE_BUSY}, {
122 "dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
123 };
124
125 static struct {
126 struct resource nile4;
127 } ddb5476_iomem = {
128 { "Nile 4", NILE4_BASE, NILE4_BASE + NILE4_SIZE - 1, IORESOURCE_BUSY}
129 };
130
131 void __init ddb_setup(void)
132 {
133 extern int panic_timeout;
134
135 irq_setup = ddb_irq_setup;
136 mips_io_port_base = NILE4_PCI_IO_BASE;
137 isa_slot_offset = NILE4_PCI_MEM_BASE;
138
139 board_time_init = ddb_time_init;
140 board_timer_setup = ddb_timer_setup;
141
142 _machine_restart = ddb_machine_restart;
143 _machine_halt = ddb_machine_halt;
144 _machine_power_off = ddb_machine_power_off;
145
146 /* request io port/mem resources */
147 if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
148 request_resource(&ioport_resource, &ddb5476_ioport.pic1) ||
149 request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
150 request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
151 request_resource(&ioport_resource,
152 &ddb5476_ioport.dma_page_reg)
153 || request_resource(&ioport_resource, &ddb5476_ioport.pic2)
154 || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
155 || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
156 printk
157 ("ddb_setup - requesting oo port resources failed.\n");
158 for (;;);
159 }
160 #ifdef CONFIG_BLK_DEV_IDE
161 ide_ops = &std_ide_ops;
162 #endif
163 rtc_ops = &ddb_rtc_ops;
164
165 #ifdef CONFIG_PC_KEYB
166 kbd_ops = &std_kbd_ops;
167 #endif
168
169 /* Reboot on panic */
170 panic_timeout = 180;
171
172 /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
173 /* *(long*)0xbfa00218 = 0x8; */
174
175 #ifdef CONFIG_FB
176 conswitchp = &dummy_con;
177 #endif
178
179
180 /* board initialization stuff - non-fundamental, but need to be set
181 * before kernel runs */
182
183 /* setup I/O space */
184 nile4_set_pdar(NILE4_PCIW0,
185 PHYSADDR(NILE4_PCI_IO_BASE), 0x02000000, 32, 0, 0);
186 nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0);
187
188 /* map config space to 0xa8000000, 128MB */
189 nile4_set_pdar(NILE4_PCIW1,
190 PHYSADDR(NILE4_PCI_CFG_BASE), 0x08000000, 32, 0, 0);
191 nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, 0x0);
192
193 /* ----- M1543 PCI setup ------ */
194
195 /* we know M1543 PCI-ISA controller is at addr:18 */
196 /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
197 *(volatile unsigned char *) 0xa8040072 &= 0xf0;
198 *(volatile unsigned char *) 0xa8040072 |= 0xa;
199
200 /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
201 * no IOCHRDY signal, (bit 7 - 1)
202 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
203 * Bypass USB Master INTAJ level to edge conversion (bit 4 - 0)
204 */
205 *(unsigned char *) 0xa8040074 = 0xc1;
206
207 /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
208 * SCI routing to IRQ 13 disabled (bit 7 - 1)
209 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
210 */
211 *(unsigned char *) 0xa8040076 = 0x83;
212
213 /* setup IDE controller
214 * enable IDE controller (bit 6 - 1)
215 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
216 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
217 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
218 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
219 */
220 // *(unsigned char*)0xa8040058 = 0x71;
221 // *(unsigned char*)0xa8040058 = 0x79;
222 // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
223 *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
224
225 #if 0
226 /* this is not necessary if M5229 does not use SIRQ */
227 *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
228 *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
229 #endif
230
231 /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
232 /* M5229 IDSEL is addr:24; see above setting */
233 *(unsigned char *) 0xa9000050 |= 0x1;
234
235 /* enable bus master (bit 2) and IO decoding (bit 0) */
236 *(unsigned char *) 0xa9000004 |= 0x5;
237
238 /* enable native, copied from arch/ppc/k2boot/head.S */
239 /* TODO - need volatile, need to be portable */
240 *(unsigned char *) 0xa9000009 = 0xff;
241
242 /* ----- end of M1543 PCI setup ------ */
243
244 /* ----- reset on-board ether chip ------ */
245 *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
246 *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
247
248 /* send reset command */
249 *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
250
251 /* disable ether chip */
252 *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
253
254 /* put it into sleep */
255 *((volatile u32 *) 0xa8020040) = 0x80000000;
256
257 /* ----- end of reset on-board ether chip ------ */
258
259 /* ----- set pci window 1 to pci memory space -------- */
260 nile4_set_pdar(NILE4_PCIW1,
261 PHYSADDR(NILE4_PCI_MEM_BASE), 0x08000000, 32, 0, 0);
262 // nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
263 nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0x08000000);
264
265 }
266
267 #define USE_NILE4_SERIAL 0
268
269 #if USE_NILE4_SERIAL
270 #define ns16550_in(reg) nile4_in8((reg)*8)
271 #define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
272 #else
273 #define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
274 static inline u8 ns16550_in(u32 reg)
275 {
276 return *(volatile u8 *) (NS16550_BASE + reg);
277 }
278
279 static inline void ns16550_out(u32 reg, u8 val)
280 {
281 *(volatile u8 *) (NS16550_BASE + reg) = val;
282 }
283 #endif
284
285 #define NS16550_RBR 0
286 #define NS16550_THR 0
287 #define NS16550_DLL 0
288 #define NS16550_IER 1
289 #define NS16550_DLM 1
290 #define NS16550_FCR 2
291 #define NS16550_IIR 2
292 #define NS16550_LCR 3
293 #define NS16550_MCR 4
294 #define NS16550_LSR 5
295 #define NS16550_MSR 6
296 #define NS16550_SCR 7
297
298 #define NS16550_LSR_DR 0x01 /* Data ready */
299 #define NS16550_LSR_OE 0x02 /* Overrun */
300 #define NS16550_LSR_PE 0x04 /* Parity error */
301 #define NS16550_LSR_FE 0x08 /* Framing error */
302 #define NS16550_LSR_BI 0x10 /* Break */
303 #define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
304 #define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
305 #define NS16550_LSR_ERR 0x80 /* Error */
306
307
308 void _serinit(void)
309 {
310 #if USE_NILE4_SERIAL
311 ns16550_out(NS16550_LCR, 0x80);
312 ns16550_out(NS16550_DLM, 0x00);
313 ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
314 ns16550_out(NS16550_LCR, 0x00);
315 ns16550_out(NS16550_LCR, 0x03);
316 ns16550_out(NS16550_FCR, 0x47);
317 #else
318 /* done by PMON */
319 #endif
320 }
321
322 void _putc(char c)
323 {
324 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
325 ns16550_out(NS16550_THR, c);
326 if (c == '\n') {
327 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
328 ns16550_out(NS16550_THR, '\r');
329 }
330 }
331
332 void _puts(const char *s)
333 {
334 char c;
335
336 while ((c = *s++))
337 _putc(c);
338 }
339
340 char _getc(void)
341 {
342 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
343
344 return ns16550_in(NS16550_RBR);
345 }
346
347 int _testc(void)
348 {
349 return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
350 }
351
352
353 /*
354 * Hexadecimal 7-segment LED
355 */
356 void ddb5476_led_hex(int hex)
357 {
358 outb(hex, 0x80);
359 }
360
361
362 /*
363 * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
364 */
365 struct pci_dev *pci_pmu = NULL;
366
367 void ddb5476_led_d2(int on)
368 {
369 u8 t;
370
371 if (pci_pmu) {
372 pci_read_config_byte(pci_pmu, 0x7e, &t);
373 if (on)
374 t &= 0x7f;
375 else
376 t |= 0x80;
377 pci_write_config_byte(pci_pmu, 0x7e, t);
378 }
379 }
380
381 void ddb5476_led_d3(int on)
382 {
383 u8 t;
384
385 if (pci_pmu) {
386 pci_read_config_byte(pci_pmu, 0x7e, &t);
387 if (on)
388 t &= 0xbf;
389 else
390 t |= 0x40;
391 pci_write_config_byte(pci_pmu, 0x7e, t);
392 }
393 }
394