File: /usr/src/linux/arch/mips/dec/time.c
1 /*
2 * linux/arch/mips/dec/time.c
3 *
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 * Copyright (C) 2000 Maciej W. Rozycki
6 *
7 * This file contains the time handling details for PC-style clocks as
8 * found in some MIPS systems.
9 *
10 */
11 #include <linux/errno.h>
12 #include <linux/init.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/param.h>
16 #include <linux/string.h>
17 #include <linux/mm.h>
18 #include <linux/interrupt.h>
19
20 #include <asm/cpu.h>
21 #include <asm/bootinfo.h>
22 #include <asm/mipsregs.h>
23 #include <asm/io.h>
24 #include <asm/irq.h>
25 #include <asm/dec/machtype.h>
26 #include <asm/dec/ioasic.h>
27 #include <asm/dec/ioasic_addrs.h>
28
29 #include <linux/mc146818rtc.h>
30 #include <linux/timex.h>
31
32 #include <asm/div64.h>
33
34 extern void (*board_time_init)(struct irqaction *irq);
35
36 extern volatile unsigned long wall_jiffies;
37 extern rwlock_t xtime_lock;
38
39 /*
40 * Change this if you have some constant time drift
41 */
42 /* This is the value for the PC-style PICs. */
43 /* #define USECS_PER_JIFFY (1000020/HZ) */
44
45 /* This is for machines which generate the exact clock. */
46 #define USECS_PER_JIFFY (1000000/HZ)
47 #define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff)
48
49 /* Cycle counter value at the previous timer interrupt.. */
50
51 static unsigned int timerhi, timerlo;
52
53 /*
54 * Cached "1/(clocks per usec)*2^32" value.
55 * It has to be recalculated once each jiffy.
56 */
57 static unsigned long cached_quotient = 0;
58
59 /* Last jiffy when do_fast_gettimeoffset() was called. */
60 static unsigned long last_jiffies = 0;
61
62 /*
63 * On MIPS only R4000 and better have a cycle counter.
64 *
65 * FIXME: Does playing with the RP bit in c0_status interfere with this code?
66 */
67 static unsigned long do_fast_gettimeoffset(void)
68 {
69 u32 count;
70 unsigned long res, tmp;
71 unsigned long quotient;
72
73 tmp = jiffies;
74
75 quotient = cached_quotient;
76
77 if (last_jiffies != tmp) {
78 last_jiffies = tmp;
79 if (last_jiffies != 0) {
80 unsigned long r0;
81 __asm__(".set push\n\t"
82 ".set mips3\n\t"
83 "lwu %0,%3\n\t"
84 "dsll32 %1,%2,0\n\t"
85 "or %1,%1,%0\n\t"
86 "ddivu $0,%1,%4\n\t"
87 "mflo %1\n\t"
88 "dsll32 %0,%5,0\n\t"
89 "or %0,%0,%6\n\t"
90 "ddivu $0,%0,%1\n\t"
91 "mflo %0\n\t"
92 ".set pop"
93 : "=&r" (quotient), "=&r" (r0)
94 : "r" (timerhi), "m" (timerlo),
95 "r" (tmp), "r" (USECS_PER_JIFFY),
96 "r" (USECS_PER_JIFFY_FRAC));
97 cached_quotient = quotient;
98 }
99 }
100 /* Get last timer tick in absolute kernel time */
101 count = read_32bit_cp0_register(CP0_COUNT);
102
103 /* .. relative to previous jiffy (32 bits is enough) */
104 count -= timerlo;
105 //printk("count: %08lx, %08lx:%08lx\n", count, timerhi, timerlo);
106
107 __asm__("multu %2,%3"
108 : "=l" (tmp), "=h" (res)
109 : "r" (count), "r" (quotient));
110
111 /*
112 * Due to possible jiffies inconsistencies, we need to check
113 * the result so that we'll get a timer that is monotonic.
114 */
115 if (res >= USECS_PER_JIFFY)
116 res = USECS_PER_JIFFY - 1;
117
118 return res;
119 }
120
121 static unsigned long do_ioasic_gettimeoffset(void)
122 {
123 u32 count;
124 unsigned long res, tmp;
125 unsigned long quotient;
126
127 tmp = jiffies;
128
129 quotient = cached_quotient;
130
131 if (last_jiffies != tmp) {
132 last_jiffies = tmp;
133 if (last_jiffies != 0) {
134 unsigned long r0;
135 do_div64_32(r0, timerhi, timerlo, tmp);
136 do_div64_32(quotient, USECS_PER_JIFFY,
137 USECS_PER_JIFFY_FRAC, r0);
138 cached_quotient = quotient;
139 }
140 }
141 /* Get last timer tick in absolute kernel time */
142 count = ioasic_read(FCTR);
143
144 /* .. relative to previous jiffy (32 bits is enough) */
145 count -= timerlo;
146 //printk("count: %08x, %08x:%08x\n", count, timerhi, timerlo);
147
148 __asm__("multu %2,%3"
149 : "=l" (tmp), "=h" (res)
150 : "r" (count), "r" (quotient));
151
152 /*
153 * Due to possible jiffies inconsistencies, we need to check
154 * the result so that we'll get a timer that is monotonic.
155 */
156 if (res >= USECS_PER_JIFFY)
157 res = USECS_PER_JIFFY - 1;
158
159 return res;
160 }
161
162 /* This function must be called with interrupts disabled
163 * It was inspired by Steve McCanne's microtime-i386 for BSD. -- jrs
164 *
165 * However, the pc-audio speaker driver changes the divisor so that
166 * it gets interrupted rather more often - it loads 64 into the
167 * counter rather than 11932! This has an adverse impact on
168 * do_gettimeoffset() -- it stops working! What is also not
169 * good is that the interval that our timer function gets called
170 * is no longer 10.0002 ms, but 9.9767 ms. To get around this
171 * would require using a different timing source. Maybe someone
172 * could use the RTC - I know that this can interrupt at frequencies
173 * ranging from 8192Hz to 2Hz. If I had the energy, I'd somehow fix
174 * it so that at startup, the timer code in sched.c would select
175 * using either the RTC or the 8253 timer. The decision would be
176 * based on whether there was any other device around that needed
177 * to trample on the 8253. I'd set up the RTC to interrupt at 1024 Hz,
178 * and then do some jiggery to have a version of do_timer that
179 * advanced the clock by 1/1024 s. Every time that reached over 1/100
180 * of a second, then do all the old code. If the time was kept correct
181 * then do_gettimeoffset could just return 0 - there is no low order
182 * divider that can be accessed.
183 *
184 * Ideally, you would be able to use the RTC for the speaker driver,
185 * but it appears that the speaker driver really needs interrupt more
186 * often than every 120 us or so.
187 *
188 * Anyway, this needs more thought.... pjsg (1993-08-28)
189 *
190 * If you are really that interested, you should be reading
191 * comp.protocols.time.ntp!
192 */
193
194 #define TICK_SIZE tick
195
196 static unsigned long do_slow_gettimeoffset(void)
197 {
198 /*
199 * This is a kludge until I find a way for the
200 * DECstations without bus cycle counter. HK
201 */
202 return 0;
203 }
204
205 static unsigned long (*do_gettimeoffset) (void) = do_slow_gettimeoffset;
206
207 /*
208 * This version of gettimeofday has near microsecond resolution.
209 */
210 void do_gettimeofday(struct timeval *tv)
211 {
212 unsigned long flags;
213
214 read_lock_irqsave(&xtime_lock, flags);
215 *tv = xtime;
216 tv->tv_usec += do_gettimeoffset();
217
218 /*
219 * xtime is atomically updated in timer_bh. jiffies - wall_jiffies
220 * is nonzero if the timer bottom half hasnt executed yet.
221 */
222 if (jiffies - wall_jiffies)
223 tv->tv_usec += USECS_PER_JIFFY;
224
225 read_unlock_irqrestore(&xtime_lock, flags);
226
227 if (tv->tv_usec >= 1000000) {
228 tv->tv_usec -= 1000000;
229 tv->tv_sec++;
230 }
231 }
232
233 void do_settimeofday(struct timeval *tv)
234 {
235 write_lock_irq(&xtime_lock);
236
237 /* This is revolting. We need to set the xtime.tv_usec
238 * correctly. However, the value in this location is
239 * is value at the last tick.
240 * Discover what correction gettimeofday
241 * would have done, and then undo it!
242 */
243 tv->tv_usec -= do_gettimeoffset();
244
245 if (tv->tv_usec < 0) {
246 tv->tv_usec += 1000000;
247 tv->tv_sec--;
248 }
249
250 xtime = *tv;
251 time_adjust = 0; /* stop active adjtime() */
252 time_status |= STA_UNSYNC;
253 time_maxerror = NTP_PHASE_LIMIT;
254 time_esterror = NTP_PHASE_LIMIT;
255
256 write_unlock_irq(&xtime_lock);
257 }
258
259 /*
260 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
261 * called 500 ms after the second nowtime has started, because when
262 * nowtime is written into the registers of the CMOS clock, it will
263 * jump to the next second precisely 500 ms later. Check the Motorola
264 * MC146818A or Dallas DS12887 data sheet for details.
265 */
266 static int set_rtc_mmss(unsigned long nowtime)
267 {
268 int retval = 0;
269 int real_seconds, real_minutes, cmos_minutes;
270 unsigned char save_control, save_freq_select;
271
272 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
273 CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);
274
275 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
276 CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
277
278 cmos_minutes = CMOS_READ(RTC_MINUTES);
279 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
280 BCD_TO_BIN(cmos_minutes);
281
282 /*
283 * since we're only adjusting minutes and seconds,
284 * don't interfere with hour overflow. This avoids
285 * messing with unknown time zones but requires your
286 * RTC not to be off by more than 15 minutes
287 */
288 real_seconds = nowtime % 60;
289 real_minutes = nowtime / 60;
290 if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1)
291 real_minutes += 30; /* correct for half hour time zone */
292 real_minutes %= 60;
293
294 if (abs(real_minutes - cmos_minutes) < 30) {
295 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
296 BIN_TO_BCD(real_seconds);
297 BIN_TO_BCD(real_minutes);
298 }
299 CMOS_WRITE(real_seconds, RTC_SECONDS);
300 CMOS_WRITE(real_minutes, RTC_MINUTES);
301 } else {
302 printk(KERN_WARNING
303 "set_rtc_mmss: can't update from %d to %d\n",
304 cmos_minutes, real_minutes);
305 retval = -1;
306 }
307
308 /* The following flags have to be released exactly in this order,
309 * otherwise the DS12887 (popular MC146818A clone with integrated
310 * battery and quartz) will not reset the oscillator and will not
311 * update precisely 500 ms later. You won't find this mentioned in
312 * the Dallas Semiconductor data sheets, but who believes data
313 * sheets anyway ... -- Markus Kuhn
314 */
315 CMOS_WRITE(save_control, RTC_CONTROL);
316 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
317
318 return retval;
319 }
320
321 /* last time the cmos clock got updated */
322 static long last_rtc_update;
323
324 /*
325 * timer_interrupt() needs to keep up the real-time clock,
326 * as well as call the "do_timer()" routine every clocktick
327 */
328 static void inline
329 timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
330 {
331 volatile unsigned char dummy;
332
333 dummy = CMOS_READ(RTC_REG_C); /* ACK RTC Interrupt */
334
335 if (!user_mode(regs)) {
336 if (prof_buffer && current->pid) {
337 extern int _stext;
338 unsigned long pc = regs->cp0_epc;
339
340 pc -= (unsigned long) &_stext;
341 pc >>= prof_shift;
342 /*
343 * Dont ignore out-of-bounds pc values silently,
344 * put them into the last histogram slot, so if
345 * present, they will show up as a sharp peak.
346 */
347 if (pc > prof_len - 1)
348 pc = prof_len - 1;
349 atomic_inc((atomic_t *) & prof_buffer[pc]);
350 }
351 }
352 do_timer(regs);
353
354 /*
355 * If we have an externally synchronized Linux clock, then update
356 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
357 * called as close as possible to 500 ms before the new second starts.
358 */
359 read_lock(&xtime_lock);
360 if ((time_status & STA_UNSYNC) == 0
361 && xtime.tv_sec > last_rtc_update + 660
362 && xtime.tv_usec >= 500000 - tick / 2
363 && xtime.tv_usec <= 500000 + tick / 2) {
364 if (set_rtc_mmss(xtime.tv_sec) == 0)
365 last_rtc_update = xtime.tv_sec;
366 else
367 /* do it again in 60 s */
368 last_rtc_update = xtime.tv_sec - 600;
369 }
370 /* As we return to user mode fire off the other CPU schedulers.. this is
371 basically because we don't yet share IRQ's around. This message is
372 rigged to be safe on the 386 - basically it's a hack, so don't look
373 closely for now.. */
374 /*smp_message_pass(MSG_ALL_BUT_SELF, MSG_RESCHEDULE, 0L, 0); */
375 read_unlock(&xtime_lock);
376 }
377
378 static void r4k_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
379 {
380 unsigned int count;
381
382 /*
383 * The cycle counter is only 32 bit which is good for about
384 * a minute at current count rates of upto 150MHz or so.
385 */
386 count = read_32bit_cp0_register(CP0_COUNT);
387 timerhi += (count < timerlo); /* Wrap around */
388 timerlo = count;
389
390 if (jiffies == ~0) {
391 /*
392 * If jiffies is to overflow in this timer_interrupt we must
393 * update the timer[hi]/[lo] to make do_fast_gettimeoffset()
394 * quotient calc still valid. -arca
395 */
396 write_32bit_cp0_register(CP0_COUNT, 0);
397 timerhi = timerlo = 0;
398 }
399
400 timer_interrupt(irq, dev_id, regs);
401 }
402
403 static void ioasic_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
404 {
405 unsigned int count;
406
407 /*
408 * The free-running counter is 32 bit which is good for about
409 * 2 minutes, 50 seconds at possible count rates of upto 25MHz.
410 */
411 count = ioasic_read(FCTR);
412 timerhi += (count < timerlo); /* Wrap around */
413 timerlo = count;
414
415 if (jiffies == ~0) {
416 /*
417 * If jiffies is to overflow in this timer_interrupt we must
418 * update the timer[hi]/[lo] to make do_fast_gettimeoffset()
419 * quotient calc still valid. -arca
420 */
421 ioasic_write(FCTR, 0);
422 timerhi = timerlo = 0;
423 }
424
425 timer_interrupt(irq, dev_id, regs);
426 }
427
428 struct irqaction irq0 = {timer_interrupt, SA_INTERRUPT, 0,
429 "timer", NULL, NULL};
430
431 void __init time_init(void)
432 {
433 unsigned int year, mon, day, hour, min, sec, real_year;
434 int i;
435
436 /* The Linux interpretation of the CMOS clock register contents:
437 * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
438 * RTC registers show the second which has precisely just started.
439 * Let's hope other operating systems interpret the RTC the same way.
440 */
441 /* read RTC exactly on falling edge of update flag */
442 for (i = 0; i < 1000000; i++) /* may take up to 1 second... */
443 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
444 break;
445 for (i = 0; i < 1000000; i++) /* must try at least 2.228 ms */
446 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
447 break;
448 do { /* Isn't this overkill ? UIP above should guarantee consistency */
449 sec = CMOS_READ(RTC_SECONDS);
450 min = CMOS_READ(RTC_MINUTES);
451 hour = CMOS_READ(RTC_HOURS);
452 day = CMOS_READ(RTC_DAY_OF_MONTH);
453 mon = CMOS_READ(RTC_MONTH);
454 year = CMOS_READ(RTC_YEAR);
455 } while (sec != CMOS_READ(RTC_SECONDS));
456 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
457 BCD_TO_BIN(sec);
458 BCD_TO_BIN(min);
459 BCD_TO_BIN(hour);
460 BCD_TO_BIN(day);
461 BCD_TO_BIN(mon);
462 BCD_TO_BIN(year);
463 }
464 /*
465 * The PROM will reset the year to either '72 or '73.
466 * Therefore we store the real year separately, in one
467 * of unused BBU RAM locations.
468 */
469 real_year = CMOS_READ(RTC_DEC_YEAR);
470 year += real_year - 72 + 2000;
471
472 write_lock_irq(&xtime_lock);
473 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
474 xtime.tv_usec = 0;
475 write_unlock_irq(&xtime_lock);
476
477 if (mips_cpu.options & MIPS_CPU_COUNTER) {
478 write_32bit_cp0_register(CP0_COUNT, 0);
479 do_gettimeoffset = do_fast_gettimeoffset;
480 irq0.handler = r4k_timer_interrupt;
481 } else if (IOASIC) {
482 ioasic_write(FCTR, 0);
483 do_gettimeoffset = do_ioasic_gettimeoffset;
484 irq0.handler = ioasic_timer_interrupt;
485 }
486 board_time_init(&irq0);
487 }
488