File: /usr/src/linux/arch/mips/ite-boards/generic/irq.c
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE 8172G interrupt/setup routines.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * Part of this file was derived from Carsten Langgaard's
11 * arch/mips/mips-boards/atlas/atlas_int.c.
12 *
13 * Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36 #include <linux/errno.h>
37 #include <linux/init.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/module.h>
40 #include <linux/signal.h>
41 #include <linux/sched.h>
42 #include <linux/types.h>
43 #include <linux/interrupt.h>
44 #include <linux/ioport.h>
45 #include <linux/timex.h>
46 #include <linux/slab.h>
47 #include <linux/random.h>
48 #include <linux/serial_reg.h>
49
50 #include <asm/bitops.h>
51 #include <asm/bootinfo.h>
52 #include <asm/io.h>
53 #include <asm/mipsregs.h>
54 #include <asm/system.h>
55 #include <asm/it8172/it8172.h>
56 #include <asm/it8172/it8172_int.h>
57 #include <asm/it8172/it8172_dbg.h>
58
59 #undef DEBUG_IRQ
60 #ifdef DEBUG_IRQ
61 /* note: prints function name for you */
62 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
63 #else
64 #define DPRINTK(fmt, args...)
65 #endif
66
67 #ifdef CONFIG_REMOTE_DEBUG
68 extern void breakpoint(void);
69 #endif
70
71 /* revisit */
72 #define EXT_IRQ0_TO_IP 2 /* IP 2 */
73 #define EXT_IRQ5_TO_IP 7 /* IP 7 */
74
75 extern void set_debug_traps(void);
76 extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
77 extern asmlinkage void it8172_IRQ(void);
78 unsigned int local_bh_count[NR_CPUS];
79 unsigned int local_irq_count[NR_CPUS];
80 unsigned long spurious_count = 0;
81 irq_desc_t irq_desc[NR_IRQS];
82 irq_desc_t *irq_desc_base=&irq_desc[0];
83 void disable_it8172_irq(unsigned int irq_nr);
84 void enable_it8172_irq(unsigned int irq_nr);
85
86 struct it8172_intc_regs volatile *it8172_hw0_icregs
87 = (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
88
89 /* Function for careful CP0 interrupt mask access */
90 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
91 {
92 unsigned long status = read_32bit_cp0_register(CP0_STATUS);
93 status &= ~((clr_mask & 0xFF) << 8);
94 status |= (set_mask & 0xFF) << 8;
95 write_32bit_cp0_register(CP0_STATUS, status);
96 }
97
98 static inline void mask_irq(unsigned int irq_nr)
99 {
100 modify_cp0_intmask(irq_nr, 0);
101 }
102
103 static inline void unmask_irq(unsigned int irq_nr)
104 {
105 modify_cp0_intmask(0, irq_nr);
106 }
107
108 void disable_irq(unsigned int irq_nr)
109 {
110 unsigned long flags;
111
112 save_and_cli(flags);
113 disable_it8172_irq(irq_nr);
114 restore_flags(flags);
115 }
116
117 void enable_irq(unsigned int irq_nr)
118 {
119 unsigned long flags;
120
121 save_and_cli(flags);
122 enable_it8172_irq(irq_nr);
123 restore_flags(flags);
124 }
125
126
127 void disable_it8172_irq(unsigned int irq_nr)
128 {
129 DPRINTK("disable_it8172_irq %d\n", irq_nr);
130
131 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
132 /* LPC interrupt */
133 DPRINTK("disable, before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
134 it8172_hw0_icregs->lpc_mask |= (1 << (irq_nr - IT8172_LPC_IRQ_BASE));
135 DPRINTK("disable, after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
136 }
137 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
138 /* Local Bus interrupt */
139 DPRINTK("before lb_mask %x\n", it8172_hw0_icregs->lb_mask);
140 it8172_hw0_icregs->lb_mask |= (1 << (irq_nr - IT8172_LB_IRQ_BASE));
141 DPRINTK("after lb_mask %x\n", it8172_hw0_icregs->lb_mask);
142 }
143 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
144 /* PCI and other interrupts */
145 DPRINTK("before pci_mask %x\n", it8172_hw0_icregs->pci_mask);
146 it8172_hw0_icregs->pci_mask |= (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
147 DPRINTK("after pci_mask %x\n", it8172_hw0_icregs->pci_mask);
148 }
149 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
150 /* NMI interrupts */
151 DPRINTK("before nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
152 it8172_hw0_icregs->nmi_mask |= (1 << (irq_nr - IT8172_NMI_IRQ_BASE));
153 DPRINTK("after nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
154 }
155 else {
156 panic("disable_it8172_irq: bad irq %d\n", irq_nr);
157 }
158 }
159
160
161 void enable_it8172_irq(unsigned int irq_nr)
162 {
163 DPRINTK("enable_it8172_irq %d\n", irq_nr);
164 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
165 /* LPC interrupt */
166 DPRINTK("enable, before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
167 it8172_hw0_icregs->lpc_mask &= ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
168 DPRINTK("enable, after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask);
169 }
170 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
171 /* Local Bus interrupt */
172 DPRINTK("before lb_mask %x\n", it8172_hw0_icregs->lb_mask);
173 it8172_hw0_icregs->lb_mask &= ~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
174 DPRINTK("after lb_mask %x\n", it8172_hw0_icregs->lb_mask);
175 }
176 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
177 /* PCI and other interrupts */
178 DPRINTK("before pci_mask %x\n", it8172_hw0_icregs->pci_mask);
179 it8172_hw0_icregs->pci_mask &= ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
180 DPRINTK("after pci_mask %x\n", it8172_hw0_icregs->pci_mask);
181 }
182 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
183 /* NMI interrupts */
184 DPRINTK("before nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
185 it8172_hw0_icregs->nmi_mask &= ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
186 DPRINTK("after nmi_mask %x\n", it8172_hw0_icregs->nmi_mask);
187 }
188 else {
189 panic("enable_it8172_irq: bad irq %d\n", irq_nr);
190 }
191 }
192
193 static unsigned int startup_ite_irq(unsigned int irq)
194 {
195 enable_it8172_irq(irq);
196 return 0;
197 }
198
199 #define shutdown_ite_irq disable_it8172_irq
200 #define mask_and_ack_ite_irq disable_it8172_irq
201
202 static void end_ite_irq(unsigned int irq)
203 {
204 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
205 enable_it8172_irq(irq);
206 }
207
208 static struct hw_interrupt_type it8172_irq_type = {
209 "ITE8172",
210 startup_ite_irq,
211 shutdown_ite_irq,
212 enable_it8172_irq,
213 disable_it8172_irq,
214 mask_and_ack_ite_irq,
215 end_ite_irq,
216 NULL
217 };
218
219
220 int get_irq_list(char *buf)
221 {
222 int i, len = 0, j;
223 struct irqaction * action;
224
225 len += sprintf(buf+len, " ");
226 for (j=0; j<smp_num_cpus; j++)
227 len += sprintf(buf+len, "CPU%d ",j);
228 *(char *)(buf+len++) = '\n';
229
230 for (i = 0 ; i < NR_IRQS ; i++) {
231 action = irq_desc[i].action;
232 if ( !action || !action->handler )
233 continue;
234 len += sprintf(buf+len, "%3d: ", i);
235 len += sprintf(buf+len, "%10u ", kstat_irqs(i));
236 if ( irq_desc[i].handler )
237 len += sprintf(buf+len, " %s ", irq_desc[i].handler->typename );
238 else
239 len += sprintf(buf+len, " None ");
240 len += sprintf(buf+len, " %s",action->name);
241 for (action=action->next; action; action = action->next) {
242 len += sprintf(buf+len, ", %s", action->name);
243 }
244 len += sprintf(buf+len, "\n");
245 }
246 len += sprintf(buf+len, "BAD: %10lu\n", spurious_count);
247 return len;
248 }
249
250 asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
251 {
252 struct irqaction *action;
253 int cpu;
254
255 cpu = smp_processor_id();
256 irq_enter(cpu, irq);
257
258 kstat.irqs[cpu][irq]++;
259 #if 0
260 if (irq_desc[irq].handler && irq_desc[irq].handler->ack) {
261 // printk("invoking ack handler\n");
262 irq_desc[irq].handler->ack(irq);
263 }
264 #endif
265
266 action = irq_desc[irq].action;
267
268 if (action && action->handler)
269 {
270 //mask_irq(1<<irq);
271 //printk("action->handler %x\n", action->handler);
272 disable_it8172_irq(irq);
273 //if (!(action->flags & SA_INTERRUPT)) __sti(); /* reenable ints */
274 do {
275 action->handler(irq, action->dev_id, regs);
276 action = action->next;
277 } while ( action );
278 //__cli(); /* disable ints */
279 if (irq_desc[irq].handler)
280 {
281 }
282 //unmask_irq(1<<irq);
283 enable_it8172_irq(irq);
284 }
285 else
286 {
287 spurious_count++;
288 printk("Unhandled interrupt %d, cause %x, disabled\n",
289 (unsigned)irq, (unsigned)regs->cp0_cause);
290 disable_it8172_irq(irq);
291 }
292 irq_exit(cpu, irq);
293 }
294
295 int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *),
296 unsigned long irqflags, const char * devname, void *dev_id)
297 {
298 struct irqaction *old, **p, *action;
299 unsigned long flags;
300
301 /*
302 * IP0 and IP1 are software interrupts. IP7 is typically the timer interrupt.
303 *
304 * The ITE QED-4N-S01B board has one single interrupt line going from
305 * the system controller to the CPU. It's connected to the CPU external
306 * irq pin 1, which is IP2. The interrupt numbers are listed in it8172_int.h;
307 * the ISA interrupts are numbered from 0 to 15, and the rest go from
308 * there.
309 */
310
311 //printk("request_irq: %d handler %x\n", irq, handler);
312 if (irq >= NR_IRQS)
313 return -EINVAL;
314
315 if (!handler)
316 {
317 /* Free */
318 for (p = &irq_desc[irq].action; (action = *p) != NULL; p = &action->next)
319 {
320 /* Found it - now free it */
321 save_flags(flags);
322 cli();
323 *p = action->next;
324 disable_it8172_irq(irq);
325 restore_flags(flags);
326 kfree(action);
327 return 0;
328 }
329 return -ENOENT;
330 }
331
332 action = (struct irqaction *)
333 kmalloc(sizeof(struct irqaction), GFP_KERNEL);
334 if (!action)
335 return -ENOMEM;
336 memset(action, 0, sizeof(struct irqaction));
337
338 save_flags(flags);
339 cli();
340
341 action->handler = handler;
342 action->flags = irqflags;
343 action->mask = 0;
344 action->name = devname;
345 action->dev_id = dev_id;
346 action->next = NULL;
347
348 p = &irq_desc[irq].action;
349
350 if ((old = *p) != NULL) {
351 /* Can't share interrupts unless both agree to */
352 if (!(old->flags & action->flags & SA_SHIRQ))
353 return -EBUSY;
354 /* add new interrupt at end of irq queue */
355 do {
356 p = &old->next;
357 old = *p;
358 } while (old);
359 }
360 *p = action;
361 enable_it8172_irq(irq);
362 restore_flags(flags);
363 #if 0
364 printk("request_irq: status %x cause %x\n",
365 read_32bit_cp0_register(CP0_STATUS), read_32bit_cp0_register(CP0_CAUSE));
366 #endif
367 return 0;
368 }
369
370 void free_irq(unsigned int irq, void *dev_id)
371 {
372 request_irq(irq, NULL, 0, NULL, dev_id);
373 }
374
375 void enable_cpu_timer(void)
376 {
377 unsigned long flags;
378
379 save_and_cli(flags);
380 unmask_irq(1<<EXT_IRQ5_TO_IP); /* timer interrupt */
381 restore_flags(flags);
382 }
383
384 unsigned long probe_irq_on (void)
385 {
386 return 0;
387 }
388
389 int probe_irq_off (unsigned long irqs)
390 {
391 return 0;
392 }
393
394
395 void __init init_IRQ(void)
396 {
397 int i;
398 unsigned long flags;
399
400
401 memset(irq_desc, 0, sizeof(irq_desc));
402 set_except_vector(0, it8172_IRQ);
403
404 /* mask all interrupts */
405 it8172_hw0_icregs->lb_mask = 0xffff;
406 it8172_hw0_icregs->lpc_mask = 0xffff;
407 it8172_hw0_icregs->pci_mask = 0xffff;
408 it8172_hw0_icregs->nmi_mask = 0xffff;
409
410 /* make all interrupts level triggered */
411 it8172_hw0_icregs->lb_trigger = 0;
412 it8172_hw0_icregs->lpc_trigger = 0;
413 it8172_hw0_icregs->pci_trigger = 0;
414 it8172_hw0_icregs->nmi_trigger = 0;
415
416 /* active level setting */
417 /* uart, keyboard, and mouse are active high */
418 it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
419 it8172_hw0_icregs->lb_level |= 0x20;
420
421 /* keyboard and mouse are edge triggered */
422 it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
423
424
425 #if 0
426 // Enable this piece of code to make internal USB interrupt
427 // edge triggered.
428 it8172_hw0_icregs->pci_trigger |=
429 (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
430 it8172_hw0_icregs->pci_level &=
431 ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
432 #endif
433
434 for (i = 0; i <= IT8172_INT_END; i++) {
435 irq_desc[i].status = IRQ_DISABLED;
436 irq_desc[i].action = 0;
437 irq_desc[i].depth = 1;
438 irq_desc[i].handler = &it8172_irq_type;
439 }
440
441 /*
442 * Enable external int line 2
443 * All ITE interrupts are masked for now.
444 */
445 save_and_cli(flags);
446 unmask_irq(1<<EXT_IRQ0_TO_IP);
447 restore_flags(flags);
448
449 #ifdef CONFIG_REMOTE_DEBUG
450 /* If local serial I/O used for debug port, enter kgdb at once */
451 puts("Waiting for kgdb to connect...");
452 set_debug_traps();
453 breakpoint();
454 #endif
455 }
456
457 void mips_spurious_interrupt(struct pt_regs *regs)
458 {
459 #if 1
460 return;
461 #else
462 unsigned long status, cause;
463
464 printk("got spurious interrupt\n");
465 status = read_32bit_cp0_register(CP0_STATUS);
466 cause = read_32bit_cp0_register(CP0_CAUSE);
467 printk("status %x cause %x\n", status, cause);
468 printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
469 // while(1);
470 #endif
471 }
472
473 void it8172_hw0_irqdispatch(struct pt_regs *regs)
474 {
475 int irq;
476 unsigned short intstatus, status;
477
478 intstatus = it8172_hw0_icregs->intstatus;
479 if (intstatus & 0x8) {
480 panic("Got NMI interrupt\n");
481 }
482 else if (intstatus & 0x4) {
483 /* PCI interrupt */
484 irq = 0;
485 status = it8172_hw0_icregs->pci_req;
486 while (!(status & 0x1)) {
487 irq++;
488 status >>= 1;
489 }
490 irq += IT8172_PCI_DEV_IRQ_BASE;
491 //printk("pci int %d\n", irq);
492 }
493 else if (intstatus & 0x1) {
494 /* Local Bus interrupt */
495 irq = 0;
496 status = it8172_hw0_icregs->lb_req;
497 while (!(status & 0x1)) {
498 irq++;
499 status >>= 1;
500 }
501 irq += IT8172_LB_IRQ_BASE;
502 //printk("lb int %d\n", irq);
503 }
504 else if (intstatus & 0x2) {
505 /* LPC interrupt */
506 /* Since some lpc interrupts are edge triggered,
507 * we could lose an interrupt this way because
508 * we acknowledge all ints at onces. Revisit.
509 */
510 status = it8172_hw0_icregs->lpc_req;
511 it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
512 irq = 0;
513 while (!(status & 0x1)) {
514 irq++;
515 status >>= 1;
516 }
517 irq += IT8172_LPC_IRQ_BASE;
518 //printk("LPC int %d\n", irq);
519 }
520 else {
521 return;
522 }
523 do_IRQ(irq, regs);
524 }
525
526 void show_pending_irqs(void)
527 {
528 fputs("intstatus: ");
529 put32(it8172_hw0_icregs->intstatus);
530 puts("");
531
532 fputs("pci_req: ");
533 put32(it8172_hw0_icregs->pci_req);
534 puts("");
535
536 fputs("lb_req: ");
537 put32(it8172_hw0_icregs->lb_req);
538 puts("");
539
540 fputs("lpc_req: ");
541 put32(it8172_hw0_icregs->lpc_req);
542 puts("");
543 }
544