File: /usr/src/linux/arch/mips/kernel/i8259.c

1     /*
2      * This file is subject to the terms and conditions of the GNU General Public
3      * License.  See the file "COPYING" in the main directory of this archive
4      * for more details.
5      *
6      * Code to handle x86 style IRQs plus some generic interrupt stuff.
7      *
8      * Copyright (C) 1992 Linus Torvalds
9      * Copyright (C) 1994 - 2000 Ralf Baechle
10      */
11     #include <linux/delay.h>
12     #include <linux/init.h>
13     #include <linux/ioport.h>
14     #include <linux/irq.h>
15     #include <linux/interrupt.h>
16     #include <linux/kernel.h>
17     #include <linux/spinlock.h>
18     
19     #include <asm/io.h>
20     
21     void enable_8259A_irq(unsigned int irq);
22     void disable_8259A_irq(unsigned int irq);
23     
24     /*
25      * This is the 'legacy' 8259A Programmable Interrupt Controller,
26      * present in the majority of PC/AT boxes.
27      * plus some generic x86 specific things if generic specifics makes
28      * any sense at all.
29      * this file should become arch/i386/kernel/irq.c when the old irq.c
30      * moves to arch independent land
31      */
32     
33     spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
34     
35     static void end_8259A_irq (unsigned int irq)
36     {
37     	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
38     		enable_8259A_irq(irq);
39     }
40     
41     #define shutdown_8259A_irq	disable_8259A_irq
42     
43     void mask_and_ack_8259A(unsigned int);
44     
45     static unsigned int startup_8259A_irq(unsigned int irq)
46     { 
47     	enable_8259A_irq(irq);
48     
49     	return 0; /* never anything pending */
50     }
51     
52     static struct hw_interrupt_type i8259A_irq_type = {
53     	"XT-PIC",
54     	startup_8259A_irq,
55     	shutdown_8259A_irq,
56     	enable_8259A_irq,
57     	disable_8259A_irq,
58     	mask_and_ack_8259A,
59     	end_8259A_irq,
60     	NULL
61     };
62     
63     /*
64      * 8259A PIC functions to handle ISA devices:
65      */
66     
67     /*
68      * This contains the irq mask for both 8259A irq controllers,
69      */
70     static unsigned int cached_irq_mask = 0xffff;
71     
72     #define __byte(x,y) 	(((unsigned char *)&(y))[x])
73     #define cached_21	(__byte(0,cached_irq_mask))
74     #define cached_A1	(__byte(1,cached_irq_mask))
75     
76     void disable_8259A_irq(unsigned int irq)
77     {
78     	unsigned int mask = 1 << irq;
79     	unsigned long flags;
80     
81     	spin_lock_irqsave(&i8259A_lock, flags);
82     	cached_irq_mask |= mask;
83     	if (irq & 8)
84     		outb(cached_A1,0xA1);
85     	else
86     		outb(cached_21,0x21);
87     	spin_unlock_irqrestore(&i8259A_lock, flags);
88     }
89     
90     void enable_8259A_irq(unsigned int irq)
91     {
92     	unsigned int mask = ~(1 << irq);
93     	unsigned long flags;
94     
95     	spin_lock_irqsave(&i8259A_lock, flags);
96     	cached_irq_mask &= mask;
97     	if (irq & 8)
98     		outb(cached_A1,0xA1);
99     	else
100     		outb(cached_21,0x21);
101     	spin_unlock_irqrestore(&i8259A_lock, flags);
102     }
103     
104     int i8259A_irq_pending(unsigned int irq)
105     {
106     	unsigned int mask = 1 << irq;
107     	unsigned long flags;
108     	int ret;
109     
110     	spin_lock_irqsave(&i8259A_lock, flags);
111     	if (irq < 8)
112     		ret = inb(0x20) & mask;
113     	else
114     		ret = inb(0xA0) & (mask >> 8);
115     	spin_unlock_irqrestore(&i8259A_lock, flags);
116     
117     	return ret;
118     }
119     
120     void make_8259A_irq(unsigned int irq)
121     {
122     	disable_irq_nosync(irq);
123     	irq_desc[irq].handler = &i8259A_irq_type;
124     	enable_irq(irq);
125     }
126     
127     /*
128      * This function assumes to be called rarely. Switching between
129      * 8259A registers is slow.
130      * This has to be protected by the irq controller spinlock
131      * before being called.
132      */
133     static inline int i8259A_irq_real(unsigned int irq)
134     {
135     	int value;
136     	int irqmask = 1 << irq;
137     
138     	if (irq < 8) {
139     		outb(0x0B,0x20);		/* ISR register */
140     		value = inb(0x20) & irqmask;
141     		outb(0x0A,0x20);		/* back to the IRR register */
142     		return value;
143     	}
144     	outb(0x0B,0xA0);		/* ISR register */
145     	value = inb(0xA0) & (irqmask >> 8);
146     	outb(0x0A,0xA0);		/* back to the IRR register */
147     	return value;
148     }
149     
150     /*
151      * Careful! The 8259A is a fragile beast, it pretty
152      * much _has_ to be done exactly like this (mask it
153      * first, _then_ send the EOI, and the order of EOI
154      * to the two 8259s is important!
155      */
156     void mask_and_ack_8259A(unsigned int irq)
157     {
158     	unsigned int irqmask = 1 << irq;
159     	unsigned long flags;
160     
161     	spin_lock_irqsave(&i8259A_lock, flags);
162     	/*
163     	 * Lightweight spurious IRQ detection. We do not want to overdo
164     	 * spurious IRQ handling - it's usually a sign of hardware problems, so
165     	 * we only do the checks we can do without slowing down good hardware
166     	 * nnecesserily.
167     	 *
168     	 * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting
169     	 * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A.
170     	 * Thus we can check spurious 8259A IRQs without doing the quite slow
171     	 * i8259A_irq_real() call for every IRQ.  This does not cover 100% of
172     	 * spurious interrupts, but should be enough to warn the user that
173     	 * there is something bad going on ...
174     	 */
175     	if (cached_irq_mask & irqmask)
176     		goto spurious_8259A_irq;
177     	cached_irq_mask |= irqmask;
178     
179     handle_real_irq:
180     	if (irq & 8) {
181     		inb(0xA1);		/* DUMMY - (do we need this?) */
182     		outb(cached_A1,0xA1);
183     		outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
184     		outb(0x62,0x20);	/* 'Specific EOI' to master-IRQ2 */
185     	} else {
186     		inb(0x21);		/* DUMMY - (do we need this?) */
187     		outb(cached_21,0x21);
188     		outb(0x60+irq,0x20);	/* 'Specific EOI' to master */
189     	}
190     	spin_unlock_irqrestore(&i8259A_lock, flags);
191     	return;
192     
193     spurious_8259A_irq:
194     	/*
195     	 * this is the slow path - should happen rarely.
196     	 */
197     	if (i8259A_irq_real(irq))
198     		/*
199     		 * oops, the IRQ _is_ in service according to the
200     		 * 8259A - not spurious, go handle it.
201     		 */
202     		goto handle_real_irq;
203     
204     	{
205     		static int spurious_irq_mask = 0;
206     		/*
207     		 * At this point we can be sure the IRQ is spurious,
208     		 * lets ACK and report it. [once per IRQ]
209     		 */
210     		if (!(spurious_irq_mask & irqmask)) {
211     			printk("spurious 8259A interrupt: IRQ%d.\n", irq);
212     			spurious_irq_mask |= irqmask;
213     		}
214     		irq_err_count++;
215     		/*
216     		 * Theoretically we do not have to handle this IRQ,
217     		 * but in Linux this does not cause problems and is
218     		 * simpler for us.
219     		 */
220     		goto handle_real_irq;
221     	}
222     }
223     
224     void __init init_8259A(int auto_eoi)
225     {
226     	unsigned long flags;
227     
228     	spin_lock_irqsave(&i8259A_lock, flags);
229     
230     	outb(0xff, 0x21);	/* mask all of 8259A-1 */
231     	outb(0xff, 0xA1);	/* mask all of 8259A-2 */
232     
233     	/*
234     	 * outb_p - this has to work on a wide range of PC hardware.
235     	 */
236     	outb_p(0x11, 0x20);	/* ICW1: select 8259A-1 init */
237     	outb_p(0x20 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
238     	outb_p(0x04, 0x21);	/* 8259A-1 (the master) has a slave on IR2 */
239     	if (auto_eoi)
240     		outb_p(0x03, 0x21);	/* master does Auto EOI */
241     	else
242     		outb_p(0x01, 0x21);	/* master expects normal EOI */
243     
244     	outb_p(0x11, 0xA0);	/* ICW1: select 8259A-2 init */
245     	outb_p(0x20 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
246     	outb_p(0x02, 0xA1);	/* 8259A-2 is a slave on master's IR2 */
247     	outb_p(0x01, 0xA1);	/* (slave's support for AEOI in flat mode
248     				    is to be investigated) */
249     
250     	if (auto_eoi)
251     		/*
252     		 * in AEOI mode we just have to mask the interrupt
253     		 * when acking.
254     		 */
255     		i8259A_irq_type.ack = disable_8259A_irq;
256     	else
257     		i8259A_irq_type.ack = mask_and_ack_8259A;
258     
259     	udelay(100);		/* wait for 8259A to initialize */
260     
261     	outb(cached_21, 0x21);	/* restore master IRQ mask */
262     	outb(cached_A1, 0xA1);	/* restore slave IRQ mask */
263     
264     	spin_unlock_irqrestore(&i8259A_lock, flags);
265     }
266     
267     asmlinkage void i8259_do_irq(int irq, struct pt_regs regs)
268     {
269     	panic("i8259_do_irq: I want to be implemented");
270     }
271     
272     /*
273      * IRQ2 is cascade interrupt to second interrupt controller
274      */
275     static struct irqaction irq2 = {
276     	no_action, 0, 0, "cascade", NULL, NULL
277     };
278     
279     static struct resource pic1_io_resource = {
280     	"pic1", 0x20, 0x3f, IORESOURCE_BUSY
281     };
282     
283     static struct resource pic2_io_resource = {
284     	"pic2", 0xa0, 0xbf, IORESOURCE_BUSY
285     };
286     
287     /*
288      * On systems with i8259-style interrupt controllers we assume for
289      * driver compatibility reasons interrupts 0 - 15 to be the i8295
290      * interrupts even if the hardware uses a different interrupt numbering.
291      */
292     void __init init_i8259_irqs (void)
293     {
294     	int i;
295     
296     	request_resource(&ioport_resource, &pic1_io_resource);
297     	request_resource(&ioport_resource, &pic2_io_resource);
298     
299     	init_8259A(0);
300     
301     	for (i = 0; i < 16; i++) {
302     		irq_desc[i].status = IRQ_DISABLED;
303     		irq_desc[i].action = 0;
304     		irq_desc[i].depth = 1;
305     		irq_desc[i].handler = &i8259A_irq_type;
306     	}
307     
308     	setup_irq(2, &irq2);
309     }
310