File: /usr/src/linux/arch/mips/mips-boards/generic/pci.c
1 /*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * MIPS boards specific PCI support.
19 *
20 */
21 #include <linux/config.h>
22
23 #ifdef CONFIG_PCI
24
25 #include <linux/types.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29
30 #include <asm/mips-boards/generic.h>
31 #include <asm/gt64120.h>
32 #ifdef CONFIG_MIPS_MALTA
33 #include <asm/mips-boards/malta.h>
34 #endif
35
36 #define PCI_ACCESS_READ 0
37 #define PCI_ACCESS_WRITE 1
38
39 static int
40 mips_pcibios_config_access(unsigned char access_type, struct pci_dev *dev,
41 unsigned char where, u32 *data)
42 {
43 unsigned char bus = dev->bus->number;
44 unsigned char dev_fn = dev->devfn;
45 u32 intr;
46
47 if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0)))
48 return -1; /* Because of a bug in the galileo (for slot 31). */
49
50 /* Clear cause register bits */
51 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
52 GT_INTRCAUSE_TARABORT0_BIT));
53
54 /* Setup address */
55 GT_WRITE(GT_PCI0_CFGADDR_OFS,
56 (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
57 (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
58 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
59 GT_PCI0_CFGADDR_CONFIGEN_BIT);
60
61 if (access_type == PCI_ACCESS_WRITE) {
62 if (bus == 0 && dev_fn == 0) {
63 /*
64 * Galileo is acting differently than other devices.
65 */
66 GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
67 } else {
68 GT_PCI_WRITE(GT_PCI0_CFGDATA_OFS, *data);
69 }
70 } else {
71 if (bus == 0 && dev_fn == 0) {
72 /*
73 * Galileo is acting differently than other devices.
74 */
75 GT_READ(GT_PCI0_CFGDATA_OFS, *data);
76 } else {
77 GT_PCI_READ(GT_PCI0_CFGDATA_OFS, *data);
78 }
79 }
80
81 /* Check for master or target abort */
82 GT_READ(GT_INTRCAUSE_OFS, intr);
83
84 if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT))
85 {
86 /* Error occured */
87
88 /* Clear bits */
89 GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
90 GT_INTRCAUSE_TARABORT0_BIT) );
91
92 return -1;
93 }
94
95 return 0;
96 }
97
98
99 /*
100 * We can't address 8 and 16 bit words directly. Instead we have to
101 * read/write a 32bit word and mask/modify the data we actually want.
102 */
103 static int
104 mips_pcibios_read_config_byte (struct pci_dev *dev, int where, u8 *val)
105 {
106 u32 data = 0;
107
108 if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
109 return -1;
110
111 *val = (data >> ((where & 3) << 3)) & 0xff;
112
113 return PCIBIOS_SUCCESSFUL;
114 }
115
116
117 static int
118 mips_pcibios_read_config_word (struct pci_dev *dev, int where, u16 *val)
119 {
120 u32 data = 0;
121
122 if (where & 1)
123 return PCIBIOS_BAD_REGISTER_NUMBER;
124
125 if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
126 return -1;
127
128 *val = (data >> ((where & 3) << 3)) & 0xffff;
129
130 return PCIBIOS_SUCCESSFUL;
131 }
132
133 static int
134 mips_pcibios_read_config_dword (struct pci_dev *dev, int where, u32 *val)
135 {
136 u32 data = 0;
137
138 if (where & 3)
139 return PCIBIOS_BAD_REGISTER_NUMBER;
140
141 if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
142 return -1;
143
144 *val = data;
145
146 return PCIBIOS_SUCCESSFUL;
147 }
148
149
150 static int
151 mips_pcibios_write_config_byte (struct pci_dev *dev, int where, u8 val)
152 {
153 u32 data = 0;
154
155 if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
156 return -1;
157
158 data = (data & ~(0xff << ((where & 3) << 3))) |
159 (val << ((where & 3) << 3));
160
161 if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data))
162 return -1;
163
164 return PCIBIOS_SUCCESSFUL;
165 }
166
167 static int
168 mips_pcibios_write_config_word (struct pci_dev *dev, int where, u16 val)
169 {
170 u32 data = 0;
171
172 if (where & 1)
173 return PCIBIOS_BAD_REGISTER_NUMBER;
174
175 if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
176 return -1;
177
178 data = (data & ~(0xffff << ((where & 3) << 3))) |
179 (val << ((where & 3) << 3));
180
181 if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data))
182 return -1;
183
184
185 return PCIBIOS_SUCCESSFUL;
186 }
187
188 static int
189 mips_pcibios_write_config_dword(struct pci_dev *dev, int where, u32 val)
190 {
191 if (where & 3)
192 return PCIBIOS_BAD_REGISTER_NUMBER;
193
194 if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &val))
195 return -1;
196
197 return PCIBIOS_SUCCESSFUL;
198 }
199
200 struct pci_ops mips_pci_ops = {
201 mips_pcibios_read_config_byte,
202 mips_pcibios_read_config_word,
203 mips_pcibios_read_config_dword,
204 mips_pcibios_write_config_byte,
205 mips_pcibios_write_config_word,
206 mips_pcibios_write_config_dword
207 };
208
209 void __init pcibios_init(void)
210 {
211 #ifdef CONFIG_MIPS_MALTA
212 struct pci_dev *pdev;
213 unsigned char reg_val;
214 #endif
215
216 printk("PCI: Probing PCI hardware on host bus 0.\n");
217 pci_scan_bus(0, &mips_pci_ops, NULL);
218
219 /*
220 * Due to a bug in the Galileo system controller, we need to setup
221 * the PCI BAR for the Galileo internal registers.
222 * This should be done in the bios/bootprom and will be fixed in
223 * a later revision of YAMON (the MIPS boards boot prom).
224 */
225 GT_WRITE(GT_PCI0_CFGADDR_OFS,
226 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
227 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 device */
228 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */
229 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */
230 GT_PCI0_CFGADDR_CONFIGEN_BIT );
231
232 /* Perform the write */
233 GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(MIPS_GT_BASE));
234
235 #ifdef CONFIG_MIPS_MALTA
236 pci_for_each_dev(pdev) {
237 if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
238 && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB)
239 && (PCI_SLOT(pdev->devfn) == 0x0a)) {
240 /*
241 * IDE Decode enable.
242 */
243 pci_read_config_byte(pdev, 0x41, ®_val);
244 pci_write_config_byte(pdev, 0x41, reg_val | 0x80);
245 pci_read_config_byte(pdev, 0x43, ®_val);
246 pci_write_config_byte(pdev, 0x43, reg_val | 0x80);
247 }
248
249 if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
250 && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0)
251 && (PCI_SLOT(pdev->devfn) == 0x0a)) {
252 /*
253 * Set top of main memory accessible by ISA or DMA
254 * devices to 16 Mb.
255 */
256 pci_read_config_byte(pdev, 0x69, ®_val);
257 pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
258 }
259 }
260
261 /*
262 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
263 * Controller.
264 * This should be done in the bios/bootprom and will be fixed in
265 * a later revision of YAMON (the MIPS boards boot prom).
266 */
267 /* Entering config state. */
268 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
269
270 /* Activate floppy controller. */
271 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
272 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
273 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
274 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
275
276 /* Exit config state. */
277 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
278 #endif
279 }
280
281 int __init
282 pcibios_enable_device(struct pci_dev *dev)
283 {
284 /* Not needed, since we enable all devices at startup. */
285 return 0;
286 }
287
288 void __init
289 pcibios_align_resource(void *data, struct resource *res, unsigned long size)
290 {
291 }
292
293 char * __init
294 pcibios_setup(char *str)
295 {
296 /* Nothing to do for now. */
297
298 return str;
299 }
300
301 struct pci_fixup pcibios_fixups[] = {
302 { 0 }
303 };
304
305 void __init
306 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
307 struct resource *res, int resource)
308 {
309 unsigned long where, size;
310 u32 reg;
311
312 where = PCI_BASE_ADDRESS_0 + (resource * 4);
313 size = res->end - res->start;
314 pci_read_config_dword(dev, where, ®);
315 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
316 pci_write_config_dword(dev, where, reg);
317 }
318
319 /*
320 * Called after each bus is probed, but before its children
321 * are examined.
322 */
323 void __init pcibios_fixup_bus(struct pci_bus *b)
324 {
325 pci_read_bridge_bases(b);
326 }
327
328 unsigned __init int pcibios_assign_all_busses(void)
329 {
330 return 1;
331 }
332
333 #endif /* CONFIG_PCI */
334