File: /usr/src/linux/arch/mips/mm/mips32.c
1 /*
2 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * MIPS32 CPU variant specific MMU/Cache routines.
19 */
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/mm.h>
24
25 #include <asm/bootinfo.h>
26 #include <asm/cpu.h>
27 #include <asm/bcache.h>
28 #include <asm/io.h>
29 #include <asm/page.h>
30 #include <asm/pgtable.h>
31 #include <asm/system.h>
32 #include <asm/mmu_context.h>
33
34 /* CP0 hazard avoidance. */
35 #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
36 "nop; nop; nop; nop; nop; nop;\n\t" \
37 ".set reorder\n\t")
38
39 /* Primary cache parameters. */
40 static int icache_size, dcache_size; /* Size in bytes */
41 static int ic_lsize, dc_lsize; /* LineSize in bytes */
42
43 /* Secondary cache (if present) parameters. */
44 static unsigned int scache_size, sc_lsize; /* Again, in bytes */
45
46 #include <asm/cacheops.h>
47 #include <asm/mips32_cache.h>
48
49 #undef DEBUG_CACHE
50
51 /*
52 * Dummy cache handling routines for machines without boardcaches
53 */
54 static void no_sc_noop(void) {}
55
56 static struct bcache_ops no_sc_ops = {
57 (void *)no_sc_noop, (void *)no_sc_noop,
58 (void *)no_sc_noop, (void *)no_sc_noop
59 };
60
61 struct bcache_ops *bcops = &no_sc_ops;
62
63
64 /*
65 * Zero an entire page.
66 */
67
68 static void mips32_clear_page_dc(unsigned long page)
69 {
70 unsigned long i;
71
72 if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
73 for (i=page; i<page+PAGE_SIZE; i+=dc_lsize) {
74 __asm__ __volatile__(
75 ".set\tnoreorder\n\t"
76 ".set\tnoat\n\t"
77 ".set\tmips3\n\t"
78 "cache\t%2,(%0)\n\t"
79 ".set\tmips0\n\t"
80 ".set\tat\n\t"
81 ".set\treorder"
82 :"=r" (i)
83 :"0" (i),
84 "I" (Create_Dirty_Excl_D));
85 }
86 }
87 for (i=page; i<page+PAGE_SIZE; i+=4)
88 *(unsigned long *)(i) = 0;
89 }
90
91 static void mips32_clear_page_sc(unsigned long page)
92 {
93 unsigned long i;
94
95 if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
96 for (i=page; i<page+PAGE_SIZE; i+=sc_lsize) {
97 __asm__ __volatile__(
98 ".set\tnoreorder\n\t"
99 ".set\tnoat\n\t"
100 ".set\tmips3\n\t"
101 "cache\t%2,(%0)\n\t"
102 ".set\tmips0\n\t"
103 ".set\tat\n\t"
104 ".set\treorder"
105 :"=r" (i)
106 :"0" (i),
107 "I" (Create_Dirty_Excl_SD));
108 }
109 }
110 for (i=page; i<page+PAGE_SIZE; i+=4)
111 *(unsigned long *)(i) = 0;
112 }
113
114 static void mips32_copy_page_dc(unsigned long to, unsigned long from)
115 {
116 unsigned long i;
117
118 if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
119 for (i=to; i<to+PAGE_SIZE; i+=dc_lsize) {
120 __asm__ __volatile__(
121 ".set\tnoreorder\n\t"
122 ".set\tnoat\n\t"
123 ".set\tmips3\n\t"
124 "cache\t%2,(%0)\n\t"
125 ".set\tmips0\n\t"
126 ".set\tat\n\t"
127 ".set\treorder"
128 :"=r" (i)
129 :"0" (i),
130 "I" (Create_Dirty_Excl_D));
131 }
132 }
133 for (i=0; i<PAGE_SIZE; i+=4)
134 *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
135 }
136
137 static void mips32_copy_page_sc(unsigned long to, unsigned long from)
138 {
139 unsigned long i;
140
141 if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
142 for (i=to; i<to+PAGE_SIZE; i+=sc_lsize) {
143 __asm__ __volatile__(
144 ".set\tnoreorder\n\t"
145 ".set\tnoat\n\t"
146 ".set\tmips3\n\t"
147 "cache\t%2,(%0)\n\t"
148 ".set\tmips0\n\t"
149 ".set\tat\n\t"
150 ".set\treorder"
151 :"=r" (i)
152 :"0" (i),
153 "I" (Create_Dirty_Excl_SD));
154 }
155 }
156 for (i=0; i<PAGE_SIZE; i+=4)
157 *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
158 }
159
160 static inline void mips32_flush_cache_all_sc(void)
161 {
162 unsigned long flags;
163
164 __save_and_cli(flags);
165 blast_dcache(); blast_icache(); blast_scache();
166 __restore_flags(flags);
167 }
168
169 static inline void mips32_flush_cache_all_pc(void)
170 {
171 unsigned long flags;
172
173 __save_and_cli(flags);
174 blast_dcache(); blast_icache();
175 __restore_flags(flags);
176 }
177
178 static void
179 mips32_flush_cache_range_sc(struct mm_struct *mm,
180 unsigned long start,
181 unsigned long end)
182 {
183 struct vm_area_struct *vma;
184 unsigned long flags;
185
186 if(mm->context == 0)
187 return;
188
189 start &= PAGE_MASK;
190 #ifdef DEBUG_CACHE
191 printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
192 #endif
193 vma = find_vma(mm, start);
194 if(vma) {
195 if(mm->context != current->mm->context) {
196 mips32_flush_cache_all_sc();
197 } else {
198 pgd_t *pgd;
199 pmd_t *pmd;
200 pte_t *pte;
201
202 __save_and_cli(flags);
203 while(start < end) {
204 pgd = pgd_offset(mm, start);
205 pmd = pmd_offset(pgd, start);
206 pte = pte_offset(pmd, start);
207
208 if(pte_val(*pte) & _PAGE_VALID)
209 blast_scache_page(start);
210 start += PAGE_SIZE;
211 }
212 __restore_flags(flags);
213 }
214 }
215 }
216
217 static void mips32_flush_cache_range_pc(struct mm_struct *mm,
218 unsigned long start,
219 unsigned long end)
220 {
221 if(mm->context != 0) {
222 unsigned long flags;
223
224 #ifdef DEBUG_CACHE
225 printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
226 #endif
227 __save_and_cli(flags);
228 blast_dcache(); blast_icache();
229 __restore_flags(flags);
230 }
231 }
232
233 /*
234 * On architectures like the Sparc, we could get rid of lines in
235 * the cache created only by a certain context, but on the MIPS
236 * (and actually certain Sparc's) we cannot.
237 */
238 static void mips32_flush_cache_mm_sc(struct mm_struct *mm)
239 {
240 if(mm->context != 0) {
241 #ifdef DEBUG_CACHE
242 printk("cmm[%d]", (int)mm->context);
243 #endif
244 mips32_flush_cache_all_sc();
245 }
246 }
247
248 static void mips32_flush_cache_mm_pc(struct mm_struct *mm)
249 {
250 if(mm->context != 0) {
251 #ifdef DEBUG_CACHE
252 printk("cmm[%d]", (int)mm->context);
253 #endif
254 mips32_flush_cache_all_pc();
255 }
256 }
257
258
259
260
261
262 static void mips32_flush_cache_page_sc(struct vm_area_struct *vma,
263 unsigned long page)
264 {
265 struct mm_struct *mm = vma->vm_mm;
266 unsigned long flags;
267 pgd_t *pgdp;
268 pmd_t *pmdp;
269 pte_t *ptep;
270
271 /*
272 * If ownes no valid ASID yet, cannot possibly have gotten
273 * this page into the cache.
274 */
275 if (mm->context == 0)
276 return;
277
278 #ifdef DEBUG_CACHE
279 printk("cpage[%d,%08lx]", (int)mm->context, page);
280 #endif
281 __save_and_cli(flags);
282 page &= PAGE_MASK;
283 pgdp = pgd_offset(mm, page);
284 pmdp = pmd_offset(pgdp, page);
285 ptep = pte_offset(pmdp, page);
286
287 /*
288 * If the page isn't marked valid, the page cannot possibly be
289 * in the cache.
290 */
291 if (!(pte_val(*ptep) & _PAGE_VALID))
292 goto out;
293
294 /*
295 * Doing flushes for another ASID than the current one is
296 * too difficult since R4k caches do a TLB translation
297 * for every cache flush operation. So we do indexed flushes
298 * in that case, which doesn't overly flush the cache too much.
299 */
300 if (mm->context != current->active_mm->context) {
301 /*
302 * Do indexed flush, too much work to get the (possible)
303 * tlb refills to work correctly.
304 */
305 page = (KSEG0 + (page & (scache_size - 1)));
306 blast_dcache_page_indexed(page);
307 blast_scache_page_indexed(page);
308 } else
309 blast_scache_page(page);
310 out:
311 __restore_flags(flags);
312 }
313
314 static void mips32_flush_cache_page_pc(struct vm_area_struct *vma,
315 unsigned long page)
316 {
317 struct mm_struct *mm = vma->vm_mm;
318 unsigned long flags;
319 pgd_t *pgdp;
320 pmd_t *pmdp;
321 pte_t *ptep;
322
323 /*
324 * If ownes no valid ASID yet, cannot possibly have gotten
325 * this page into the cache.
326 */
327 if (mm->context == 0)
328 return;
329
330 #ifdef DEBUG_CACHE
331 printk("cpage[%d,%08lx]", (int)mm->context, page);
332 #endif
333 __save_and_cli(flags);
334 page &= PAGE_MASK;
335 pgdp = pgd_offset(mm, page);
336 pmdp = pmd_offset(pgdp, page);
337 ptep = pte_offset(pmdp, page);
338
339 /*
340 * If the page isn't marked valid, the page cannot possibly be
341 * in the cache.
342 */
343 if (!(pte_val(*ptep) & _PAGE_VALID))
344 goto out;
345
346 /*
347 * Doing flushes for another ASID than the current one is
348 * too difficult since Mips32 caches do a TLB translation
349 * for every cache flush operation. So we do indexed flushes
350 * in that case, which doesn't overly flush the cache too much.
351 */
352 if (mm == current->active_mm) {
353 blast_dcache_page(page);
354 } else {
355 /* Do indexed flush, too much work to get the (possible)
356 * tlb refills to work correctly.
357 */
358 page = (KSEG0 + (page & (dcache_size - 1)));
359 blast_dcache_page_indexed(page);
360 }
361 out:
362 __restore_flags(flags);
363 }
364
365 /* If the addresses passed to these routines are valid, they are
366 * either:
367 *
368 * 1) In KSEG0, so we can do a direct flush of the page.
369 * 2) In KSEG2, and since every process can translate those
370 * addresses all the time in kernel mode we can do a direct
371 * flush.
372 * 3) In KSEG1, no flush necessary.
373 */
374 static void mips32_flush_page_to_ram_sc(struct page *page)
375 {
376 blast_scache_page((unsigned long)page_address(page));
377 }
378
379 static void mips32_flush_page_to_ram_pc(struct page *page)
380 {
381 blast_dcache_page((unsigned long)page_address(page));
382 }
383
384 static void
385 mips32_flush_icache_page_s(struct vm_area_struct *vma, struct page *page)
386 {
387 /*
388 * We did an scache flush therefore PI is already clean.
389 */
390 }
391
392 static void
393 mips32_flush_icache_range(unsigned long start, unsigned long end)
394 {
395 flush_cache_all();
396 }
397
398 static void
399 mips32_flush_icache_page(struct vm_area_struct *vma, struct page *page)
400 {
401 int address;
402
403 if (!(vma->vm_flags & VM_EXEC))
404 return;
405
406 address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1));
407 blast_icache_page_indexed(address);
408 }
409
410 /*
411 * Writeback and invalidate the primary cache dcache before DMA.
412 */
413 static void
414 mips32_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size)
415 {
416 unsigned long end, a;
417 unsigned int flags;
418
419 if (size >= dcache_size) {
420 flush_cache_all();
421 } else {
422 __save_and_cli(flags);
423 a = addr & ~(dc_lsize - 1);
424 end = (addr + size) & ~(dc_lsize - 1);
425 while (1) {
426 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
427 if (a == end) break;
428 a += dc_lsize;
429 }
430 __restore_flags(flags);
431 }
432 bc_wback_inv(addr, size);
433 }
434
435 static void
436 mips32_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size)
437 {
438 unsigned long end, a;
439
440 if (size >= scache_size) {
441 flush_cache_all();
442 return;
443 }
444
445 a = addr & ~(sc_lsize - 1);
446 end = (addr + size) & ~(sc_lsize - 1);
447 while (1) {
448 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
449 if (a == end) break;
450 a += sc_lsize;
451 }
452 }
453
454 static void
455 mips32_dma_cache_inv_pc(unsigned long addr, unsigned long size)
456 {
457 unsigned long end, a;
458 unsigned int flags;
459
460 if (size >= dcache_size) {
461 flush_cache_all();
462 } else {
463 __save_and_cli(flags);
464 a = addr & ~(dc_lsize - 1);
465 end = (addr + size) & ~(dc_lsize - 1);
466 while (1) {
467 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
468 if (a == end) break;
469 a += dc_lsize;
470 }
471 __restore_flags(flags);
472 }
473
474 bc_inv(addr, size);
475 }
476
477 static void
478 mips32_dma_cache_inv_sc(unsigned long addr, unsigned long size)
479 {
480 unsigned long end, a;
481
482 if (size >= scache_size) {
483 flush_cache_all();
484 return;
485 }
486
487 a = addr & ~(sc_lsize - 1);
488 end = (addr + size) & ~(sc_lsize - 1);
489 while (1) {
490 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
491 if (a == end) break;
492 a += sc_lsize;
493 }
494 }
495
496 static void
497 mips32_dma_cache_wback(unsigned long addr, unsigned long size)
498 {
499 panic("mips32_dma_cache called - should not happen.\n");
500 }
501
502 /*
503 * While we're protected against bad userland addresses we don't care
504 * very much about what happens in that case. Usually a segmentation
505 * fault will dump the process later on anyway ...
506 */
507 static void mips32_flush_cache_sigtramp(unsigned long addr)
508 {
509 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
510 protected_flush_icache_line(addr & ~(ic_lsize - 1));
511 }
512
513 #undef DEBUG_TLB
514 #undef DEBUG_TLBUPDATE
515
516 void flush_tlb_all(void)
517 {
518 unsigned long flags;
519 unsigned long old_ctx;
520 int entry;
521
522 #ifdef DEBUG_TLB
523 printk("[tlball]");
524 #endif
525
526 __save_and_cli(flags);
527 /* Save old context and create impossible VPN2 value */
528 old_ctx = (get_entryhi() & 0xff);
529 set_entryhi(KSEG0);
530 set_entrylo0(0);
531 set_entrylo1(0);
532 BARRIER;
533
534 entry = get_wired();
535
536 /* Blast 'em all away. */
537 while(entry < mips_cpu.tlbsize) {
538 /* Make sure all entries differ. */
539 set_entryhi(KSEG0+entry*0x2000);
540 set_index(entry);
541 BARRIER;
542 tlb_write_indexed();
543 BARRIER;
544 entry++;
545 }
546 BARRIER;
547 set_entryhi(old_ctx);
548 __restore_flags(flags);
549 }
550
551 void flush_tlb_mm(struct mm_struct *mm)
552 {
553 if (mm->context != 0) {
554 unsigned long flags;
555
556 #ifdef DEBUG_TLB
557 printk("[tlbmm<%d>]", mm->context);
558 #endif
559 __save_and_cli(flags);
560 get_new_mmu_context(mm, asid_cache);
561 if (mm == current->active_mm)
562 set_entryhi(mm->context & 0xff);
563 __restore_flags(flags);
564 }
565 }
566
567 void flush_tlb_range(struct mm_struct *mm, unsigned long start,
568 unsigned long end)
569 {
570 if(mm->context != 0) {
571 unsigned long flags;
572 int size;
573
574 #ifdef DEBUG_TLB
575 printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff),
576 start, end);
577 #endif
578 __save_and_cli(flags);
579 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
580 size = (size + 1) >> 1;
581 if(size <= mips_cpu.tlbsize/2) {
582 int oldpid = (get_entryhi() & 0xff);
583 int newpid = (mm->context & 0xff);
584
585 start &= (PAGE_MASK << 1);
586 end += ((PAGE_SIZE << 1) - 1);
587 end &= (PAGE_MASK << 1);
588 while(start < end) {
589 int idx;
590
591 set_entryhi(start | newpid);
592 start += (PAGE_SIZE << 1);
593 BARRIER;
594 tlb_probe();
595 BARRIER;
596 idx = get_index();
597 set_entrylo0(0);
598 set_entrylo1(0);
599 if(idx < 0)
600 continue;
601 /* Make sure all entries differ. */
602 set_entryhi(KSEG0+idx*0x2000);
603 BARRIER;
604 tlb_write_indexed();
605 BARRIER;
606 }
607 set_entryhi(oldpid);
608 } else {
609 get_new_mmu_context(mm, asid_cache);
610 if (mm == current->active_mm)
611 set_entryhi(mm->context & 0xff);
612 }
613 __restore_flags(flags);
614 }
615 }
616
617 void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
618 {
619 if (vma->vm_mm->context != 0) {
620 unsigned long flags;
621 int oldpid, newpid, idx;
622
623 #ifdef DEBUG_TLB
624 printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page);
625 #endif
626 newpid = (vma->vm_mm->context & 0xff);
627 page &= (PAGE_MASK << 1);
628 __save_and_cli(flags);
629 oldpid = (get_entryhi() & 0xff);
630 set_entryhi(page | newpid);
631 BARRIER;
632 tlb_probe();
633 BARRIER;
634 idx = get_index();
635 set_entrylo0(0);
636 set_entrylo1(0);
637 if(idx < 0)
638 goto finish;
639 /* Make sure all entries differ. */
640 set_entryhi(KSEG0+idx*0x2000);
641 BARRIER;
642 tlb_write_indexed();
643
644 finish:
645 BARRIER;
646 set_entryhi(oldpid);
647 __restore_flags(flags);
648 }
649 }
650
651 void pgd_init(unsigned long page)
652 {
653 unsigned long *p = (unsigned long *) page;
654 int i;
655
656 for(i = 0; i < USER_PTRS_PER_PGD; i+=8) {
657 p[i + 0] = (unsigned long) invalid_pte_table;
658 p[i + 1] = (unsigned long) invalid_pte_table;
659 p[i + 2] = (unsigned long) invalid_pte_table;
660 p[i + 3] = (unsigned long) invalid_pte_table;
661 p[i + 4] = (unsigned long) invalid_pte_table;
662 p[i + 5] = (unsigned long) invalid_pte_table;
663 p[i + 6] = (unsigned long) invalid_pte_table;
664 p[i + 7] = (unsigned long) invalid_pte_table;
665 }
666 }
667
668 /*
669 * Updates the TLB with the new pte(s).
670 */
671 void update_mmu_cache(struct vm_area_struct * vma,
672 unsigned long address, pte_t pte)
673 {
674 unsigned long flags;
675 pgd_t *pgdp;
676 pmd_t *pmdp;
677 pte_t *ptep;
678 int idx, pid;
679
680 /*
681 * Handle debugger faulting in for debugee.
682 */
683 if (current->active_mm != vma->vm_mm)
684 return;
685
686 pid = get_entryhi() & 0xff;
687
688 #ifdef DEBUG_TLB
689 if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) {
690 printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n",
691 (int) (vma->vm_mm->context & 0xff), pid);
692 }
693 #endif
694
695 __save_and_cli(flags);
696 address &= (PAGE_MASK << 1);
697 set_entryhi(address | (pid));
698 pgdp = pgd_offset(vma->vm_mm, address);
699 BARRIER;
700 tlb_probe();
701 BARRIER;
702 pmdp = pmd_offset(pgdp, address);
703 idx = get_index();
704 ptep = pte_offset(pmdp, address);
705 BARRIER;
706 set_entrylo0(pte_val(*ptep++) >> 6);
707 set_entrylo1(pte_val(*ptep) >> 6);
708 set_entryhi(address | (pid));
709 BARRIER;
710 if(idx < 0) {
711 tlb_write_random();
712 } else {
713 tlb_write_indexed();
714 }
715 BARRIER;
716 set_entryhi(pid);
717 BARRIER;
718 __restore_flags(flags);
719 }
720
721 void show_regs(struct pt_regs * regs)
722 {
723 /* Saved main processor registers. */
724 printk("$0 : %08lx %08lx %08lx %08lx\n",
725 0UL, regs->regs[1], regs->regs[2], regs->regs[3]);
726 printk("$4 : %08lx %08lx %08lx %08lx\n",
727 regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
728 printk("$8 : %08lx %08lx %08lx %08lx\n",
729 regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]);
730 printk("$12: %08lx %08lx %08lx %08lx\n",
731 regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
732 printk("$16: %08lx %08lx %08lx %08lx\n",
733 regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]);
734 printk("$20: %08lx %08lx %08lx %08lx\n",
735 regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
736 printk("$24: %08lx %08lx\n",
737 regs->regs[24], regs->regs[25]);
738 printk("$28: %08lx %08lx %08lx %08lx\n",
739 regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
740
741 /* Saved cp0 registers. */
742 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\n",
743 regs->cp0_epc, regs->cp0_status, regs->cp0_cause);
744 }
745
746 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
747 unsigned long entryhi, unsigned long pagemask)
748 {
749 unsigned long flags;
750 unsigned long wired;
751 unsigned long old_pagemask;
752 unsigned long old_ctx;
753
754 __save_and_cli(flags);
755 /* Save old context and create impossible VPN2 value */
756 old_ctx = (get_entryhi() & 0xff);
757 old_pagemask = get_pagemask();
758 wired = get_wired();
759 set_wired (wired + 1);
760 set_index (wired);
761 BARRIER;
762 set_pagemask (pagemask);
763 set_entryhi(entryhi);
764 set_entrylo0(entrylo0);
765 set_entrylo1(entrylo1);
766 BARRIER;
767 tlb_write_indexed();
768 BARRIER;
769
770 set_entryhi(old_ctx);
771 BARRIER;
772 set_pagemask (old_pagemask);
773 flush_tlb_all();
774 __restore_flags(flags);
775 }
776
777 /* Detect and size the various caches. */
778 static void __init probe_icache(unsigned long config)
779 {
780 unsigned long config1;
781 unsigned int lsize;
782
783 if (!(config & (1 << 31))) {
784 /*
785 * Not a MIPS32 complainant CPU.
786 * Config 1 register not supported, we assume R4k style.
787 */
788 icache_size = 1 << (12 + ((config >> 9) & 7));
789 ic_lsize = 16 << ((config >> 5) & 1);
790 mips_cpu.icache.linesz = ic_lsize;
791
792 /*
793 * We cannot infer associativity - assume direct map
794 * unless probe template indicates otherwise
795 */
796 if(!mips_cpu.icache.ways) mips_cpu.icache.ways = 1;
797 mips_cpu.icache.sets =
798 (icache_size / ic_lsize) / mips_cpu.icache.ways;
799 } else {
800 config1 = read_mips32_cp0_config1();
801
802 if ((lsize = ((config1 >> 19) & 7)))
803 mips_cpu.icache.linesz = 2 << lsize;
804 else
805 mips_cpu.icache.linesz = lsize;
806 mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7);
807 mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7);
808
809 ic_lsize = mips_cpu.icache.linesz;
810 icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways *
811 ic_lsize;
812 }
813 printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",
814 icache_size >> 10, ic_lsize, mips_cpu.icache.ways);
815 }
816
817 static void __init probe_dcache(unsigned long config)
818 {
819 unsigned long config1;
820 unsigned int lsize;
821
822 if (!(config & (1 << 31))) {
823 /*
824 * Not a MIPS32 complainant CPU.
825 * Config 1 register not supported, we assume R4k style.
826 */
827 dcache_size = 1 << (12 + ((config >> 6) & 7));
828 dc_lsize = 16 << ((config >> 4) & 1);
829 mips_cpu.dcache.linesz = dc_lsize;
830 /*
831 * We cannot infer associativity - assume direct map
832 * unless probe template indicates otherwise
833 */
834 if(!mips_cpu.dcache.ways) mips_cpu.dcache.ways = 1;
835 mips_cpu.dcache.sets =
836 (dcache_size / dc_lsize) / mips_cpu.dcache.ways;
837 } else {
838 config1 = read_mips32_cp0_config1();
839
840 if ((lsize = ((config1 >> 10) & 7)))
841 mips_cpu.dcache.linesz = 2 << lsize;
842 else
843 mips_cpu.dcache.linesz= lsize;
844 mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7);
845 mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7);
846
847 dc_lsize = mips_cpu.dcache.linesz;
848 dcache_size =
849 mips_cpu.dcache.sets * mips_cpu.dcache.ways
850 * dc_lsize;
851 }
852 printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n",
853 dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways);
854 }
855
856
857 /* If you even _breathe_ on this function, look at the gcc output
858 * and make sure it does not pop things on and off the stack for
859 * the cache sizing loop that executes in KSEG1 space or else
860 * you will crash and burn badly. You have been warned.
861 */
862 static int __init probe_scache(unsigned long config)
863 {
864 extern unsigned long stext;
865 unsigned long flags, addr, begin, end, pow2;
866 int tmp;
867
868 if (mips_cpu.scache.flags == MIPS_CACHE_NOT_PRESENT)
869 return 0;
870
871 tmp = ((config >> 17) & 1);
872 if(tmp)
873 return 0;
874 tmp = ((config >> 22) & 3);
875 switch(tmp) {
876 case 0:
877 sc_lsize = 16;
878 break;
879 case 1:
880 sc_lsize = 32;
881 break;
882 case 2:
883 sc_lsize = 64;
884 break;
885 case 3:
886 sc_lsize = 128;
887 break;
888 }
889
890 begin = (unsigned long) &stext;
891 begin &= ~((4 * 1024 * 1024) - 1);
892 end = begin + (4 * 1024 * 1024);
893
894 /* This is such a bitch, you'd think they would make it
895 * easy to do this. Away you daemons of stupidity!
896 */
897 __save_and_cli(flags);
898
899 /* Fill each size-multiple cache line with a valid tag. */
900 pow2 = (64 * 1024);
901 for(addr = begin; addr < end; addr = (begin + pow2)) {
902 unsigned long *p = (unsigned long *) addr;
903 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
904 pow2 <<= 1;
905 }
906
907 /* Load first line with zero (therefore invalid) tag. */
908 set_taglo(0);
909 set_taghi(0);
910 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
911 __asm__ __volatile__("\n\t.set noreorder\n\t"
912 ".set mips3\n\t"
913 "cache 8, (%0)\n\t"
914 ".set mips0\n\t"
915 ".set reorder\n\t" : : "r" (begin));
916 __asm__ __volatile__("\n\t.set noreorder\n\t"
917 ".set mips3\n\t"
918 "cache 9, (%0)\n\t"
919 ".set mips0\n\t"
920 ".set reorder\n\t" : : "r" (begin));
921 __asm__ __volatile__("\n\t.set noreorder\n\t"
922 ".set mips3\n\t"
923 "cache 11, (%0)\n\t"
924 ".set mips0\n\t"
925 ".set reorder\n\t" : : "r" (begin));
926
927 /* Now search for the wrap around point. */
928 pow2 = (128 * 1024);
929 tmp = 0;
930 for(addr = (begin + (128 * 1024)); addr < (end); addr = (begin + pow2)) {
931 __asm__ __volatile__("\n\t.set noreorder\n\t"
932 ".set mips3\n\t"
933 "cache 7, (%0)\n\t"
934 ".set mips0\n\t"
935 ".set reorder\n\t" : : "r" (addr));
936 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
937 if(!get_taglo())
938 break;
939 pow2 <<= 1;
940 }
941 __restore_flags(flags);
942 addr -= begin;
943 printk("Secondary cache sized at %dK linesize %d bytes.\n",
944 (int) (addr >> 10), sc_lsize);
945 scache_size = addr;
946 return 1;
947 }
948
949 static void __init setup_noscache_funcs(void)
950 {
951 _clear_page = (void *)mips32_clear_page_dc;
952 _copy_page = (void *)mips32_copy_page_dc;
953 _flush_cache_all = mips32_flush_cache_all_pc;
954 ___flush_cache_all = mips32_flush_cache_all_pc;
955 _flush_cache_mm = mips32_flush_cache_mm_pc;
956 _flush_cache_range = mips32_flush_cache_range_pc;
957 _flush_cache_page = mips32_flush_cache_page_pc;
958 _flush_page_to_ram = mips32_flush_page_to_ram_pc;
959
960 _flush_icache_page = mips32_flush_icache_page;
961
962 _dma_cache_wback_inv = mips32_dma_cache_wback_inv_pc;
963 _dma_cache_wback = mips32_dma_cache_wback;
964 _dma_cache_inv = mips32_dma_cache_inv_pc;
965 }
966
967 static void __init setup_scache_funcs(void)
968 {
969 _flush_cache_all = mips32_flush_cache_all_sc;
970 ___flush_cache_all = mips32_flush_cache_all_sc;
971 _flush_cache_mm = mips32_flush_cache_mm_sc;
972 _flush_cache_range = mips32_flush_cache_range_sc;
973 _flush_cache_page = mips32_flush_cache_page_sc;
974 _flush_page_to_ram = mips32_flush_page_to_ram_sc;
975 _clear_page = (void *)mips32_clear_page_sc;
976 _copy_page = (void *)mips32_copy_page_sc;
977
978 _flush_icache_page = mips32_flush_icache_page_s;
979
980 _dma_cache_wback_inv = mips32_dma_cache_wback_inv_sc;
981 _dma_cache_wback = mips32_dma_cache_wback;
982 _dma_cache_inv = mips32_dma_cache_inv_sc;
983 }
984
985 typedef int (*probe_func_t)(unsigned long);
986
987 static inline void __init setup_scache(unsigned int config)
988 {
989 probe_func_t probe_scache_kseg1;
990 int sc_present = 0;
991
992 /* Maybe the cpu knows about a l2 cache? */
993 probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
994 sc_present = probe_scache_kseg1(config);
995
996 if (sc_present) {
997 mips_cpu.scache.linesz = sc_lsize;
998 /*
999 * We cannot infer associativity - assume direct map
1000 * unless probe template indicates otherwise
1001 */
1002 if(!mips_cpu.scache.ways) mips_cpu.scache.ways = 1;
1003 mips_cpu.scache.sets =
1004 (scache_size / sc_lsize) / mips_cpu.scache.ways;
1005
1006 setup_scache_funcs();
1007 return;
1008 }
1009
1010 setup_noscache_funcs();
1011 }
1012
1013 static void __init probe_tlb(unsigned long config)
1014 {
1015 unsigned long config1;
1016
1017 if (!(config & (1 << 31))) {
1018 /*
1019 * Not a MIPS32 complainant CPU.
1020 * Config 1 register not supported, we assume R4k style.
1021 */
1022 mips_cpu.tlbsize = 48;
1023 } else {
1024 config1 = read_mips32_cp0_config1();
1025 if (!((config >> 7) & 3))
1026 panic("No MMU present");
1027 else
1028 mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;
1029 }
1030
1031 printk("Number of TLB entries %d.\n", mips_cpu.tlbsize);
1032 }
1033
1034 void __init ld_mmu_mips32(void)
1035 {
1036 unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
1037
1038 printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
1039
1040 #ifdef CONFIG_MIPS_UNCACHED
1041 change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
1042 #else
1043 change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
1044 #endif
1045
1046 probe_icache(config);
1047 probe_dcache(config);
1048 setup_scache(config);
1049 probe_tlb(config);
1050
1051 _flush_cache_sigtramp = mips32_flush_cache_sigtramp;
1052 _flush_icache_range = mips32_flush_icache_range; /* Ouch */
1053
1054 __flush_cache_all();
1055 write_32bit_cp0_register(CP0_WIRED, 0);
1056
1057 /*
1058 * You should never change this register:
1059 * - The entire mm handling assumes the c0_pagemask register to
1060 * be set for 4kb pages.
1061 */
1062 write_32bit_cp0_register(CP0_PAGEMASK, PM_4K);
1063 flush_tlb_all();
1064 }
1065