Macro Cross Reference Report
R
Declared as: 0x0020
Define [constants.c, 166] constants.c
Use [constants.c, 191] constants.c
Use [constants.c, 199] constants.c
Use [constants.c, 205] constants.c
Use [constants.c, 206] constants.c
Use [constants.c, 207] constants.c
Use [constants.c, 208] constants.c
Use [constants.c, 209] constants.c
Use [constants.c, 210] constants.c
Use [constants.c, 211] constants.c
Use [constants.c, 212] constants.c
Use [constants.c, 214] constants.c
Use [constants.c, 218] constants.c
Use [constants.c, 219] constants.c
Use [constants.c, 220] constants.c
Use [constants.c, 221] constants.c
Use [constants.c, 222] constants.c
Use [constants.c, 225] constants.c
Use [constants.c, 226] constants.c
Use [constants.c, 227] constants.c
Use [constants.c, 228] constants.c
Use [constants.c, 229] constants.c
Use [constants.c, 230] constants.c
Use [constants.c, 231] constants.c
Use [constants.c, 232] constants.c
Use [constants.c, 233] constants.c
Use [constants.c, 234] constants.c
Use [constants.c, 235] constants.c
Use [constants.c, 236] constants.c
Use [constants.c, 237] constants.c
Use [constants.c, 238] constants.c
Use [constants.c, 239] constants.c
Use [constants.c, 240] constants.c
Use [constants.c, 241] constants.c
Use [constants.c, 242] constants.c
Use [constants.c, 243] constants.c
Use [constants.c, 244] constants.c
Use [constants.c, 245] constants.c
Use [constants.c, 252] constants.c
Use [constants.c, 253] constants.c
Use [constants.c, 254] constants.c
Use [constants.c, 255] constants.c
Use [constants.c, 257] constants.c
Use [constants.c, 258] constants.c
Use [constants.c, 259] constants.c
Use [constants.c, 262] constants.c
Use [constants.c, 263] constants.c
Use [constants.c, 270] constants.c
Use [constants.c, 271] constants.c
Use [constants.c, 272] constants.c
Use [constants.c, 273] constants.c
Use [constants.c, 274] constants.c
Use [constants.c, 277] constants.c
Use [constants.c, 278] constants.c
Use [constants.c, 284] constants.c
Use [constants.c, 285] constants.c
Use [constants.c, 286] constants.c
Use [constants.c, 292] constants.c
Use [constants.c, 293] constants.c
Use [constants.c, 294] constants.c
Use [constants.c, 295] constants.c
Use [constants.c, 296] constants.c
Use [constants.c, 297] constants.c
Use [constants.c, 299] constants.c
Use [constants.c, 300] constants.c
Use [constants.c, 301] constants.c
Use [constants.c, 302] constants.c
Use [constants.c, 303] constants.c
Use [constants.c, 304] constants.c
Use [constants.c, 305] constants.c
Use [constants.c, 306] constants.c
Use [constants.c, 307] constants.c
Use [constants.c, 308] constants.c
Use [constants.c, 314] constants.c
Use [constants.c, 315] constants.c
Use [constants.c, 319] constants.c
Use [constants.c, 322] constants.c
Use [constants.c, 323] constants.c
Use [constants.c, 324] constants.c
Use [constants.c, 326] constants.c
Use [constants.c, 327] constants.c
Use [constants.c, 328] constants.c
Use [constants.c, 329] constants.c
Use [constants.c, 330] constants.c
Use [constants.c, 331] constants.c
Use [constants.c, 332] constants.c
Use [constants.c, 333] constants.c
Use [constants.c, 334] constants.c
Use [constants.c, 335] constants.c
Use [constants.c, 336] constants.c
Use [constants.c, 337] constants.c
Use [constants.c, 338] constants.c
Use [constants.c, 339] constants.c
Use [constants.c, 340] constants.c
Use [constants.c, 341] constants.c
Use [constants.c, 342] constants.c
Use [constants.c, 343] constants.c
Use [constants.c, 344] constants.c
Use [constants.c, 345] constants.c
Use [constants.c, 346] constants.c
Use [constants.c, 347] constants.c
Use [constants.c, 348] constants.c
Use [constants.c, 349] constants.c
Use [constants.c, 350] constants.c
Use [constants.c, 351] constants.c
Use [constants.c, 352] constants.c
Use [constants.c, 353] constants.c
Use [constants.c, 354] constants.c
Use [constants.c, 355] constants.c
Use [constants.c, 356] constants.c
Use [constants.c, 357] constants.c
Use [constants.c, 358] constants.c
Use [constants.c, 359] constants.c
Use [constants.c, 360] constants.c
Use [constants.c, 361] constants.c
Use [constants.c, 362] constants.c
Use [constants.c, 363] constants.c
Use [constants.c, 364] constants.c
Use [constants.c, 365] constants.c
Use [constants.c, 368] constants.c
Use [constants.c, 369] constants.c
Use [constants.c, 372] constants.c
Use [constants.c, 373] constants.c
Use [constants.c, 374] constants.c
Use [constants.c, 375] constants.c
Use [constants.c, 376] constants.c
Use [constants.c, 377] constants.c
Use [constants.c, 378] constants.c
Use [constants.c, 379] constants.c
Use [constants.c, 380] constants.c
Use [constants.c, 381] constants.c
Use [constants.c, 382] constants.c
Use [constants.c, 383] constants.c
Use [constants.c, 384] constants.c
Use [constants.c, 388] constants.c
Use [constants.c, 389] constants.c
Use [constants.c, 390] constants.c
Use [constants.c, 391] constants.c
Use [constants.c, 392] constants.c
Use [constants.c, 393] constants.c
Use [constants.c, 395] constants.c
Use [constants.c, 400] constants.c
Use [constants.c, 401] constants.c
Use [constants.c, 402] constants.c
Use [constants.c, 403] constants.c
Use [constants.c, 404] constants.c
Use [constants.c, 405] constants.c
Use [constants.c, 419] constants.c
Use [constants.c, 420] constants.c
Use [constants.c, 421] constants.c
Use [constants.c, 422] constants.c
Use [constants.c, 423] constants.c
Use [constants.c, 424] constants.c
Use [constants.c, 425] constants.c
Use [constants.c, 426] constants.c
Use [constants.c, 427] constants.c
Use [constants.c, 428] constants.c
Use [constants.c, 429] constants.c
Use [constants.c, 430] constants.c
Use [constants.c, 431] constants.c
Use [constants.c, 432] constants.c
Use [constants.c, 433] constants.c
Use [constants.c, 434] constants.c
Use [constants.c, 435] constants.c
Use [constants.c, 436] constants.c
Use [constants.c, 437] constants.c
Use [constants.c, 438] constants.c
Use [constants.c, 439] constants.c
Use [constants.c, 440] constants.c
Use [constants.c, 441] constants.c
Use [constants.c, 442] constants.c
Use [constants.c, 443] constants.c
Use [constants.c, 444] constants.c
Use [constants.c, 445] constants.c
Use [constants.c, 446] constants.c
Use [constants.c, 447] constants.c
Use [constants.c, 448] constants.c
Use [constants.c, 449] constants.c
Use [constants.c, 450] constants.c
Use [constants.c, 455] constants.c
Use [constants.c, 458] constants.c
Use [constants.c, 459] constants.c
Use [constants.c, 460] constants.c
Use [constants.c, 461] constants.c
Use [constants.c, 462] constants.c
Use [constants.c, 463] constants.c
Use [constants.c, 464] constants.c
Use [constants.c, 465] constants.c
Use [constants.c, 466] constants.c
Use [constants.c, 467] constants.c
Use [constants.c, 468] constants.c
Use [constants.c, 469] constants.c
Use [constants.c, 470] constants.c
Use [constants.c, 471] constants.c
Use [constants.c, 475] constants.c
Use [constants.c, 476] constants.c
Use [constants.c, 480] constants.c
Use [constants.c, 482] constants.c
Use [constants.c, 484] constants.c
Use [constants.c, 488] constants.c
Use [constants.c, 489] constants.c
Use [constants.c, 490] constants.c
Use [constants.c, 491] constants.c
Use [constants.c, 494] constants.c
Use [constants.c, 495] constants.c
Use [constants.c, 496] constants.c
Use [constants.c, 497] constants.c
Use [constants.c, 498] constants.c
Use [constants.c, 499] constants.c
Use [constants.c, 500] constants.c
Use [constants.c, 501] constants.c
Use [constants.c, 505] constants.c
Use [constants.c, 506] constants.c
Use [constants.c, 507] constants.c
Use [constants.c, 586] constants.c
Use [constants.c, 587] constants.c
Use [constants.c, 588] constants.c
Use [constants.c, 589] constants.c
Use [constants.c, 590] constants.c
Use [constants.c, 591] constants.c
Use [constants.c, 602] constants.c
Use [constants.c, 603] constants.c
Use [constants.c, 604] constants.c
Use [constants.c, 605] constants.c
Use [constants.c, 606] constants.c
Use [constants.c, 632] constants.c
Use [constants.c, 633] constants.c
Use [constants.c, 634] constants.c
Use [constants.c, 635] constants.c
Use [constants.c, 636] constants.c
Use [constants.c, 637] constants.c
Use [constants.c, 643] constants.c
Use [constants.c, 644] constants.c
Use [constants.c, 645] constants.c
Use [constants.c, 646] constants.c
Use [constants.c, 647] constants.c
Use [constants.c, 648] constants.c
Use [constants.c, 649] constants.c
Use [constants.c, 650] constants.c
Use [constants.c, 651] constants.c
Use [constants.c, 652] constants.c
Use [constants.c, 653] constants.c
Use [constants.c, 654] constants.c
Use [constants.c, 655] constants.c
R
Declared as: ((size_t) &((struct pt_regs *)0)->x)
Define [traps.c, 667] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 670] traps.c
Use [traps.c, 673] traps.c
Use [traps.c, 673] traps.c
Use [traps.c, 673] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 674] traps.c
Use [traps.c, 675] traps.c
Use [traps.c, 675] traps.c
Use [traps.c, 675] traps.c
Use [traps.c, 679] traps.c
R0
Declared as: 0
Define [macserial.h, 221] macserial.h
R0
Declared as: 0
Define [zs.h, 188] zs.h
Use [zs.c, 407] receive_chars
Use [zs.c, 440] receive_chars
Use [zs.c, 482] transmit_chars
Use [zs.c, 496] transmit_chars
Use [zs.c, 514] status_handle
Use [zs.c, 551] status_handle
R0
Declared as: if (read_sx_byte (board, i) != 0x55) return 1
Define [sx.c, 1581] sx.c
Use [sx.c, 1596] do_memtest
Use [sx.c, 1596] do_memtest
Use [sx.c, 1599] do_memtest
Use [sx.c, 1609] sx.c
R0
Declared as: if (read_sx_word (board, i) != 0x55aa) return 1
Define [sx.c, 1616] sx.c
r0
Declared as: (in_p(0) & 0xff)
Define [paride.h, 104] paride.h
Use [aten.c, 62] aten_read_regr
Use [aten.c, 89] aten_read_block
Use [aten.c, 89] aten_read_block
Use [aten.c, 111] aten_connect
Use [bpck.c, 63] bpck_read_regr
Use [bpck.c, 166] bpck_read_block
Use [bpck.c, 204] bpck_probe_unit
Use [bpck.c, 220] bpck_connect
Use [bpck.c, 263] bpck_force_spp
Use [bpck.c, 300] bpck_test_proto
Use [bpck.c, 403] bpck_test_port
Use [bpck.c, 403] bpck_test_port
Use [bpck.c, 408] bpck_test_port
Use [bpck.c, 408] bpck_test_port
Use [bpck.c, 411] bpck_test_port
Use [comm.c, 57] comm_read_regr
Use [comm.c, 91] comm_connect
Use [comm.c, 123] comm_read_block
Use [dstr.c, 61] dstr_read_regr
Use [dstr.c, 102] dstr_connect
Use [dstr.c, 133] dstr_read_block
Use [epat.c, 77] epat_read_regr
Use [epat.c, 124] epat_read_block
Use [epat.c, 127] epat_read_block
Use [epat.c, 207] epat_connect
Use [epia.c, 69] epia_read_regr
Use [epia.c, 114] epia_connect
Use [epia.c, 168] epia_read_block
Use [fit2.c, 104] fit2_connect
Use [fit3.c, 79] fit3_read_regr
Use [fit3.c, 115] fit3_read_block
Use [fit3.c, 116] fit3_read_block
Use [fit3.c, 156] fit3_connect
Use [friq.c, 96] friq_read_block_int
Use [friq.c, 170] friq_connect
Use [friq.c, 187] friq_test_proto
Use [frpw.c, 93] frpw_read_block_int
Use [frpw.c, 174] frpw_connect
Use [frpw.c, 204] frpw_test_pnp
Use [kbic.c, 61] kbic_read_regr
Use [kbic.c, 100] k951_connect
Use [kbic.c, 116] k971_connect
Use [kbic.c, 166] kbic_read_block
Use [kbic.c, 167] kbic_read_block
Use [ktti.c, 80] ktti_connect
Use [on20.c, 50] on20_read_regr
Use [on20.c, 71] on20_connect
Use [on20.c, 94] on20_read_block
Use [on26.c, 61] on26_read_regr
Use [on26.c, 105] on26_connect
Use [on26.c, 130] on26_test_port
Use [on26.c, 204] on26_read_block
Use [on26.c, 205] on26_read_block
R0
Declared as: 0
Define [zs.h, 185] zs.h
Use [zs.c, 317] load_zsregs
Use [zs.c, 318] load_zsregs
Use [zs.c, 1822] block_til_ready
Use [zs.c, 2506] zs_init
Use [zs.c, 2541] zs_init
Use [zs.c, 2543] zs_init
Use [zs.c, 2584] zs_init
Use [zs.c, 2586] zs_init
Use [zs.c, 2638] zs_init
Use [zs.c, 2640] zs_init
R0
Declared as: 0
Define [z85230.h, 24] z85230.h
Use [z85230.c, 345] z8530_rx
Use [z85230.c, 413] z8530_tx
Use [z85230.c, 454] z8530_status
Use [z85230.c, 569] z8530_dma_status
Use [z85230.c, 681] z8530_status_clear
Use [z85230.c, 826] z8530_sync_close
Use [z85230.c, 1011] z8530_sync_dma_close
Use [z85230.c, 1167] z8530_sync_txdma_close
Use [z85230.c, 1266] z8530_init
Use [z85230.c, 1344] z8530_channel_load
Use [z85230.c, 1440] z8530_tx_begin
Use [z85230.c, 1557] z8530_rx_done
R0
Declared as: 0
Define [z8530.h, 6] z8530.h
Use [dmascc.c, 502] setup_adapter
Use [dmascc.c, 524] setup_adapter
Use [dmascc.c, 542] setup_adapter
Use [dmascc.c, 838] scc_open
Use [dmascc.c, 1002] z8530_isr
Use [dmascc.c, 1017] rx_isr
Use [dmascc.c, 1022] rx_isr
Use [dmascc.c, 1046] special_condition
Use [dmascc.c, 1145] tx_isr
Use [dmascc.c, 1150] tx_isr
Use [dmascc.c, 1156] tx_isr
Use [dmascc.c, 1167] es_isr
Use [dmascc.c, 1168] es_isr
Use [dmascc.c, 1196] es_isr
Use [dmascc.c, 1197] es_isr
Use [dmascc.c, 1263] tm_isr
Use [dmascc.c, 1288] tm_isr
Use [dmascc.c, 1336] tx_on
Use [dmascc.c, 1344] rx_on
Use [dmascc.c, 1369] rx_on
Use [scc.c, 402] scc_txint
Use [scc.c, 439] scc_exint
Use [scc.c, 652] scc_isr
Use [scc.c, 701] scc_isr
Use [scc.c, 861] init_channel
Use [scc.c, 876] init_channel
Use [scc.c, 1262] t_maxkeyup
r0
Declared as: 0
Define [ppc_asm.tmpl, 15] ppc_asm.tmpl
R0
Declared as: 0
Define [sgiserial.h, 192] sgiserial.h
R0_OFF
Declared as: 0x0
Define [nmi.h, 85] nmi.h
R1
Declared as: 1
Define [macserial.h, 222] macserial.h
Use [macserial.c, 271] load_zsregs
Use [macserial.c, 271] load_zsregs
Use [macserial.c, 401] receive_chars
Use [macserial.c, 550] receive_special_dma
Use [macserial.c, 2637] macserial_init
Use [macserial.c, 2769] serial_console_write
Use [macserial.c, 2789] serial_console_write
Use [macserial.c, 2802] serial_console_wait_key
Use [macserial.c, 2811] serial_console_wait_key
R1
Declared as: 1
Define [zs.h, 189] zs.h
Use [zs.c, 322] load_zsregs
Use [zs.c, 322] load_zsregs
Use [zs.c, 409] receive_chars
R1
Declared as: if (read_sx_byte (board, i) != 0xaa) return 1
Define [sx.c, 1582] sx.c
Use [sx.c, 1596] do_memtest
Use [sx.c, 1597] do_memtest
Use [sx.c, 1598] do_memtest
Use [sx.c, 1610] sx.c
R1
Declared as: if (read_sx_word (board, i) != 0xaa55) return 1
Define [sx.c, 1617] sx.c
r1
Declared as: (in_p(1) & 0xff)
Define [paride.h, 106] paride.h
Use [aten.c, 56] aten_read_regr
Use [aten.c, 56] aten_read_regr
Use [aten.c, 78] aten_read_block
Use [aten.c, 78] aten_read_block
Use [aten.c, 79] aten_read_block
Use [aten.c, 79] aten_read_block
Use [bpck.c, 56] bpck_read_regr
Use [bpck.c, 58] bpck_read_regr
Use [bpck.c, 157] bpck_read_block
Use [bpck.c, 158] bpck_read_block
Use [bpck.c, 203] bpck_probe_unit
Use [bpck.c, 207] bpck_probe_unit
Use [bpck.c, 209] bpck_probe_unit
Use [bpck.c, 290] bpck_test_proto
Use [bpck.c, 291] bpck_test_proto
Use [comm.c, 53] comm_read_regr
Use [comm.c, 53] comm_read_regr
Use [comm.c, 62] comm_read_regr
Use [comm.c, 84] comm_write_regr
Use [comm.c, 115] comm_read_block
Use [comm.c, 116] comm_read_block
Use [comm.c, 128] comm_read_block
Use [comm.c, 133] comm_read_block
Use [comm.c, 138] comm_read_block
Use [comm.c, 162] comm_write_block
Use [comm.c, 166] comm_write_block
Use [comm.c, 170] comm_write_block
Use [dstr.c, 58] dstr_read_regr
Use [dstr.c, 58] dstr_read_regr
Use [dstr.c, 125] dstr_read_block
Use [dstr.c, 126] dstr_read_block
Use [epat.c, 69] epat_read_regr
Use [epat.c, 69] epat_read_regr
Use [epat.c, 73] epat_read_regr
Use [epat.c, 99] epat_read_block
Use [epat.c, 101] epat_read_block
Use [epat.c, 113] epat_read_block
Use [epia.c, 58] epia_read_regr
Use [epia.c, 58] epia_read_regr
Use [epia.c, 64] epia_read_regr
Use [epia.c, 144] epia_read_block
Use [epia.c, 145] epia_read_block
Use [epia.c, 157] epia_read_block
Use [fit2.c, 55] fit2_read_regr
Use [fit2.c, 56] fit2_read_regr
Use [fit2.c, 72] fit2_read_block
Use [fit2.c, 72] fit2_read_block
Use [fit2.c, 73] fit2_read_block
Use [fit2.c, 73] fit2_read_block
Use [fit2.c, 78] fit2_read_block
Use [fit2.c, 78] fit2_read_block
Use [fit2.c, 79] fit2_read_block
Use [fit2.c, 79] fit2_read_block
Use [fit3.c, 73] fit3_read_regr
Use [fit3.c, 74] fit3_read_regr
Use [fit3.c, 102] fit3_read_block
Use [fit3.c, 103] fit3_read_block
Use [fit3.c, 104] fit3_read_block
Use [fit3.c, 105] fit3_read_block
Use [friq.c, 57] friq_read_regr
Use [friq.c, 58] friq_read_regr
Use [friq.c, 84] friq_read_block_int
Use [friq.c, 85] friq_read_block_int
Use [frpw.c, 54] frpw_read_regr
Use [frpw.c, 55] frpw_read_regr
Use [frpw.c, 81] frpw_read_block_int
Use [frpw.c, 82] frpw_read_block_int
Use [frpw.c, 208] frpw_test_pnp
Use [frpw.c, 208] frpw_test_pnp
Use [kbic.c, 53] kbic_read_regr
Use [kbic.c, 53] kbic_read_regr
Use [kbic.c, 141] kbic_read_block
Use [kbic.c, 142] kbic_read_block
Use [kbic.c, 144] kbic_read_block
Use [kbic.c, 145] kbic_read_block
Use [ktti.c, 48] ktti_read_regr
Use [ktti.c, 48] ktti_read_regr
Use [ktti.c, 59] ktti_read_block
Use [ktti.c, 59] ktti_read_block
Use [ktti.c, 61] ktti_read_block
Use [ktti.c, 61] ktti_read_block
Use [on20.c, 45] on20_read_regr
Use [on20.c, 46] on20_read_regr
Use [on20.c, 96] on20_read_block
Use [on20.c, 97] on20_read_block
Use [on26.c, 55] on26_read_regr
Use [on26.c, 56] on26_read_regr
Use [on26.c, 143] on26_test_port
Use [on26.c, 144] on26_test_port
Use [on26.c, 146] on26_test_port
Use [on26.c, 194] on26_read_block
Use [on26.c, 195] on26_read_block
R1
Declared as: 1
Define [zs.h, 186] zs.h
Use [zs.c, 286] load_zsregs
Use [zs.c, 319] load_zsregs
Use [zs.c, 319] load_zsregs
Use [zs.c, 370] kgdb_chaninit
Use [zs.c, 373] kgdb_chaninit
Use [zs.c, 570] receive_chars
Use [zs.c, 662] special_receive
Use [zs.c, 2546] zs_init
Use [zs.c, 2589] zs_init
Use [zs.c, 2719] zs_console_putchar
R1
Declared as: 1
Define [z85230.h, 25] z85230.h
Use [z85230.c, 283] z8530_flush_fifo
Use [z85230.c, 284] z8530_flush_fifo
Use [z85230.c, 285] z8530_flush_fifo
Use [z85230.c, 286] z8530_flush_fifo
Use [z85230.c, 289] z8530_flush_fifo
Use [z85230.c, 290] z8530_flush_fifo
Use [z85230.c, 291] z8530_flush_fifo
Use [z85230.c, 292] z8530_flush_fifo
Use [z85230.c, 348] z8530_rx
Use [z85230.c, 519] z8530_dma_rx
Use [z85230.c, 644] z8530_rx_clear
Use [z85230.c, 800] z8530_sync_open
Use [z85230.c, 801] z8530_sync_open
Use [z85230.c, 801] z8530_sync_open
Use [z85230.c, 898] z8530_sync_dma_open
Use [z85230.c, 899] z8530_sync_dma_open
Use [z85230.c, 899] z8530_sync_dma_open
Use [z85230.c, 905] z8530_sync_dma_open
Use [z85230.c, 906] z8530_sync_dma_open
Use [z85230.c, 907] z8530_sync_dma_open
Use [z85230.c, 908] z8530_sync_dma_open
Use [z85230.c, 909] z8530_sync_dma_open
Use [z85230.c, 909] z8530_sync_dma_open
Use [z85230.c, 910] z8530_sync_dma_open
Use [z85230.c, 911] z8530_sync_dma_open
Use [z85230.c, 911] z8530_sync_dma_open
Use [z85230.c, 993] z8530_sync_dma_close
Use [z85230.c, 994] z8530_sync_dma_close
Use [z85230.c, 994] z8530_sync_dma_close
Use [z85230.c, 995] z8530_sync_dma_close
Use [z85230.c, 996] z8530_sync_dma_close
Use [z85230.c, 997] z8530_sync_dma_close
Use [z85230.c, 997] z8530_sync_dma_close
Use [z85230.c, 1084] z8530_sync_txdma_open
Use [z85230.c, 1085] z8530_sync_txdma_open
Use [z85230.c, 1085] z8530_sync_txdma_open
Use [z85230.c, 1154] z8530_sync_txdma_close
Use [z85230.c, 1155] z8530_sync_txdma_close
Use [z85230.c, 1155] z8530_sync_txdma_close
Use [z85230.c, 1156] z8530_sync_txdma_close
Use [z85230.c, 1157] z8530_sync_txdma_close
Use [z85230.c, 1158] z8530_sync_txdma_close
Use [z85230.c, 1158] z8530_sync_txdma_close
R1
Declared as: 1
Define [z8530.h, 7] z8530.h
Use [dmascc.c, 525] setup_adapter
Use [dmascc.c, 540] setup_adapter
Use [dmascc.c, 748] scc_open
Use [dmascc.c, 1016] rx_isr
Use [dmascc.c, 1023] rx_isr
Use [dmascc.c, 1190] es_isr
Use [dmascc.c, 1322] tx_on
Use [dmascc.c, 1332] tx_on
Use [dmascc.c, 1360] rx_on
Use [dmascc.c, 1366] rx_on
Use [dmascc.c, 1381] rx_off
Use [scc.c, 573] scc_spint
Use [scc.c, 798] init_channel
Use [scc.c, 874] init_channel
Use [scc.c, 912] scc_key_trx
Use [scc.c, 1260] t_maxkeyup
Use [scc.c, 1634] scc_net_close
r1
Declared as: 1
Define [ppc_asm.tmpl, 16] ppc_asm.tmpl
R1
Declared as: 1
Define [sgiserial.h, 193] sgiserial.h
Use [sgiserial.c, 225] load_zsregs
Use [sgiserial.c, 225] load_zsregs
Use [sgiserial.c, 257] kgdb_chaninit
Use [sgiserial.c, 260] kgdb_chaninit
Use [sgiserial.c, 414] receive_chars
Use [sgiserial.c, 1954] rs_init
Use [sgiserial.c, 1978] rs_init
R10
Declared as: 10
Define [macserial.h, 231] macserial.h
Use [macserial.c, 268] load_zsregs
Use [macserial.c, 268] load_zsregs
R10
Declared as: 10
Define [zs.h, 198] zs.h
Use [zs.c, 324] load_zsregs
Use [zs.c, 324] load_zsregs
R10
Declared as: 10
Define [zs.h, 195] zs.h
Use [zs.c, 307] load_zsregs
Use [zs.c, 307] load_zsregs
Use [zs.c, 2519] zs_init
Use [zs.c, 2562] zs_init
Use [zs.c, 2621] zs_init
R10
Declared as: 10
Define [z85230.h, 34] z85230.h
Use [z85230.c, 425] z8530_tx
Use [z85230.c, 1422] z8530_tx_begin
Use [z85230.c, 1436] z8530_tx_begin
R10
Declared as: 10
Define [z8530.h, 16] z8530.h
Use [dmascc.c, 797] scc_open
Use [scc.c, 404] scc_txint
Use [scc.c, 418] scc_txint
Use [scc.c, 508] scc_exint
Use [scc.c, 804] init_channel
r10
Declared as: 10
Define [ppc_asm.tmpl, 25] ppc_asm.tmpl
R10
Declared as: 10
Define [sgiserial.h, 202] sgiserial.h
Use [sgiserial.c, 222] load_zsregs
Use [sgiserial.c, 222] load_zsregs
Use [sgiserial.c, 1957] rs_init
Use [sgiserial.c, 1982] rs_init
R10_OFF
Declared as: 0x50
Define [nmi.h, 95] nmi.h
R11
Declared as: 11
Define [macserial.h, 232] macserial.h
Use [macserial.c, 273] load_zsregs
Use [macserial.c, 273] load_zsregs
Use [macserial.c, 300] get_zsbaud
R11
Declared as: 11
Define [zs.h, 199] zs.h
Use [zs.c, 325] load_zsregs
Use [zs.c, 325] load_zsregs
R11
Declared as: 11
Define [zs.h, 196] zs.h
Use [zs.c, 308] load_zsregs
Use [zs.c, 308] load_zsregs
Use [zs.c, 2520] zs_init
Use [zs.c, 2563] zs_init
Use [zs.c, 2622] zs_init
R11
Declared as: 11
Define [z85230.h, 35] z85230.h
R11
Declared as: 11
Define [z8530.h, 17] z8530.h
Use [dmascc.c, 821] scc_open
Use [scc.c, 837] init_channel
Use [scc.c, 842] init_channel
Use [scc.c, 847] init_channel
Use [scc.c, 927] scc_key_trx
Use [scc.c, 943] scc_key_trx
r11
Declared as: 11
Define [ppc_asm.tmpl, 26] ppc_asm.tmpl
R11
Declared as: 11
Define [sgiserial.h, 203] sgiserial.h
Use [sgiserial.c, 227] load_zsregs
Use [sgiserial.c, 227] load_zsregs
R11_OFF
Declared as: 0x58
Define [nmi.h, 96] nmi.h
R12
Declared as: 12
Define [macserial.h, 233] macserial.h
Use [macserial.c, 274] load_zsregs
Use [macserial.c, 274] load_zsregs
R12
Declared as: 12
Define [zs.h, 200] zs.h
Use [zs.c, 326] load_zsregs
Use [zs.c, 326] load_zsregs
R12
Declared as: 12
Define [zs.h, 197] zs.h
Use [zs.c, 309] load_zsregs
Use [zs.c, 309] load_zsregs
Use [zs.c, 377] kgdb_chaninit
Use [zs.c, 2224] zs_change_mouse_baud
Use [zs.c, 2525] zs_init
Use [zs.c, 2569] zs_init
Use [zs.c, 2627] zs_init
R12
Declared as: 12
Define [z85230.h, 36] z85230.h
Use [z85230.c, 1241] z8530_init
Use [z85230.c, 1242] z8530_init
Use [z85230.c, 1244] z8530_init
Use [z85230.c, 1245] z8530_init
R12
Declared as: 12
Define [z8530.h, 18] z8530.h
Use [dmascc.c, 802] scc_open
Use [scc.c, 720] set_brg
r12
Declared as: 12
Define [ppc_asm.tmpl, 27] ppc_asm.tmpl
R12
Declared as: 12
Define [sgiserial.h, 204] sgiserial.h
Use [sgiserial.c, 228] load_zsregs
Use [sgiserial.c, 228] load_zsregs
Use [sgiserial.c, 264] kgdb_chaninit
R128_3D_RNDR_GEN_INDX_PRIM
Declared as: 0x00002300
Define [r128_drv.h, 334] r128_drv.h
R128_ADDR
Declared as: (R128_BASE( reg ) + reg)
Define [r128_drv.h, 385] r128_drv.h
Macro [r128_drv.h, 387] r128_drv.h
Macro [r128_drv.h, 408] r128_drv.h
Macro [r128_cce.c, 92] R128_READ_PLL
Macro [r128_cce.c, 93] R128_READ_PLL
Macro [r128_cce.c, 124] r128_do_pixcache_flush
Macro [r128_cce.c, 125] r128_do_pixcache_flush
Macro [r128_cce.c, 128] r128_do_pixcache_flush
Macro [r128_cce.c, 145] r128_do_wait_for_fifo
Macro [r128_cce.c, 164] r128_do_wait_for_idle
Macro [r128_cce.c, 191] r128_cce_load_microcode
Macro [r128_cce.c, 193] r128_cce_load_microcode
Macro [r128_cce.c, 195] r128_cce_load_microcode
Macro [r128_cce.c, 208] r128_do_cce_flush
Macro [r128_cce.c, 209] r128_do_cce_flush
Macro [r128_cce.c, 220] r128_do_cce_idle
Macro [r128_cce.c, 244] r128_do_cce_start
Macro [r128_cce.c, 246] r128_do_cce_start
Macro [r128_cce.c, 247] r128_do_cce_start
Macro [r128_cce.c, 258] r128_do_cce_reset
Macro [r128_cce.c, 259] r128_do_cce_reset
Macro [r128_cce.c, 270] r128_do_cce_stop
Macro [r128_cce.c, 271] r128_do_cce_stop
Macro [r128_cce.c, 285] r128_do_engine_reset
Macro [r128_cce.c, 288] r128_do_engine_reset
Macro [r128_cce.c, 288] r128_do_engine_reset
Macro [r128_cce.c, 291] r128_do_engine_reset
Macro [r128_cce.c, 294] r128_do_engine_reset
Macro [r128_cce.c, 296] r128_do_engine_reset
Macro [r128_cce.c, 297] r128_do_engine_reset
Macro [r128_cce.c, 299] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
Macro [r128_cce.c, 302] r128_do_engine_reset
Macro [r128_cce.c, 303] r128_do_engine_reset
Macro [r128_cce.c, 335] r128_cce_init_ring_buffer
Macro [r128_cce.c, 337] r128_cce_init_ring_buffer
Macro [r128_cce.c, 338] r128_cce_init_ring_buffer
Macro [r128_cce.c, 344] r128_cce_init_ring_buffer
Macro [r128_cce.c, 353] r128_cce_init_ring_buffer
Macro [r128_cce.c, 361] r128_cce_init_ring_buffer
Macro [r128_cce.c, 368] r128_cce_init_ring_buffer
Macro [r128_cce.c, 371] r128_cce_init_ring_buffer
Macro [r128_cce.c, 372] r128_cce_init_ring_buffer
Macro [r128_cce.c, 594] r128_do_init_cce
Macro [r128_cce.c, 597] r128_do_init_cce
Macro [r128_cce.c, 608] r128_do_init_cce
Macro [r128_cce.c, 796] r128_do_init_pageflip
Macro [r128_cce.c, 797] r128_do_init_pageflip
Macro [r128_cce.c, 799] r128_do_init_pageflip
Macro [r128_cce.c, 800] r128_do_init_pageflip
Macro [r128_cce.c, 814] r128_do_cleanup_pageflip
Macro [r128_cce.c, 815] r128_do_cleanup_pageflip
Macro [r128_cce.c, 918] r128_freelist_get
Macro [r128_state.c, 82] r128_emit_clip_rects
Macro [r128_state.c, 97] r128_emit_core
Macro [r128_state.c, 123] r128_emit_context
Macro [r128_state.c, 139] r128_emit_setup
Macro [r128_state.c, 158] r128_emit_masks
Macro [r128_state.c, 173] r128_emit_window
Macro [r128_state.c, 200] r128_emit_tex0
Macro [r128_state.c, 224] r128_emit_tex1
Macro [r128_state.c, 399] r128_cce_dispatch_clear
Macro [r128_state.c, 420] r128_cce_dispatch_clear
Macro [r128_state.c, 441] r128_cce_dispatch_clear
Macro [r128_state.c, 463] r128_cce_dispatch_clear
Macro [r128_state.c, 511] r128_cce_dispatch_swap
Macro [r128_state.c, 525] r128_cce_dispatch_swap
Macro [r128_state.c, 553] r128_cce_dispatch_flip
Macro [r128_state.c, 566] r128_cce_dispatch_flip
Macro [r128_state.c, 612] r128_cce_dispatch_vertex
Macro [r128_state.c, 627] r128_cce_dispatch_vertex
Macro [r128_state.c, 675] r128_cce_dispatch_indirect
Macro [r128_state.c, 687] r128_cce_dispatch_indirect
Macro [r128_state.c, 770] r128_cce_dispatch_indices
Macro [r128_state.c, 827] r128_cce_dispatch_blit
Macro [r128_state.c, 881] r128_cce_dispatch_blit
Macro [r128_state.c, 954] r128_cce_dispatch_write_span
Macro [r128_state.c, 978] r128_cce_dispatch_write_span
Macro [r128_state.c, 1070] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1094] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1141] r128_cce_dispatch_read_span
Macro [r128_state.c, 1201] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1229] r128_cce_dispatch_stipple
R128_AGP_OFFSET
Declared as: 0x02000000
Define [r128_drv.h, 365] r128_drv.h
R128_AGP_TEX_HEAP
Declared as: 1
Define [r128_drm.h, 86] r128_drm.h
R128_AUX1_SC_BOTTOM
Declared as: 0x1670
Define [r128_drv.h, 189] r128_drv.h
R128_AUX1_SC_EN
Declared as: (1 << 0)
Define [r128_drv.h, 177] r128_drv.h
Use [r128_state.c, 58] r128_emit_clip_rects
R128_AUX1_SC_LEFT
Declared as: 0x1664
Define [r128_drv.h, 186] r128_drv.h
R128_AUX1_SC_MODE_NAND
Declared as: (1 << 1)
Define [r128_drv.h, 179] r128_drv.h
R128_AUX1_SC_MODE_OR
Declared as: (0 << 1)
Define [r128_drv.h, 178] r128_drv.h
Use [r128_state.c, 58] r128_emit_clip_rects
R128_AUX1_SC_RIGHT
Declared as: 0x1668
Define [r128_drv.h, 187] r128_drv.h
R128_AUX1_SC_TOP
Declared as: 0x166c
Define [r128_drv.h, 188] r128_drv.h
R128_AUX2_SC_BOTTOM
Declared as: 0x1680
Define [r128_drv.h, 193] r128_drv.h
R128_AUX2_SC_EN
Declared as: (1 << 2)
Define [r128_drv.h, 180] r128_drv.h
Use [r128_state.c, 67] r128_emit_clip_rects
R128_AUX2_SC_LEFT
Declared as: 0x1674
Define [r128_drv.h, 190] r128_drv.h
R128_AUX2_SC_MODE_NAND
Declared as: (1 << 3)
Define [r128_drv.h, 182] r128_drv.h
R128_AUX2_SC_MODE_OR
Declared as: (0 << 3)
Define [r128_drv.h, 181] r128_drv.h
Use [r128_state.c, 67] r128_emit_clip_rects
R128_AUX2_SC_RIGHT
Declared as: 0x1678
Define [r128_drv.h, 191] r128_drv.h
R128_AUX2_SC_TOP
Declared as: 0x167c
Define [r128_drv.h, 192] r128_drv.h
R128_AUX3_SC_BOTTOM
Declared as: 0x1690
Define [r128_drv.h, 197] r128_drv.h
R128_AUX3_SC_EN
Declared as: (1 << 4)
Define [r128_drv.h, 183] r128_drv.h
Use [r128_state.c, 76] r128_emit_clip_rects
R128_AUX3_SC_LEFT
Declared as: 0x1684
Define [r128_drv.h, 194] r128_drv.h
R128_AUX3_SC_MODE_NAND
Declared as: (1 << 5)
Define [r128_drv.h, 185] r128_drv.h
R128_AUX3_SC_MODE_OR
Declared as: (0 << 5)
Define [r128_drv.h, 184] r128_drv.h
Use [r128_state.c, 76] r128_emit_clip_rects
R128_AUX3_SC_RIGHT
Declared as: 0x1688
Define [r128_drv.h, 195] r128_drv.h
R128_AUX3_SC_TOP
Declared as: 0x168c
Define [r128_drv.h, 196] r128_drv.h
R128_AUX_SC_CNTL
Declared as: 0x1660
Define [r128_drv.h, 176] r128_drv.h
R128_BACK
Declared as: 0x2
Define [r128_drm.h, 57] r128_drm.h
Use [r128_state.c, 378] r128_cce_dispatch_clear
Use [r128_state.c, 379] r128_cce_dispatch_clear
Use [r128_state.c, 380] r128_cce_dispatch_clear
Use [r128_state.c, 393] r128_cce_dispatch_clear
Use [r128_state.c, 423] r128_cce_dispatch_clear
R128_BASE
Declared as: ((unsigned long)(dev_priv->mmio->handle))
Define [r128_drv.h, 384] r128_drv.h
Macro [r128_drv.h, 385] r128_drv.h
Macro [r128_cce.c, 92] R128_READ_PLL
Macro [r128_cce.c, 93] R128_READ_PLL
Macro [r128_cce.c, 124] r128_do_pixcache_flush
Macro [r128_cce.c, 125] r128_do_pixcache_flush
Macro [r128_cce.c, 128] r128_do_pixcache_flush
Macro [r128_cce.c, 145] r128_do_wait_for_fifo
Macro [r128_cce.c, 164] r128_do_wait_for_idle
Macro [r128_cce.c, 191] r128_cce_load_microcode
Macro [r128_cce.c, 193] r128_cce_load_microcode
Macro [r128_cce.c, 195] r128_cce_load_microcode
Macro [r128_cce.c, 208] r128_do_cce_flush
Macro [r128_cce.c, 209] r128_do_cce_flush
Macro [r128_cce.c, 220] r128_do_cce_idle
Macro [r128_cce.c, 244] r128_do_cce_start
Macro [r128_cce.c, 246] r128_do_cce_start
Macro [r128_cce.c, 247] r128_do_cce_start
Macro [r128_cce.c, 258] r128_do_cce_reset
Macro [r128_cce.c, 259] r128_do_cce_reset
Macro [r128_cce.c, 270] r128_do_cce_stop
Macro [r128_cce.c, 271] r128_do_cce_stop
Macro [r128_cce.c, 285] r128_do_engine_reset
Macro [r128_cce.c, 288] r128_do_engine_reset
Macro [r128_cce.c, 288] r128_do_engine_reset
Macro [r128_cce.c, 291] r128_do_engine_reset
Macro [r128_cce.c, 294] r128_do_engine_reset
Macro [r128_cce.c, 296] r128_do_engine_reset
Macro [r128_cce.c, 297] r128_do_engine_reset
Macro [r128_cce.c, 299] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
Macro [r128_cce.c, 302] r128_do_engine_reset
Macro [r128_cce.c, 303] r128_do_engine_reset
Macro [r128_cce.c, 335] r128_cce_init_ring_buffer
Macro [r128_cce.c, 337] r128_cce_init_ring_buffer
Macro [r128_cce.c, 338] r128_cce_init_ring_buffer
Macro [r128_cce.c, 344] r128_cce_init_ring_buffer
Macro [r128_cce.c, 353] r128_cce_init_ring_buffer
Macro [r128_cce.c, 361] r128_cce_init_ring_buffer
Macro [r128_cce.c, 368] r128_cce_init_ring_buffer
Macro [r128_cce.c, 371] r128_cce_init_ring_buffer
Macro [r128_cce.c, 372] r128_cce_init_ring_buffer
Macro [r128_cce.c, 594] r128_do_init_cce
Macro [r128_cce.c, 597] r128_do_init_cce
Macro [r128_cce.c, 608] r128_do_init_cce
Macro [r128_cce.c, 796] r128_do_init_pageflip
Macro [r128_cce.c, 797] r128_do_init_pageflip
Macro [r128_cce.c, 799] r128_do_init_pageflip
Macro [r128_cce.c, 800] r128_do_init_pageflip
Macro [r128_cce.c, 814] r128_do_cleanup_pageflip
Macro [r128_cce.c, 815] r128_do_cleanup_pageflip
Macro [r128_cce.c, 918] r128_freelist_get
Macro [r128_state.c, 82] r128_emit_clip_rects
Macro [r128_state.c, 97] r128_emit_core
Macro [r128_state.c, 123] r128_emit_context
Macro [r128_state.c, 139] r128_emit_setup
Macro [r128_state.c, 158] r128_emit_masks
Macro [r128_state.c, 173] r128_emit_window
Macro [r128_state.c, 200] r128_emit_tex0
Macro [r128_state.c, 224] r128_emit_tex1
Macro [r128_state.c, 399] r128_cce_dispatch_clear
Macro [r128_state.c, 420] r128_cce_dispatch_clear
Macro [r128_state.c, 441] r128_cce_dispatch_clear
Macro [r128_state.c, 463] r128_cce_dispatch_clear
Macro [r128_state.c, 511] r128_cce_dispatch_swap
Macro [r128_state.c, 525] r128_cce_dispatch_swap
Macro [r128_state.c, 553] r128_cce_dispatch_flip
Macro [r128_state.c, 566] r128_cce_dispatch_flip
Macro [r128_state.c, 612] r128_cce_dispatch_vertex
Macro [r128_state.c, 627] r128_cce_dispatch_vertex
Macro [r128_state.c, 675] r128_cce_dispatch_indirect
Macro [r128_state.c, 687] r128_cce_dispatch_indirect
Macro [r128_state.c, 770] r128_cce_dispatch_indices
Macro [r128_state.c, 827] r128_cce_dispatch_blit
Macro [r128_state.c, 881] r128_cce_dispatch_blit
Macro [r128_state.c, 954] r128_cce_dispatch_write_span
Macro [r128_state.c, 978] r128_cce_dispatch_write_span
Macro [r128_state.c, 1070] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1094] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1141] r128_cce_dispatch_read_span
Macro [r128_state.c, 1201] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1229] r128_cce_dispatch_stipple
R128_BROKEN_CCE
Declared as: 1
Define [r128_drv.h, 523] r128_drv.h
Macro [r128_drv.h, 525] r128_drv.h
Macro [r128_state.c, 82] r128_emit_clip_rects
Macro [r128_state.c, 97] r128_emit_core
Macro [r128_state.c, 123] r128_emit_context
Macro [r128_state.c, 139] r128_emit_setup
Macro [r128_state.c, 158] r128_emit_masks
Macro [r128_state.c, 173] r128_emit_window
Macro [r128_state.c, 200] r128_emit_tex0
Macro [r128_state.c, 224] r128_emit_tex1
Macro [r128_state.c, 399] r128_cce_dispatch_clear
Macro [r128_state.c, 420] r128_cce_dispatch_clear
Macro [r128_state.c, 441] r128_cce_dispatch_clear
Macro [r128_state.c, 463] r128_cce_dispatch_clear
Macro [r128_state.c, 511] r128_cce_dispatch_swap
Macro [r128_state.c, 525] r128_cce_dispatch_swap
Macro [r128_state.c, 553] r128_cce_dispatch_flip
Macro [r128_state.c, 566] r128_cce_dispatch_flip
Macro [r128_state.c, 612] r128_cce_dispatch_vertex
Macro [r128_state.c, 627] r128_cce_dispatch_vertex
Macro [r128_state.c, 675] r128_cce_dispatch_indirect
Macro [r128_state.c, 687] r128_cce_dispatch_indirect
Macro [r128_state.c, 770] r128_cce_dispatch_indices
Macro [r128_state.c, 827] r128_cce_dispatch_blit
Macro [r128_state.c, 881] r128_cce_dispatch_blit
Macro [r128_state.c, 954] r128_cce_dispatch_write_span
Macro [r128_state.c, 978] r128_cce_dispatch_write_span
Macro [r128_state.c, 1070] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1094] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1141] r128_cce_dispatch_read_span
Macro [r128_state.c, 1201] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1229] r128_cce_dispatch_stipple
R128_BRUSH_DATA0
Declared as: 0x1480
Define [r128_drv.h, 199] r128_drv.h
R128_BUFFER_FREE
Declared as: 0
Define [r128_cce.c, 850] r128_cce.c
R128_BUFFER_SIZE
Declared as: 16384
Define [r128_drm.h, 71] r128_drm.h
R128_BUFFER_USED
Declared as: 0xffffffff
Define [r128_cce.c, 849] r128_cce.c
R128_BUS_CNTL
Declared as: 0x0030
Define [r128_drv.h, 200] r128_drv.h
R128_BUS_MASTER_DIS
Declared as: (1 << 6)
Define [r128_drv.h, 201] r128_drv.h
Use [r128_cce.c, 371] r128_cce_init_ring_buffer
R128_CCE_PACKET0
Declared as: 0x00000000
Define [r128_drv.h, 327] r128_drv.h
Macro [r128_drv.h, 436] r128_drv.h
R128_CCE_PACKET0_REG_MASK
Declared as: 0x000007ff
Define [r128_drv.h, 338] r128_drv.h
R128_CCE_PACKET1
Declared as: 0x40000000
Define [r128_drv.h, 328] r128_drv.h
Macro [r128_drv.h, 438] r128_drv.h
R128_CCE_PACKET1_REG0_MASK
Declared as: 0x000007ff
Define [r128_drv.h, 339] r128_drv.h
R128_CCE_PACKET1_REG1_MASK
Declared as: 0x003ff800
Define [r128_drv.h, 340] r128_drv.h
R128_CCE_PACKET2
Declared as: 0x80000000
Define [r128_drv.h, 329] r128_drv.h
Macro [r128_drv.h, 440] r128_drv.h
Use [r128_state.c, 663] r128_cce_dispatch_indirect
R128_CCE_PACKET3
Declared as: 0xC0000000
Define [r128_drv.h, 330] r128_drv.h
Macro [r128_drv.h, 441] r128_drv.h
Macro [r128_state.c, 730] r128_cce_dispatch_indices
Macro [r128_state.c, 850] r128_cce_dispatch_blit
R128_CCE_PACKET_COUNT_MASK
Declared as: 0x3fff0000
Define [r128_drv.h, 337] r128_drv.h
R128_CCE_PACKET_MASK
Declared as: 0xC0000000
Define [r128_drv.h, 336] r128_drv.h
R128_CCE_VC_CNTL_NUM_SHIFT
Declared as: 16
Define [r128_drv.h, 353] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_LINE
Declared as: 0x00000002
Define [r128_drv.h, 344] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_NONE
Declared as: 0x00000000
Define [r128_drv.h, 342] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_POINT
Declared as: 0x00000001
Define [r128_drv.h, 343] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE
Declared as: 0x00000003
Define [r128_drv.h, 345] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN
Declared as: 0x00000005
Define [r128_drv.h, 347] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST
Declared as: 0x00000004
Define [r128_drv.h, 346] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP
Declared as: 0x00000006
Define [r128_drv.h, 348] r128_drv.h
R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2
Declared as: 0x00000007
Define [r128_drv.h, 349] r128_drv.h
Use [r128_state.c, 1326] r128_cce_vertex
Use [r128_state.c, 1389] r128_cce_indices
R128_CCE_VC_CNTL_PRIM_WALK_IND
Declared as: 0x00000010
Define [r128_drv.h, 350] r128_drv.h
Use [r128_state.c, 736] r128_cce_dispatch_indices
R128_CCE_VC_CNTL_PRIM_WALK_LIST
Declared as: 0x00000020
Define [r128_drv.h, 351] r128_drv.h
R128_CCE_VC_CNTL_PRIM_WALK_RING
Declared as: 0x00000030
Define [r128_drv.h, 352] r128_drv.h
R128_CLOCK_CNTL_DATA
Declared as: 0x000c
Define [r128_drv.h, 204] r128_drv.h
Macro [r128_drv.h, 426] r128_drv.h
R128_CLOCK_CNTL_INDEX
Declared as: 0x0008
Define [r128_drv.h, 203] r128_drv.h
Macro [r128_drv.h, 426] r128_drv.h
R128_CNTL_BITBLT_MULTI
Declared as: 0x00009B00
Define [r128_drv.h, 333] r128_drv.h
R128_CNTL_HOSTDATA_BLT
Declared as: 0x00009400
Define [r128_drv.h, 331] r128_drv.h
R128_CNTL_PAINT_MULTI
Declared as: 0x00009A00
Define [r128_drv.h, 332] r128_drv.h
R128_CONSTANT_COLOR_C
Declared as: 0x1d34
Define [r128_drv.h, 206] r128_drv.h
R128_CRTC_OFFSET
Declared as: 0x0224
Define [r128_drv.h, 207] r128_drv.h
R128_CRTC_OFFSET_CNTL
Declared as: 0x0228
Define [r128_drv.h, 208] r128_drv.h
R128_CRTC_OFFSET_FLIP_CNTL
Declared as: (1 << 16)
Define [r128_drv.h, 209] r128_drv.h
R128_DATATYPE_ARGB1555
Declared as: 3
Define [r128_drv.h, 356] r128_drv.h
Use [r128_state.c, 803] r128_cce_dispatch_blit
R128_DATATYPE_ARGB4444
Declared as: 15
Define [r128_drv.h, 362] r128_drv.h
Use [r128_state.c, 805] r128_cce_dispatch_blit
R128_DATATYPE_ARGB8888
Declared as: 6
Define [r128_drv.h, 359] r128_drv.h
Use [r128_cce.c, 453] r128_do_init_cce
Use [r128_cce.c, 468] r128_do_init_cce
Use [r128_state.c, 800] r128_cce_dispatch_blit
R128_DATATYPE_CI8
Declared as: 2
Define [r128_drv.h, 355] r128_drv.h
Use [r128_state.c, 808] r128_cce_dispatch_blit
R128_DATATYPE_RGB332
Declared as: 7
Define [r128_drv.h, 360] r128_drv.h
R128_DATATYPE_RGB565
Declared as: 4
Define [r128_drv.h, 357] r128_drv.h
Use [r128_cce.c, 449] r128_do_init_cce
Use [r128_cce.c, 463] r128_do_init_cce
Use [r128_state.c, 804] r128_cce_dispatch_blit
R128_DATATYPE_RGB8
Declared as: 9
Define [r128_drv.h, 361] r128_drv.h
Use [r128_state.c, 809] r128_cce_dispatch_blit
R128_DATATYPE_RGB888
Declared as: 5
Define [r128_drv.h, 358] r128_drv.h
R128_DEPTH
Declared as: 0x4
Define [r128_drm.h, 58] r128_drm.h
Use [r128_state.c, 444] r128_cce_dispatch_clear
R128_DEREF
Declared as: *(volatile u32 *)R128_ADDR( reg )
Define [r128_drv.h, 387] r128_drv.h
Macro [r128_drv.h, 401] r128_drv.h
Macro [r128_drv.h, 402] r128_drv.h
Macro [r128_cce.c, 93] R128_READ_PLL
Macro [r128_cce.c, 124] r128_do_pixcache_flush
Macro [r128_cce.c, 125] r128_do_pixcache_flush
Macro [r128_cce.c, 128] r128_do_pixcache_flush
Macro [r128_cce.c, 145] r128_do_wait_for_fifo
Macro [r128_cce.c, 164] r128_do_wait_for_idle
Macro [r128_cce.c, 191] r128_cce_load_microcode
Macro [r128_cce.c, 193] r128_cce_load_microcode
Macro [r128_cce.c, 195] r128_cce_load_microcode
Macro [r128_cce.c, 208] r128_do_cce_flush
Macro [r128_cce.c, 209] r128_do_cce_flush
Macro [r128_cce.c, 220] r128_do_cce_idle
Macro [r128_cce.c, 244] r128_do_cce_start
Macro [r128_cce.c, 246] r128_do_cce_start
Macro [r128_cce.c, 247] r128_do_cce_start
Macro [r128_cce.c, 258] r128_do_cce_reset
Macro [r128_cce.c, 259] r128_do_cce_reset
Macro [r128_cce.c, 270] r128_do_cce_stop
Macro [r128_cce.c, 271] r128_do_cce_stop
Macro [r128_cce.c, 285] r128_do_engine_reset
Macro [r128_cce.c, 288] r128_do_engine_reset
Macro [r128_cce.c, 291] r128_do_engine_reset
Macro [r128_cce.c, 294] r128_do_engine_reset
Macro [r128_cce.c, 296] r128_do_engine_reset
Macro [r128_cce.c, 297] r128_do_engine_reset
Macro [r128_cce.c, 299] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
Macro [r128_cce.c, 302] r128_do_engine_reset
Macro [r128_cce.c, 303] r128_do_engine_reset
Macro [r128_cce.c, 335] r128_cce_init_ring_buffer
Macro [r128_cce.c, 337] r128_cce_init_ring_buffer
Macro [r128_cce.c, 338] r128_cce_init_ring_buffer
Macro [r128_cce.c, 344] r128_cce_init_ring_buffer
Macro [r128_cce.c, 353] r128_cce_init_ring_buffer
Macro [r128_cce.c, 361] r128_cce_init_ring_buffer
Macro [r128_cce.c, 368] r128_cce_init_ring_buffer
Macro [r128_cce.c, 371] r128_cce_init_ring_buffer
Macro [r128_cce.c, 372] r128_cce_init_ring_buffer
Macro [r128_cce.c, 594] r128_do_init_cce
Macro [r128_cce.c, 597] r128_do_init_cce
Macro [r128_cce.c, 608] r128_do_init_cce
Macro [r128_cce.c, 796] r128_do_init_pageflip
Macro [r128_cce.c, 797] r128_do_init_pageflip
Macro [r128_cce.c, 799] r128_do_init_pageflip
Macro [r128_cce.c, 800] r128_do_init_pageflip
Macro [r128_cce.c, 814] r128_do_cleanup_pageflip
Macro [r128_cce.c, 815] r128_do_cleanup_pageflip
Macro [r128_cce.c, 918] r128_freelist_get
Macro [r128_state.c, 82] r128_emit_clip_rects
Macro [r128_state.c, 97] r128_emit_core
Macro [r128_state.c, 123] r128_emit_context
Macro [r128_state.c, 139] r128_emit_setup
Macro [r128_state.c, 158] r128_emit_masks
Macro [r128_state.c, 173] r128_emit_window
Macro [r128_state.c, 200] r128_emit_tex0
Macro [r128_state.c, 224] r128_emit_tex1
Macro [r128_state.c, 399] r128_cce_dispatch_clear
Macro [r128_state.c, 420] r128_cce_dispatch_clear
Macro [r128_state.c, 441] r128_cce_dispatch_clear
Macro [r128_state.c, 463] r128_cce_dispatch_clear
Macro [r128_state.c, 511] r128_cce_dispatch_swap
Macro [r128_state.c, 525] r128_cce_dispatch_swap
Macro [r128_state.c, 553] r128_cce_dispatch_flip
Macro [r128_state.c, 566] r128_cce_dispatch_flip
Macro [r128_state.c, 612] r128_cce_dispatch_vertex
Macro [r128_state.c, 627] r128_cce_dispatch_vertex
Macro [r128_state.c, 675] r128_cce_dispatch_indirect
Macro [r128_state.c, 687] r128_cce_dispatch_indirect
Macro [r128_state.c, 770] r128_cce_dispatch_indices
Macro [r128_state.c, 827] r128_cce_dispatch_blit
Macro [r128_state.c, 881] r128_cce_dispatch_blit
Macro [r128_state.c, 954] r128_cce_dispatch_write_span
Macro [r128_state.c, 978] r128_cce_dispatch_write_span
Macro [r128_state.c, 1070] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1094] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1141] r128_cce_dispatch_read_span
Macro [r128_state.c, 1201] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1229] r128_cce_dispatch_stipple
R128_DEREF8
Declared as: *(volatile u8 *)R128_ADDR( reg )
Define [r128_drv.h, 408] r128_drv.h
Macro [r128_drv.h, 422] r128_drv.h
Macro [r128_drv.h, 423] r128_drv.h
Macro [r128_cce.c, 92] R128_READ_PLL
Macro [r128_cce.c, 288] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
R128_DP_GUI_MASTER_CNTL
Declared as: 0x146c
Define [r128_drv.h, 211] r128_drv.h
R128_DP_SRC_SOURCE_HOST_DATA
Declared as: (3 << 24)
Define [r128_drv.h, 222] r128_drv.h
Use [r128_state.c, 856] r128_cce_dispatch_blit
R128_DP_SRC_SOURCE_MEMORY
Declared as: (2 << 24)
Define [r128_drv.h, 221] r128_drv.h
R128_DP_WRITE_MASK
Declared as: 0x16cc
Define [r128_drv.h, 228] r128_drv.h
R128_DST_PITCH_OFFSET_C
Declared as: 0x1c80
Define [r128_drv.h, 229] r128_drv.h
R128_DST_TILE
Declared as: (1 << 31)
Define [r128_drv.h, 230] r128_drv.h
Use [r128_cce.c, 481] r128_do_init_cce
R128_EVENT_CRTC_OFFSET
Declared as: (1 << 0)
Define [r128_drv.h, 271] r128_drv.h
Macro [r128_drv.h, 486] r128_drv.h
R128_FIFO_DEBUG
Declared as: 0
Define [r128_cce.c, 39] r128_cce.c
Use [r128_cce.c, 96] r128_cce.c
Use [r128_cce.c, 134] r128_do_pixcache_flush
Use [r128_cce.c, 150] r128_do_wait_for_fifo
Use [r128_cce.c, 171] r128_do_wait_for_idle
Use [r128_cce.c, 231] r128_do_cce_idle
r128_flush_write_combine
Declared as: mb()
Define [r128_drv.h, 496] r128_drv.h
Macro [r128_drv.h, 525] r128_drv.h
Macro [r128_state.c, 82] r128_emit_clip_rects
Macro [r128_state.c, 97] r128_emit_core
Macro [r128_state.c, 123] r128_emit_context
Macro [r128_state.c, 139] r128_emit_setup
Macro [r128_state.c, 158] r128_emit_masks
Macro [r128_state.c, 173] r128_emit_window
Macro [r128_state.c, 200] r128_emit_tex0
Macro [r128_state.c, 224] r128_emit_tex1
Macro [r128_state.c, 399] r128_cce_dispatch_clear
Macro [r128_state.c, 420] r128_cce_dispatch_clear
Macro [r128_state.c, 441] r128_cce_dispatch_clear
Macro [r128_state.c, 463] r128_cce_dispatch_clear
Macro [r128_state.c, 511] r128_cce_dispatch_swap
Macro [r128_state.c, 525] r128_cce_dispatch_swap
Macro [r128_state.c, 553] r128_cce_dispatch_flip
Macro [r128_state.c, 566] r128_cce_dispatch_flip
Macro [r128_state.c, 612] r128_cce_dispatch_vertex
Macro [r128_state.c, 627] r128_cce_dispatch_vertex
Macro [r128_state.c, 675] r128_cce_dispatch_indirect
Macro [r128_state.c, 687] r128_cce_dispatch_indirect
Macro [r128_state.c, 770] r128_cce_dispatch_indices
Macro [r128_state.c, 827] r128_cce_dispatch_blit
Macro [r128_state.c, 881] r128_cce_dispatch_blit
Macro [r128_state.c, 954] r128_cce_dispatch_write_span
Macro [r128_state.c, 978] r128_cce_dispatch_write_span
Macro [r128_state.c, 1070] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1094] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1141] r128_cce_dispatch_read_span
Macro [r128_state.c, 1201] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1229] r128_cce_dispatch_stipple
R128_FORCE_GCP
Declared as: (1 << 16)
Define [r128_drv.h, 247] r128_drv.h
R128_FORCE_PIPE3D_CP
Declared as: (1 << 17)
Define [r128_drv.h, 248] r128_drv.h
R128_FORCE_RCP
Declared as: (1 << 18)
Define [r128_drv.h, 249] r128_drv.h
R128_FRONT
Declared as: 0x1
Define [r128_drm.h, 56] r128_drm.h
Use [r128_state.c, 378] r128_cce_dispatch_clear
Use [r128_state.c, 379] r128_cce_dispatch_clear
Use [r128_state.c, 380] r128_cce_dispatch_clear
Use [r128_state.c, 393] r128_cce_dispatch_clear
Use [r128_state.c, 402] r128_cce_dispatch_clear
R128_GEN_RESET_CNTL
Declared as: 0x00f0
Define [r128_drv.h, 232] r128_drv.h
R128_GMC_AUX_CLIP_DIS
Declared as: (1 << 29)
Define [r128_drv.h, 224] r128_drv.h
Use [r128_state.c, 858] r128_cce_dispatch_blit
R128_GMC_BRUSH_NONE
Declared as: (15 << 4)
Define [r128_drv.h, 215] r128_drv.h
Use [r128_state.c, 852] r128_cce_dispatch_blit
R128_GMC_BRUSH_SOLID_COLOR
Declared as: (13 << 4)
Define [r128_drv.h, 214] r128_drv.h
R128_GMC_CLR_CMP_CNTL_DIS
Declared as: (1 << 28)
Define [r128_drv.h, 223] r128_drv.h
Use [r128_state.c, 857] r128_cce_dispatch_blit
R128_GMC_DST_16BPP
Declared as: (4 << 8)
Define [r128_drv.h, 216] r128_drv.h
R128_GMC_DST_24BPP
Declared as: (5 << 8)
Define [r128_drv.h, 217] r128_drv.h
R128_GMC_DST_32BPP
Declared as: (6 << 8)
Define [r128_drv.h, 218] r128_drv.h
R128_GMC_DST_DATATYPE_SHIFT
Declared as: 8
Define [r128_drv.h, 219] r128_drv.h
R128_GMC_DST_PITCH_OFFSET_CNTL
Declared as: (1 << 1)
Define [r128_drv.h, 213] r128_drv.h
Use [r128_state.c, 851] r128_cce_dispatch_blit
R128_GMC_SRC_DATATYPE_COLOR
Declared as: (3 << 12)
Define [r128_drv.h, 220] r128_drv.h
Use [r128_state.c, 854] r128_cce_dispatch_blit
R128_GMC_SRC_PITCH_OFFSET_CNTL
Declared as: (1 << 0)
Define [r128_drv.h, 212] r128_drv.h
R128_GMC_WR_MSK_DIS
Declared as: (1 << 30)
Define [r128_drv.h, 225] r128_drv.h
Use [r128_state.c, 859] r128_cce_dispatch_blit
R128_GUI_ACTIVE
Declared as: (1 << 31)
Define [r128_drv.h, 244] r128_drv.h
Use [r128_cce.c, 164] r128_do_wait_for_idle
R128_GUI_FIFOCNT_MASK
Declared as: 0x0fff
Define [r128_drv.h, 243] r128_drv.h
Use [r128_cce.c, 145] r128_do_wait_for_fifo
R128_GUI_SCRATCH_REG0
Declared as: 0x15e0
Define [r128_drv.h, 235] r128_drv.h
Macro [r128_drv.h, 374] r128_drv.h
R128_GUI_SCRATCH_REG1
Declared as: 0x15e4
Define [r128_drv.h, 236] r128_drv.h
Macro [r128_drv.h, 375] r128_drv.h
R128_GUI_SCRATCH_REG2
Declared as: 0x15e8
Define [r128_drv.h, 237] r128_drv.h
R128_GUI_SCRATCH_REG3
Declared as: 0x15ec
Define [r128_drv.h, 238] r128_drv.h
R128_GUI_SCRATCH_REG4
Declared as: 0x15f0
Define [r128_drv.h, 239] r128_drv.h
R128_GUI_SCRATCH_REG5
Declared as: 0x15f4
Define [r128_drv.h, 240] r128_drv.h
R128_GUI_STAT
Declared as: 0x1740
Define [r128_drv.h, 242] r128_drv.h
R128_HOSTDATA_BLIT_OFFSET
Declared as: 32
Define [r128_drm.h, 76] r128_drm.h
R128_INDEX_PRIM_OFFSET
Declared as: 20
Define [r128_drm.h, 75] r128_drm.h
Use [r128_state.c, 1411] r128_cce_indices
R128_LAST_DISPATCH_REG
Declared as: R128_GUI_SCRATCH_REG1
Define [r128_drv.h, 375] r128_drv.h
R128_LAST_FRAME_REG
Declared as: R128_GUI_SCRATCH_REG0
Define [r128_drv.h, 374] r128_drv.h
R128_LINE_STRIP
Declared as: 0x3
Define [r128_drm.h, 64] r128_drm.h
R128_LINES
Declared as: 0x2
Define [r128_drm.h, 63] r128_drm.h
R128_LOCAL_TEX_HEAP
Declared as: 0
Define [r128_drm.h, 85] r128_drm.h
R128_LOG_TEX_GRANULARITY
Declared as: 16
Define [r128_drm.h, 89] r128_drm.h
R128_MAX_TEXTURE_LEVELS
Declared as: 11
Define [r128_drm.h, 93] r128_drm.h
Use [r128_drm.h, 139] drm_r128_texture_regs_t
Use [r128_state.c, 192] r128_emit_tex0
Use [r128_state.c, 217] r128_emit_tex1
R128_MAX_TEXTURE_UNITS
Declared as: 2
Define [r128_drm.h, 94] r128_drm.h
Use [r128_drm.h, 149] drm_r128_sarea
R128_MAX_USEC_TIMEOUT
Declared as: 100000
Define [r128_drv.h, 372] r128_drv.h
Use [r128_cce.c, 399] r128_do_init_cce
R128_MAX_VB_AGE
Declared as: 0x7fffffff
Define [r128_drv.h, 376] r128_drv.h
Macro [r128_drv.h, 475] r128_drv.h
Macro [r128_state.c, 1332] r128_cce_vertex
Macro [r128_state.c, 1395] r128_cce_indices
Macro [r128_state.c, 1456] r128_cce_blit
R128_MAX_VB_VERTS
Declared as: (0xffff)
Define [r128_drv.h, 377] r128_drv.h
Use [r128_state.c, 734] r128_cce_dispatch_indices
R128_MCLK_CNTL
Declared as: 0x000f
Define [r128_drv.h, 246] r128_drv.h
Use [r128_cce.c, 286] r128_do_engine_reset
R128_NR_CONTEXT_REGS
Declared as: 12
Define [r128_drm.h, 91] r128_drm.h
R128_NR_SAREA_CLIPRECTS
Declared as: 12
Define [r128_drm.h, 80] r128_drm.h
Use [r128_drm.h, 156] drm_r128_sarea
Use [r128_state.c, 1255] r128_cce_clear
Use [r128_state.c, 1256] r128_cce_clear
Use [r128_state.c, 1280] r128_cce_swap
Use [r128_state.c, 1281] r128_cce_swap
R128_NR_TEX_HEAPS
Declared as: 2
Define [r128_drm.h, 87] r128_drm.h
Use [r128_drm.h, 164] drm_r128_sarea
Use [r128_drm.h, 165] drm_r128_sarea
R128_NR_TEX_REGIONS
Declared as: 64
Define [r128_drm.h, 88] r128_drm.h
Use [r128_drm.h, 164] drm_r128_sarea
R128_PC_BUSY
Declared as: (1 << 31)
Define [r128_drv.h, 256] r128_drv.h
Use [r128_cce.c, 128] r128_do_pixcache_flush
R128_PC_FLUSH_ALL
Declared as: 0x00ff
Define [r128_drv.h, 255] r128_drv.h
Use [r128_cce.c, 124] r128_do_pixcache_flush
R128_PC_FLUSH_GUI
Declared as: (3 << 0)
Define [r128_drv.h, 253] r128_drv.h
R128_PC_GUI_CTLSTAT
Declared as: 0x1748
Define [r128_drv.h, 251] r128_drv.h
R128_PC_NGUI_CTLSTAT
Declared as: 0x0184
Define [r128_drv.h, 252] r128_drv.h
R128_PC_RI_GUI
Declared as: (1 << 2)
Define [r128_drv.h, 254] r128_drv.h
R128_PCI_GART_PAGE
Declared as: 0x017c
Define [r128_drv.h, 258] r128_drv.h
R128_PERFORMANCE_BOXES
Declared as: 0
Define [r128_drv.h, 381] r128_drv.h
Use [r128_state.c, 276] r128_state.c
Use [r128_state.c, 478] r128_cce_dispatch_swap
Use [r128_state.c, 534] r128_cce_dispatch_flip
R128_PLL_WR_EN
Declared as: (1 << 7)
Define [r128_drv.h, 205] r128_drv.h
Macro [r128_drv.h, 426] r128_drv.h
R128_PM4_128BM_64INDBM
Declared as: (4 << 28)
Define [r128_drv.h, 284] r128_drv.h
Use [r128_cce.c, 417] r128_do_init_cce
Use [r128_cce.c, 435] r128_do_init_cce
R128_PM4_128PIO_64INDBM
Declared as: (3 << 28)
Define [r128_drv.h, 283] r128_drv.h
Use [r128_cce.c, 434] r128_do_init_cce
R128_PM4_192BM
Declared as: (2 << 28)
Define [r128_drv.h, 282] r128_drv.h
Use [r128_cce.c, 416] r128_do_init_cce
Use [r128_cce.c, 431] r128_do_init_cce
R128_PM4_192PIO
Declared as: (1 << 28)
Define [r128_drv.h, 281] r128_drv.h
Use [r128_cce.c, 430] r128_do_init_cce
R128_PM4_64BM_128INDBM
Declared as: (6 << 28)
Define [r128_drv.h, 286] r128_drv.h
Use [r128_cce.c, 418] r128_do_init_cce
Use [r128_cce.c, 439] r128_do_init_cce
R128_PM4_64BM_64VCBM_64INDBM
Declared as: (8 << 28)
Define [r128_drv.h, 288] r128_drv.h
Use [r128_cce.c, 419] r128_do_init_cce
Use [r128_cce.c, 441] r128_do_init_cce
R128_PM4_64PIO_128INDBM
Declared as: (5 << 28)
Define [r128_drv.h, 285] r128_drv.h
Use [r128_cce.c, 438] r128_do_init_cce
R128_PM4_64PIO_64VCBM_64INDBM
Declared as: (7 << 28)
Define [r128_drv.h, 287] r128_drv.h
Use [r128_cce.c, 440] r128_do_init_cce
R128_PM4_64PIO_64VCPIO_64INDPIO
Declared as: (15 << 28)
Define [r128_drv.h, 289] r128_drv.h
Use [r128_cce.c, 442] r128_do_init_cce
R128_PM4_BUFFER_ADDR
Declared as: 0x07f0
Define [r128_drv.h, 317] r128_drv.h
R128_PM4_BUFFER_CNTL
Declared as: 0x0704
Define [r128_drv.h, 278] r128_drv.h
R128_PM4_BUFFER_DL_DONE
Declared as: (1 << 31)
Define [r128_drv.h, 300] r128_drv.h
Use [r128_cce.c, 208] r128_do_cce_flush
R128_PM4_BUFFER_DL_RPTR
Declared as: 0x0710
Define [r128_drv.h, 298] r128_drv.h
R128_PM4_BUFFER_DL_RPTR_ADDR
Declared as: 0x070c
Define [r128_drv.h, 297] r128_drv.h
R128_PM4_BUFFER_DL_WPTR
Declared as: 0x0714
Define [r128_drv.h, 299] r128_drv.h
Macro [r128_drv.h, 525] r128_drv.h
R128_PM4_BUFFER_OFFSET
Declared as: 0x0700
Define [r128_drv.h, 277] r128_drv.h
R128_PM4_BUFFER_WM_CNTL
Declared as: 0x0708
Define [r128_drv.h, 291] r128_drv.h
R128_PM4_BUSY
Declared as: (1 << 16)
Define [r128_drv.h, 309] r128_drv.h
Use [r128_cce.c, 223] r128_do_cce_idle
R128_PM4_FIFO_DATA_EVEN
Declared as: 0x1000
Define [r128_drv.h, 321] r128_drv.h
R128_PM4_FIFO_DATA_ODD
Declared as: 0x1004
Define [r128_drv.h, 322] r128_drv.h
R128_PM4_FIFOCNT_MASK
Declared as: 0x0fff
Define [r128_drv.h, 308] r128_drv.h
Use [r128_cce.c, 221] r128_do_cce_idle
R128_PM4_GUI_ACTIVE
Declared as: (1 << 31)
Define [r128_drv.h, 310] r128_drv.h
Use [r128_cce.c, 224] r128_do_cce_idle
R128_PM4_IW_INDOFF
Declared as: 0x0738
Define [r128_drv.h, 304] r128_drv.h
R128_PM4_IW_INDSIZE
Declared as: 0x073c
Define [r128_drv.h, 305] r128_drv.h
R128_PM4_MASK
Declared as: (15 << 28)
Define [r128_drv.h, 279] r128_drv.h
R128_PM4_MICRO_CNTL
Declared as: 0x07fc
Define [r128_drv.h, 318] r128_drv.h
R128_PM4_MICRO_FREERUN
Declared as: (1 << 30)
Define [r128_drv.h, 319] r128_drv.h
R128_PM4_MICROCODE_ADDR
Declared as: 0x07d4
Define [r128_drv.h, 312] r128_drv.h
R128_PM4_MICROCODE_DATAH
Declared as: 0x07dc
Define [r128_drv.h, 314] r128_drv.h
R128_PM4_MICROCODE_DATAL
Declared as: 0x07e0
Define [r128_drv.h, 315] r128_drv.h
R128_PM4_MICROCODE_RADDR
Declared as: 0x07d8
Define [r128_drv.h, 313] r128_drv.h
R128_PM4_NONPM4
Declared as: (0 << 28)
Define [r128_drv.h, 280] r128_drv.h
Use [r128_cce.c, 427] r128_do_init_cce
Use [r128_cce.c, 677] r128_cce_start
R128_PM4_STAT
Declared as: 0x07b8
Define [r128_drv.h, 307] r128_drv.h
R128_PM4_VC_FPU_SETUP
Declared as: 0x071c
Define [r128_drv.h, 302] r128_drv.h
R128_POINTS
Declared as: 0x1
Define [r128_drm.h, 62] r128_drm.h
R128_PRIM_TEX_CNTL_C
Declared as: 0x1cb0
Define [r128_drv.h, 259] r128_drv.h
R128_READ
Declared as: le32_to_cpu( R128_DEREF( reg ) )
Define [r128_drv.h, 401] r128_drv.h
Use [r128_cce.c, 93] R128_READ_PLL
Use [r128_cce.c, 124] r128_do_pixcache_flush
Use [r128_cce.c, 128] r128_do_pixcache_flush
Use [r128_cce.c, 145] r128_do_wait_for_fifo
Use [r128_cce.c, 164] r128_do_wait_for_idle
Use [r128_cce.c, 208] r128_do_cce_flush
Use [r128_cce.c, 220] r128_do_cce_idle
Use [r128_cce.c, 246] r128_do_cce_start
Use [r128_cce.c, 285] r128_do_engine_reset
Use [r128_cce.c, 291] r128_do_engine_reset
Use [r128_cce.c, 296] r128_do_engine_reset
Use [r128_cce.c, 299] r128_do_engine_reset
Use [r128_cce.c, 368] r128_cce_init_ring_buffer
Use [r128_cce.c, 371] r128_cce_init_ring_buffer
Use [r128_cce.c, 796] r128_do_init_pageflip
Use [r128_cce.c, 797] r128_do_init_pageflip
Use [r128_cce.c, 918] r128_freelist_get
R128_READ8
Declared as: R128_DEREF8( reg )
Define [r128_drv.h, 422] r128_drv.h
R128_REQUIRE_QUIESCENCE
Declared as: 0x400
Define [r128_drm.h, 53] r128_drm.h
Use [r128_state.c, 272] r128_emit_state
Use [r128_state.c, 360] r128_print_dirty
R128_RING_HIGH_MARK
Declared as: 128
Define [r128_drv.h, 379] r128_drv.h
R128_ROP3_P
Declared as: 0x00f00000
Define [r128_drv.h, 227] r128_drv.h
R128_ROP3_S
Declared as: 0x00cc0000
Define [r128_drv.h, 226] r128_drv.h
Use [r128_state.c, 855] r128_cce_dispatch_blit
R128_SCALE_3D_CNTL
Declared as: 0x1a00
Define [r128_drv.h, 261] r128_drv.h
R128_SEC_TEX_CNTL_C
Declared as: 0x1d00
Define [r128_drv.h, 262] r128_drv.h
R128_SEC_TEXTURE_BORDER_COLOR_C
Declared as: 0x1d3c
Define [r128_drv.h, 263] r128_drv.h
R128_SETUP_CNTL
Declared as: 0x1bc4
Define [r128_drv.h, 264] r128_drv.h
R128_SOFT_RESET_GUI
Declared as: (1 << 0)
Define [r128_drv.h, 233] r128_drv.h
R128_STEN_REF_MASK_C
Declared as: 0x1d40
Define [r128_drv.h, 265] r128_drv.h
R128_TEX_CACHE_FLUSH
Declared as: (1 << 23)
Define [r128_drv.h, 268] r128_drv.h
Use [r128_state.c, 270] r128_emit_state
R128_TEX_CNTL_C
Declared as: 0x1c9c
Define [r128_drv.h, 267] r128_drv.h
R128_TRIANGLE_FAN
Declared as: 0x5
Define [r128_drm.h, 66] r128_drm.h
R128_TRIANGLE_STRIP
Declared as: 0x6
Define [r128_drm.h, 67] r128_drm.h
R128_TRIANGLES
Declared as: 0x4
Define [r128_drm.h, 65] r128_drm.h
R128_UPLOAD_ALL
Declared as: 0x7ff
Define [r128_drm.h, 54] r128_drm.h
R128_UPLOAD_CLIPRECTS
Declared as: 0x200
Define [r128_drm.h, 52] r128_drm.h
Use [r128_state.c, 359] r128_print_dirty
Use [r128_state.c, 590] r128_cce_dispatch_vertex
Use [r128_state.c, 637] r128_cce_dispatch_vertex
Use [r128_state.c, 721] r128_cce_dispatch_indices
Use [r128_state.c, 779] r128_cce_dispatch_indices
R128_UPLOAD_CONTEXT
Declared as: 0x001
Define [r128_drm.h, 43] r128_drm.h
Use [r128_state.c, 239] r128_emit_state
Use [r128_state.c, 241] r128_emit_state
Use [r128_state.c, 353] r128_print_dirty
Use [r128_state.c, 1262] r128_cce_clear
Use [r128_state.c, 1285] r128_cce_swap
R128_UPLOAD_CORE
Declared as: 0x040
Define [r128_drm.h, 49] r128_drm.h
Use [r128_state.c, 234] r128_emit_state
Use [r128_state.c, 236] r128_emit_state
Use [r128_state.c, 352] r128_print_dirty
R128_UPLOAD_MASKS
Declared as: 0x080
Define [r128_drm.h, 50] r128_drm.h
Use [r128_state.c, 249] r128_emit_state
Use [r128_state.c, 251] r128_emit_state
Use [r128_state.c, 357] r128_print_dirty
Use [r128_state.c, 1262] r128_cce_clear
Use [r128_state.c, 1286] r128_cce_swap
R128_UPLOAD_SETUP
Declared as: 0x002
Define [r128_drm.h, 44] r128_drm.h
Use [r128_state.c, 244] r128_emit_state
Use [r128_state.c, 246] r128_emit_state
Use [r128_state.c, 354] r128_print_dirty
R128_UPLOAD_TEX0
Declared as: 0x004
Define [r128_drm.h, 45] r128_drm.h
Use [r128_state.c, 259] r128_emit_state
Use [r128_state.c, 261] r128_emit_state
Use [r128_state.c, 355] r128_print_dirty
R128_UPLOAD_TEX0IMAGES
Declared as: 0x010
Define [r128_drm.h, 47] r128_drm.h
R128_UPLOAD_TEX1
Declared as: 0x008
Define [r128_drm.h, 46] r128_drm.h
Use [r128_state.c, 264] r128_emit_state
Use [r128_state.c, 266] r128_emit_state
Use [r128_state.c, 356] r128_print_dirty
R128_UPLOAD_TEX1IMAGES
Declared as: 0x020
Define [r128_drm.h, 48] r128_drm.h
R128_UPLOAD_WINDOW
Declared as: 0x100
Define [r128_drm.h, 51] r128_drm.h
Use [r128_state.c, 254] r128_emit_state
Use [r128_state.c, 256] r128_emit_state
Use [r128_state.c, 358] r128_print_dirty
R128_VERBOSE
Declared as: 0
Define [r128_drv.h, 499] r128_drv.h
Macro [r128_drv.h, 504] r128_drv.h
Macro [r128_drv.h, 525] r128_drv.h
Macro [r128_drv.h, 540] r128_drv.h
Macro [r128_state.c, 49] r128_emit_clip_rects
Macro [r128_state.c, 52] r128_emit_clip_rects
Macro [r128_state.c, 53] r128_emit_clip_rects
Macro [r128_state.c, 54] r128_emit_clip_rects
Macro [r128_state.c, 55] r128_emit_clip_rects
Macro [r128_state.c, 56] r128_emit_clip_rects
Macro [r128_state.c, 61] r128_emit_clip_rects
Macro [r128_state.c, 62] r128_emit_clip_rects
Macro [r128_state.c, 63] r128_emit_clip_rects
Macro [r128_state.c, 64] r128_emit_clip_rects
Macro [r128_state.c, 65] r128_emit_clip_rects
Macro [r128_state.c, 70] r128_emit_clip_rects
Macro [r128_state.c, 71] r128_emit_clip_rects
Macro [r128_state.c, 72] r128_emit_clip_rects
Macro [r128_state.c, 73] r128_emit_clip_rects
Macro [r128_state.c, 74] r128_emit_clip_rects
Macro [r128_state.c, 79] r128_emit_clip_rects
Macro [r128_state.c, 80] r128_emit_clip_rects
Macro [r128_state.c, 82] r128_emit_clip_rects
Macro [r128_state.c, 92] r128_emit_core
Macro [r128_state.c, 94] r128_emit_core
Macro [r128_state.c, 95] r128_emit_core
Macro [r128_state.c, 97] r128_emit_core
Macro [r128_state.c, 107] r128_emit_context
Macro [r128_state.c, 109] r128_emit_context
Macro [r128_state.c, 110] r128_emit_context
Macro [r128_state.c, 111] r128_emit_context
Macro [r128_state.c, 112] r128_emit_context
Macro [r128_state.c, 113] r128_emit_context
Macro [r128_state.c, 114] r128_emit_context
Macro [r128_state.c, 115] r128_emit_context
Macro [r128_state.c, 116] r128_emit_context
Macro [r128_state.c, 117] r128_emit_context
Macro [r128_state.c, 118] r128_emit_context
Macro [r128_state.c, 119] r128_emit_context
Macro [r128_state.c, 120] r128_emit_context
Macro [r128_state.c, 121] r128_emit_context
Macro [r128_state.c, 123] r128_emit_context
Macro [r128_state.c, 133] r128_emit_setup
Macro [r128_state.c, 135] r128_emit_setup
Macro [r128_state.c, 136] r128_emit_setup
Macro [r128_state.c, 137] r128_emit_setup
Macro [r128_state.c, 139] r128_emit_setup
Macro [r128_state.c, 149] r128_emit_masks
Macro [r128_state.c, 151] r128_emit_masks
Macro [r128_state.c, 152] r128_emit_masks
Macro [r128_state.c, 154] r128_emit_masks
Macro [r128_state.c, 155] r128_emit_masks
Macro [r128_state.c, 156] r128_emit_masks
Macro [r128_state.c, 158] r128_emit_masks
Macro [r128_state.c, 168] r128_emit_window
Macro [r128_state.c, 170] r128_emit_window
Macro [r128_state.c, 171] r128_emit_window
Macro [r128_state.c, 173] r128_emit_window
Macro [r128_state.c, 185] r128_emit_tex0
Macro [r128_state.c, 187] r128_emit_tex0
Macro [r128_state.c, 189] r128_emit_tex0
Macro [r128_state.c, 190] r128_emit_tex0
Macro [r128_state.c, 191] r128_emit_tex0
Macro [r128_state.c, 193] r128_emit_tex0
Macro [r128_state.c, 196] r128_emit_tex0
Macro [r128_state.c, 197] r128_emit_tex0
Macro [r128_state.c, 198] r128_emit_tex0
Macro [r128_state.c, 200] r128_emit_tex0
Macro [r128_state.c, 211] r128_emit_tex1
Macro [r128_state.c, 213] r128_emit_tex1
Macro [r128_state.c, 215] r128_emit_tex1
Macro [r128_state.c, 216] r128_emit_tex1
Macro [r128_state.c, 218] r128_emit_tex1
Macro [r128_state.c, 221] r128_emit_tex1
Macro [r128_state.c, 222] r128_emit_tex1
Macro [r128_state.c, 224] r128_emit_tex1
Macro [r128_state.c, 394] r128_cce_dispatch_clear
Macro [r128_state.c, 396] r128_cce_dispatch_clear
Macro [r128_state.c, 397] r128_cce_dispatch_clear
Macro [r128_state.c, 399] r128_cce_dispatch_clear
Macro [r128_state.c, 403] r128_cce_dispatch_clear
Macro [r128_state.c, 405] r128_cce_dispatch_clear
Macro [r128_state.c, 406] r128_cce_dispatch_clear
Macro [r128_state.c, 414] r128_cce_dispatch_clear
Macro [r128_state.c, 415] r128_cce_dispatch_clear
Macro [r128_state.c, 417] r128_cce_dispatch_clear
Macro [r128_state.c, 418] r128_cce_dispatch_clear
Macro [r128_state.c, 420] r128_cce_dispatch_clear
Macro [r128_state.c, 424] r128_cce_dispatch_clear
Macro [r128_state.c, 426] r128_cce_dispatch_clear
Macro [r128_state.c, 427] r128_cce_dispatch_clear
Macro [r128_state.c, 435] r128_cce_dispatch_clear
Macro [r128_state.c, 436] r128_cce_dispatch_clear
Macro [r128_state.c, 438] r128_cce_dispatch_clear
Macro [r128_state.c, 439] r128_cce_dispatch_clear
Macro [r128_state.c, 441] r128_cce_dispatch_clear
Macro [r128_state.c, 445] r128_cce_dispatch_clear
Macro [r128_state.c, 447] r128_cce_dispatch_clear
Macro [r128_state.c, 448] r128_cce_dispatch_clear
Macro [r128_state.c, 457] r128_cce_dispatch_clear
Macro [r128_state.c, 458] r128_cce_dispatch_clear
Macro [r128_state.c, 460] r128_cce_dispatch_clear
Macro [r128_state.c, 461] r128_cce_dispatch_clear
Macro [r128_state.c, 463] r128_cce_dispatch_clear
Macro [r128_state.c, 490] r128_cce_dispatch_swap
Macro [r128_state.c, 492] r128_cce_dispatch_swap
Macro [r128_state.c, 493] r128_cce_dispatch_swap
Macro [r128_state.c, 504] r128_cce_dispatch_swap
Macro [r128_state.c, 505] r128_cce_dispatch_swap
Macro [r128_state.c, 507] r128_cce_dispatch_swap
Macro [r128_state.c, 508] r128_cce_dispatch_swap
Macro [r128_state.c, 509] r128_cce_dispatch_swap
Macro [r128_state.c, 511] r128_cce_dispatch_swap
Macro [r128_state.c, 520] r128_cce_dispatch_swap
Macro [r128_state.c, 522] r128_cce_dispatch_swap
Macro [r128_state.c, 523] r128_cce_dispatch_swap
Macro [r128_state.c, 525] r128_cce_dispatch_swap
Macro [r128_state.c, 540] r128_cce_dispatch_flip
Macro [r128_state.c, 542] r128_cce_dispatch_flip
Macro [r128_state.c, 542] r128_cce_dispatch_flip
Macro [r128_state.c, 543] r128_cce_dispatch_flip
Macro [r128_state.c, 546] r128_cce_dispatch_flip
Macro [r128_state.c, 549] r128_cce_dispatch_flip
Macro [r128_state.c, 553] r128_cce_dispatch_flip
Macro [r128_state.c, 561] r128_cce_dispatch_flip
Macro [r128_state.c, 563] r128_cce_dispatch_flip
Macro [r128_state.c, 564] r128_cce_dispatch_flip
Macro [r128_state.c, 566] r128_cce_dispatch_flip
Macro [r128_state.c, 603] r128_cce_dispatch_vertex
Macro [r128_state.c, 605] r128_cce_dispatch_vertex
Macro [r128_state.c, 606] r128_cce_dispatch_vertex
Macro [r128_state.c, 607] r128_cce_dispatch_vertex
Macro [r128_state.c, 608] r128_cce_dispatch_vertex
Macro [r128_state.c, 609] r128_cce_dispatch_vertex
Macro [r128_state.c, 612] r128_cce_dispatch_vertex
Macro [r128_state.c, 622] r128_cce_dispatch_vertex
Macro [r128_state.c, 624] r128_cce_dispatch_vertex
Macro [r128_state.c, 625] r128_cce_dispatch_vertex
Macro [r128_state.c, 627] r128_cce_dispatch_vertex
Macro [r128_state.c, 669] r128_cce_dispatch_indirect
Macro [r128_state.c, 671] r128_cce_dispatch_indirect
Macro [r128_state.c, 672] r128_cce_dispatch_indirect
Macro [r128_state.c, 673] r128_cce_dispatch_indirect
Macro [r128_state.c, 675] r128_cce_dispatch_indirect
Macro [r128_state.c, 682] r128_cce_dispatch_indirect
Macro [r128_state.c, 684] r128_cce_dispatch_indirect
Macro [r128_state.c, 685] r128_cce_dispatch_indirect
Macro [r128_state.c, 687] r128_cce_dispatch_indirect
Macro [r128_state.c, 765] r128_cce_dispatch_indices
Macro [r128_state.c, 767] r128_cce_dispatch_indices
Macro [r128_state.c, 768] r128_cce_dispatch_indices
Macro [r128_state.c, 770] r128_cce_dispatch_indices
Macro [r128_state.c, 822] r128_cce_dispatch_blit
Macro [r128_state.c, 824] r128_cce_dispatch_blit
Macro [r128_state.c, 825] r128_cce_dispatch_blit
Macro [r128_state.c, 827] r128_cce_dispatch_blit
Macro [r128_state.c, 876] r128_cce_dispatch_blit
Macro [r128_state.c, 878] r128_cce_dispatch_blit
Macro [r128_state.c, 879] r128_cce_dispatch_blit
Macro [r128_state.c, 881] r128_cce_dispatch_blit
Macro [r128_state.c, 937] r128_cce_dispatch_write_span
Macro [r128_state.c, 939] r128_cce_dispatch_write_span
Macro [r128_state.c, 940] r128_cce_dispatch_write_span
Macro [r128_state.c, 948] r128_cce_dispatch_write_span
Macro [r128_state.c, 949] r128_cce_dispatch_write_span
Macro [r128_state.c, 951] r128_cce_dispatch_write_span
Macro [r128_state.c, 952] r128_cce_dispatch_write_span
Macro [r128_state.c, 954] r128_cce_dispatch_write_span
Macro [r128_state.c, 961] r128_cce_dispatch_write_span
Macro [r128_state.c, 963] r128_cce_dispatch_write_span
Macro [r128_state.c, 964] r128_cce_dispatch_write_span
Macro [r128_state.c, 972] r128_cce_dispatch_write_span
Macro [r128_state.c, 973] r128_cce_dispatch_write_span
Macro [r128_state.c, 975] r128_cce_dispatch_write_span
Macro [r128_state.c, 976] r128_cce_dispatch_write_span
Macro [r128_state.c, 978] r128_cce_dispatch_write_span
Macro [r128_state.c, 1053] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1055] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1056] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1064] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1065] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1067] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1068] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1070] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1077] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1079] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1080] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1088] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1089] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1091] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1092] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1094] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1121] r128_cce_dispatch_read_span
Macro [r128_state.c, 1123] r128_cce_dispatch_read_span
Macro [r128_state.c, 1124] r128_cce_dispatch_read_span
Macro [r128_state.c, 1134] r128_cce_dispatch_read_span
Macro [r128_state.c, 1135] r128_cce_dispatch_read_span
Macro [r128_state.c, 1137] r128_cce_dispatch_read_span
Macro [r128_state.c, 1138] r128_cce_dispatch_read_span
Macro [r128_state.c, 1139] r128_cce_dispatch_read_span
Macro [r128_state.c, 1141] r128_cce_dispatch_read_span
Macro [r128_state.c, 1181] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1183] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1184] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1194] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1195] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1197] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1198] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1199] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1201] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1222] r128_cce_dispatch_stipple
Macro [r128_state.c, 1224] r128_cce_dispatch_stipple
Macro [r128_state.c, 1226] r128_cce_dispatch_stipple
Macro [r128_state.c, 1229] r128_cce_dispatch_stipple
R128_WAIT_UNTIL
Declared as: 0x1720
Define [r128_drv.h, 270] r128_drv.h
Macro [r128_drv.h, 486] r128_drv.h
R128_WAIT_UNTIL_PAGE_FLIPPED
Declared as: do { OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); OUT_RING( R128_EVENT_CRTC_OFFSET ); } while (0)
Define [r128_drv.h, 486] r128_drv.h
Use [r128_state.c, 542] r128_cce_dispatch_flip
R128_WATERMARK_K
Declared as: 128
Define [r128_drv.h, 370] r128_drv.h
R128_WATERMARK_L
Declared as: 16
Define [r128_drv.h, 367] r128_drv.h
R128_WATERMARK_M
Declared as: 8
Define [r128_drv.h, 368] r128_drv.h
R128_WATERMARK_N
Declared as: 8
Define [r128_drv.h, 369] r128_drv.h
R128_WB_WM_SHIFT
Declared as: 24
Define [r128_drv.h, 295] r128_drv.h
R128_WINDOW_XY_OFFSET
Declared as: 0x1bcc
Define [r128_drv.h, 272] r128_drv.h
R128_WMA_SHIFT
Declared as: 0
Define [r128_drv.h, 292] r128_drv.h
R128_WMB_SHIFT
Declared as: 8
Define [r128_drv.h, 293] r128_drv.h
R128_WMC_SHIFT
Declared as: 16
Define [r128_drv.h, 294] r128_drv.h
R128_WRITE
Declared as: do { R128_DEREF( reg ) = cpu_to_le32( val ); } while (0)
Define [r128_drv.h, 402] r128_drv.h
Macro [r128_drv.h, 426] r128_drv.h
Macro [r128_drv.h, 525] r128_drv.h
Use [r128_cce.c, 125] r128_do_pixcache_flush
Use [r128_cce.c, 191] r128_cce_load_microcode
Use [r128_cce.c, 193] r128_cce_load_microcode
Use [r128_cce.c, 195] r128_cce_load_microcode
Use [r128_cce.c, 209] r128_do_cce_flush
Use [r128_cce.c, 244] r128_do_cce_start
Use [r128_cce.c, 247] r128_do_cce_start
Use [r128_cce.c, 258] r128_do_cce_reset
Use [r128_cce.c, 259] r128_do_cce_reset
Use [r128_cce.c, 270] r128_do_cce_stop
Use [r128_cce.c, 271] r128_do_cce_stop
Macro [r128_cce.c, 288] r128_do_engine_reset
Use [r128_cce.c, 294] r128_do_engine_reset
Use [r128_cce.c, 297] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
Use [r128_cce.c, 302] r128_do_engine_reset
Use [r128_cce.c, 303] r128_do_engine_reset
Use [r128_cce.c, 335] r128_cce_init_ring_buffer
Use [r128_cce.c, 337] r128_cce_init_ring_buffer
Use [r128_cce.c, 338] r128_cce_init_ring_buffer
Use [r128_cce.c, 344] r128_cce_init_ring_buffer
Use [r128_cce.c, 353] r128_cce_init_ring_buffer
Use [r128_cce.c, 361] r128_cce_init_ring_buffer
Use [r128_cce.c, 372] r128_cce_init_ring_buffer
Use [r128_cce.c, 594] r128_do_init_cce
Use [r128_cce.c, 597] r128_do_init_cce
Use [r128_cce.c, 608] r128_do_init_cce
Use [r128_cce.c, 799] r128_do_init_pageflip
Use [r128_cce.c, 800] r128_do_init_pageflip
Use [r128_cce.c, 814] r128_do_cleanup_pageflip
Use [r128_cce.c, 815] r128_do_cleanup_pageflip
Macro [r128_state.c, 82] r128_emit_clip_rects
Macro [r128_state.c, 97] r128_emit_core
Macro [r128_state.c, 123] r128_emit_context
Macro [r128_state.c, 139] r128_emit_setup
Macro [r128_state.c, 158] r128_emit_masks
Macro [r128_state.c, 173] r128_emit_window
Macro [r128_state.c, 200] r128_emit_tex0
Macro [r128_state.c, 224] r128_emit_tex1
Macro [r128_state.c, 399] r128_cce_dispatch_clear
Macro [r128_state.c, 420] r128_cce_dispatch_clear
Macro [r128_state.c, 441] r128_cce_dispatch_clear
Macro [r128_state.c, 463] r128_cce_dispatch_clear
Macro [r128_state.c, 511] r128_cce_dispatch_swap
Macro [r128_state.c, 525] r128_cce_dispatch_swap
Macro [r128_state.c, 553] r128_cce_dispatch_flip
Macro [r128_state.c, 566] r128_cce_dispatch_flip
Macro [r128_state.c, 612] r128_cce_dispatch_vertex
Macro [r128_state.c, 627] r128_cce_dispatch_vertex
Macro [r128_state.c, 675] r128_cce_dispatch_indirect
Macro [r128_state.c, 687] r128_cce_dispatch_indirect
Macro [r128_state.c, 770] r128_cce_dispatch_indices
Macro [r128_state.c, 827] r128_cce_dispatch_blit
Macro [r128_state.c, 881] r128_cce_dispatch_blit
Macro [r128_state.c, 954] r128_cce_dispatch_write_span
Macro [r128_state.c, 978] r128_cce_dispatch_write_span
Macro [r128_state.c, 1070] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1094] r128_cce_dispatch_write_pixels
Macro [r128_state.c, 1141] r128_cce_dispatch_read_span
Macro [r128_state.c, 1201] r128_cce_dispatch_read_pixels
Macro [r128_state.c, 1229] r128_cce_dispatch_stipple
R128_WRITE8
Declared as: do { R128_DEREF8( reg ) = val; } while (0)
Define [r128_drv.h, 423] r128_drv.h
Macro [r128_drv.h, 426] r128_drv.h
Use [r128_cce.c, 92] R128_READ_PLL
Macro [r128_cce.c, 288] r128_do_engine_reset
Macro [r128_cce.c, 301] r128_do_engine_reset
R128_WRITE_PLL
Declared as: do { R128_WRITE8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); } while (0)
Define [r128_drv.h, 426] r128_drv.h
Use [r128_cce.c, 288] r128_do_engine_reset
Use [r128_cce.c, 301] r128_do_engine_reset
R12_OFF
Declared as: 0x60
Define [nmi.h, 97] nmi.h
r12w
Declared as: (delay_p,inw(pi->port+1)&0xffff)
Define [kbic.c, 32] kbic.c
Use [kbic.c, 57] kbic_read_regr
R13
Declared as: 13
Define [macserial.h, 234] macserial.h
Use [macserial.c, 275] load_zsregs
Use [macserial.c, 275] load_zsregs
R13
Declared as: 13
Define [zs.h, 201] zs.h
Use [zs.c, 327] load_zsregs
Use [zs.c, 327] load_zsregs
R13
Declared as: 13
Define [zs.h, 198] zs.h
Use [zs.c, 310] load_zsregs
Use [zs.c, 310] load_zsregs
Use [zs.c, 378] kgdb_chaninit
Use [zs.c, 2225] zs_change_mouse_baud
Use [zs.c, 2527] zs_init
Use [zs.c, 2571] zs_init
Use [zs.c, 2629] zs_init
R13
Declared as: 13
Define [z85230.h, 37] z85230.h
R13
Declared as: 13
Define [z8530.h, 19] z8530.h
Use [dmascc.c, 803] scc_open
Use [scc.c, 721] set_brg
Use [scc.c, 1795] scc_net_ioctl
Use [scc.c, 1798] scc_net_ioctl
r13
Declared as: 13
Define [ppc_asm.tmpl, 28] ppc_asm.tmpl
R13
Declared as: 13
Define [sgiserial.h, 205] sgiserial.h
Use [sgiserial.c, 229] load_zsregs
Use [sgiserial.c, 229] load_zsregs
Use [sgiserial.c, 265] kgdb_chaninit
R13_OFF
Declared as: 0x68
Define [nmi.h, 98] nmi.h
R14
Declared as: 14
Define [macserial.h, 235] macserial.h
Use [macserial.c, 276] load_zsregs
Use [macserial.c, 276] load_zsregs
Use [dmascc.c, 806] scc_open
Use [dmascc.c, 808] scc_open
Use [dmascc.c, 811] scc_open
Use [scc.c, 361] start_hunt
Use [scc.c, 361] start_hunt
Use [scc.c, 457] scc_exint
Use [scc.c, 457] scc_exint
Use [scc.c, 719] set_brg
Use [scc.c, 722] set_brg
Use [scc.c, 740] init_brg
Use [scc.c, 741] init_brg
Use [scc.c, 741] init_brg
Use [scc.c, 742] init_brg
Use [scc.c, 742] init_brg
Use [scc.c, 805] init_channel
Use [scc.c, 848] init_channel
Use [z85230.c, 895] z8530_sync_dma_open
Use [z85230.c, 896] z8530_sync_dma_open
Use [z85230.c, 896] z8530_sync_dma_open
Use [z85230.c, 998] z8530_sync_dma_close
Use [z85230.c, 999] z8530_sync_dma_close
Use [z85230.c, 999] z8530_sync_dma_close
Use [z85230.c, 1081] z8530_sync_txdma_open
Use [z85230.c, 1082] z8530_sync_txdma_open
Use [z85230.c, 1082] z8530_sync_txdma_open
Use [z85230.c, 1159] z8530_sync_txdma_close
Use [z85230.c, 1160] z8530_sync_txdma_close
Use [z85230.c, 1160] z8530_sync_txdma_close
Use [zs.c, 311] load_zsregs
Use [zs.c, 311] load_zsregs
Use [zs.c, 312] load_zsregs
Use [zs.c, 312] load_zsregs
Use [zs.c, 313] load_zsregs
Use [zs.c, 313] load_zsregs
Use [zs.c, 2529] zs_init
Use [zs.c, 2532] zs_init
Use [zs.c, 2573] zs_init
Use [zs.c, 2576] zs_init
Use [zs.c, 2631] zs_init
Use [zs.c, 2632] zs_init
Use [sgiserial.c, 230] load_zsregs
Use [sgiserial.c, 230] load_zsregs
Use [zs.c, 328] load_zsregs
Use [zs.c, 328] load_zsregs
R14
Declared as: 14
Define [zs.h, 202] zs.h
R14
Declared as: 14
Define [zs.h, 199] zs.h
R14
Declared as: 14
Define [z85230.h, 38] z85230.h
R14
Declared as: 14
Define [z8530.h, 20] z8530.h
r14
Declared as: 14
Define [ppc_asm.tmpl, 29] ppc_asm.tmpl
R14
Declared as: 14
Define [sgiserial.h, 206] sgiserial.h
R14_OFF
Declared as: 0x70
Define [nmi.h, 99] nmi.h
R15
Declared as: 15
Define [macserial.h, 236] macserial.h
Use [macserial.c, 277] load_zsregs
Use [macserial.c, 277] load_zsregs
Use [dmascc.c, 495] setup_adapter
Use [dmascc.c, 496] setup_adapter
Use [dmascc.c, 510] setup_adapter
Use [dmascc.c, 523] setup_adapter
Use [dmascc.c, 541] setup_adapter
Use [dmascc.c, 760] scc_open
Use [dmascc.c, 763] scc_open
Use [dmascc.c, 767] scc_open
Use [dmascc.c, 793] scc_open
Use [dmascc.c, 840] scc_open
Use [dmascc.c, 927] scc_send_packet
Use [dmascc.c, 1209] es_isr
Use [dmascc.c, 1227] es_isr
Use [dmascc.c, 1235] es_isr
Use [dmascc.c, 1258] tm_isr
Use [dmascc.c, 1262] tm_isr
Use [dmascc.c, 1278] tm_isr
Use [dmascc.c, 1282] tm_isr
Use [dmascc.c, 1287] tm_isr
Use [dmascc.c, 1316] tx_on
Use [dmascc.c, 1331] tx_on
Use [dmascc.c, 1399] start_timer
Use [scc.c, 857] init_channel
Use [scc.c, 869] init_channel
Use [scc.c, 913] scc_key_trx
Use [scc.c, 949] scc_key_trx
Use [scc.c, 981] scc_key_trx
Use [scc.c, 1261] t_maxkeyup
Use [scc.c, 1337] scc_set_param
Use [scc.c, 1338] scc_set_param
Use [scc.c, 1341] scc_set_param
Use [scc.c, 1342] scc_set_param
Use [z85230.c, 1254] z8530_init
Use [z85230.c, 1261] z8530_init
Use [z85230.c, 1278] z8530_init
Use [z85230.c, 1331] z8530_channel_load
Use [z85230.c, 1334] z8530_channel_load
Use [zs.c, 316] load_zsregs
Use [zs.c, 316] load_zsregs
Use [zs.c, 2539] zs_init
Use [zs.c, 2582] zs_init
Use [zs.c, 2636] zs_init
Use [sgiserial.c, 231] load_zsregs
Use [sgiserial.c, 231] load_zsregs
Use [zs.c, 329] load_zsregs
Use [zs.c, 329] load_zsregs
R15
Declared as: 15
Define [zs.h, 203] zs.h
R15
Declared as: 15
Define [zs.h, 200] zs.h
R15
Declared as: 15
Define [z85230.h, 39] z85230.h
R15
Declared as: 15
Define [z8530.h, 21] z8530.h
r15
Declared as: 15
Define [ppc_asm.tmpl, 30] ppc_asm.tmpl
R15
Declared as: 15
Define [sgiserial.h, 207] sgiserial.h
R15_OFF
Declared as: 0x78
Define [nmi.h, 100] nmi.h
r16
Declared as: 16
Define [ppc_asm.tmpl, 31] ppc_asm.tmpl
R16_OFF
Declared as: 0x80
Define [nmi.h, 101] nmi.h
r17
Declared as: 17
Define [ppc_asm.tmpl, 32] ppc_asm.tmpl
R17_OFF
Declared as: 0x88
Define [nmi.h, 102] nmi.h
r18
Declared as: 18
Define [ppc_asm.tmpl, 33] ppc_asm.tmpl
R18_OFF
Declared as: 0x90
Define [nmi.h, 103] nmi.h
r19
Declared as: 19
Define [ppc_asm.tmpl, 34] ppc_asm.tmpl
R19_OFF
Declared as: 0x98
Define [nmi.h, 104] nmi.h
R1_OFF
Declared as: 0x8
Define [nmi.h, 86] nmi.h
R1BH_PreAlloc
Declared as: 3
Define [raid1.h, 90] raid1.h
Use [raid1.c, 165] raid1_alloc_r1bh
Use [raid1.c, 218] raid1_grow_r1bh
R1BH_PreAlloc
Declared as: 3
Define [raid1.h, 93] raid1.h
R1BH_SyncPhase
Declared as: 2
Define [raid1.h, 89] raid1.h
Use [raid1.c, 591] raid1_make_request
R1BH_SyncPhase
Declared as: 2
Define [raid1.h, 92] raid1.h
R1BH_Uptodate
Declared as: 1
Define [raid1.h, 88] raid1.h
Use [raid1.c, 411] raid1_end_request
Use [raid1.c, 1450] end_sync_read
R1BH_Uptodate
Declared as: 1
Define [raid1.h, 91] raid1.h
R2
Declared as: 2
Define [macserial.h, 223] macserial.h
R2
Declared as: 2
Define [zs.h, 190] zs.h
Use [zs.c, 323] load_zsregs
Use [zs.c, 323] load_zsregs
r2
Declared as: (PC=(in_p(2) & 0xff))
Define [bpck.c, 32] bpck.c
Use [bpck.c, 202] bpck_probe_unit
Use [comm.c, 92] comm_connect
Use [dstr.c, 103] dstr_connect
Use [epat.c, 73] epat_read_regr
Use [epat.c, 113] epat_read_block
Use [epat.c, 208] epat_connect
Use [epia.c, 64] epia_read_regr
Use [epia.c, 115] epia_connect
Use [epia.c, 157] epia_read_block
Use [fit2.c, 105] fit2_connect
Use [fit3.c, 157] fit3_connect
Use [friq.c, 171] friq_connect
Use [frpw.c, 175] frpw_connect
Use [frpw.c, 205] frpw_test_pnp
Use [kbic.c, 101] k951_connect
Use [kbic.c, 117] k971_connect
Use [ktti.c, 81] ktti_connect
Use [on20.c, 72] on20_connect
Use [on26.c, 106] on26_connect
Use [on26.c, 131] on26_test_port
r2
Declared as: (in_p(2) & 0xff)
Define [paride.h, 108] paride.h
Use [aten.c, 112] aten_connect
Use [bpck.c, 28] bpck.c
R2
Declared as: 2
Define [zs.h, 187] zs.h
R2
Declared as: 2
Define [z85230.h, 26] z85230.h
R2
Declared as: 2
Define [z8530.h, 8] z8530.h
Use [scc.c, 677] scc_isr
Use [scc.c, 1519] z8530_init
r2
Declared as: 2
Define [ppc_asm.tmpl, 17] ppc_asm.tmpl
R2
Declared as: 2
Define [sgiserial.h, 194] sgiserial.h
r20
Declared as: 20
Define [ppc_asm.tmpl, 35] ppc_asm.tmpl
R20_OFF
Declared as: 0xa0
Define [nmi.h, 105] nmi.h
r21
Declared as: 21
Define [ppc_asm.tmpl, 36] ppc_asm.tmpl
R21_OFF
Declared as: 0xa8
Define [nmi.h, 106] nmi.h
r22
Declared as: 22
Define [ppc_asm.tmpl, 37] ppc_asm.tmpl
R22_OFF
Declared as: 0xb0
Define [nmi.h, 107] nmi.h
r23
Declared as: 23
Define [ppc_asm.tmpl, 38] ppc_asm.tmpl
R23_OFF
Declared as: 0xb8
Define [nmi.h, 108] nmi.h
r24
Declared as: 24
Define [ppc_asm.tmpl, 39] ppc_asm.tmpl
R24_OFF
Declared as: 0xc0
Define [nmi.h, 109] nmi.h
r25
Declared as: 25
Define [ppc_asm.tmpl, 40] ppc_asm.tmpl
R25_OFF
Declared as: 0xc8
Define [nmi.h, 110] nmi.h
r26
Declared as: 26
Define [ppc_asm.tmpl, 41] ppc_asm.tmpl
R26_OFF
Declared as: 0xd0
Define [nmi.h, 111] nmi.h
r27
Declared as: 27
Define [ppc_asm.tmpl, 42] ppc_asm.tmpl
R27_OFF
Declared as: 0xd8
Define [nmi.h, 112] nmi.h
r28
Declared as: 28
Define [ppc_asm.tmpl, 43] ppc_asm.tmpl
R28_OFF
Declared as: 0xe0
Define [nmi.h, 113] nmi.h
r29
Declared as: 29
Define [ppc_asm.tmpl, 44] ppc_asm.tmpl
R29_OFF
Declared as: 0xe8
Define [nmi.h, 114] nmi.h
R2_OFF
Declared as: 0x10
Define [nmi.h, 87] nmi.h
R3
Declared as: 3
Define [macserial.h, 224] macserial.h
Use [macserial.c, 269] load_zsregs
Use [macserial.c, 269] load_zsregs
Use [macserial.c, 278] load_zsregs
Use [macserial.c, 278] load_zsregs
Use [macserial.c, 2803] serial_console_wait_key
Use [macserial.c, 2812] serial_console_wait_key
R3
Declared as: 3
Define [zs.h, 191] zs.h
Use [zs.c, 319] load_zsregs
Use [zs.c, 319] load_zsregs
Use [zs.c, 330] load_zsregs
Use [zs.c, 330] load_zsregs
Use [zs.c, 578] rs_interrupt
R3
Declared as: 3
Define [zs.h, 188] zs.h
Use [zs.c, 291] load_zsregs
Use [zs.c, 304] load_zsregs
Use [zs.c, 304] load_zsregs
Use [zs.c, 314] load_zsregs
Use [zs.c, 314] load_zsregs
Use [zs.c, 2516] zs_init
Use [zs.c, 2534] zs_init
Use [zs.c, 2559] zs_init
Use [zs.c, 2578] zs_init
Use [zs.c, 2618] zs_init
Use [zs.c, 2634] zs_init
R3
Declared as: 3
Define [z85230.h, 27] z85230.h
Use [z85230.c, 472] z8530_status
Use [z85230.c, 481] z8530_status
Use [z85230.c, 591] z8530_dma_status
Use [z85230.c, 600] z8530_dma_status
Use [z85230.c, 729] z8530_interrupt
Use [z85230.c, 802] z8530_sync_open
Use [z85230.c, 802] z8530_sync_open
Use [z85230.c, 827] z8530_sync_close
Use [z85230.c, 827] z8530_sync_close
Use [z85230.c, 947] z8530_sync_dma_open
Use [z85230.c, 947] z8530_sync_dma_open
Use [z85230.c, 1012] z8530_sync_dma_close
Use [z85230.c, 1012] z8530_sync_dma_close
Use [z85230.c, 1112] z8530_sync_txdma_open
Use [z85230.c, 1112] z8530_sync_txdma_open
Use [z85230.c, 1168] z8530_sync_txdma_close
Use [z85230.c, 1168] z8530_sync_txdma_close
Use [z85230.c, 1346] z8530_channel_load
Use [z85230.c, 1346] z8530_channel_load
R3
Declared as: 3
Define [z8530.h, 9] z8530.h
Use [dmascc.c, 750] scc_open
Use [dmascc.c, 988] z8530_isr
Use [dmascc.c, 1370] rx_on
Use [dmascc.c, 1376] rx_off
Use [scc.c, 362] start_hunt
Use [scc.c, 475] scc_exint
Use [scc.c, 527] scc_rxint
Use [scc.c, 541] scc_rxint
Use [scc.c, 557] scc_rxint
Use [scc.c, 581] scc_spint
Use [scc.c, 675] scc_isr
Use [scc.c, 799] init_channel
Use [scc.c, 1635] scc_net_close
r3
Declared as: 3
Define [ppc_asm.tmpl, 18] ppc_asm.tmpl
R3
Declared as: 3
Define [sgiserial.h, 195] sgiserial.h
Use [sgiserial.c, 223] load_zsregs
Use [sgiserial.c, 223] load_zsregs
Use [sgiserial.c, 232] load_zsregs
Use [sgiserial.c, 232] load_zsregs
Use [sgiserial.c, 1958] rs_init
Use [sgiserial.c, 1984] rs_init
r30
Declared as: 30
Define [ppc_asm.tmpl, 45] ppc_asm.tmpl
R3000_RESET_VEC
Declared as: 0xbfc00000
Define [reset.c, 6] reset.c
Use [reset.c, 14] baget_reboot
R30_OFF
Declared as: 0xf0
Define [nmi.h, 115] nmi.h
r31
Declared as: 31
Define [ppc_asm.tmpl, 46] ppc_asm.tmpl
R31_OFF
Declared as: 0xf8
Define [nmi.h, 116] nmi.h
R3964_BCC
R3964_BREAK
R3964_CHECKSUM
R3964_DEBUG
R3964_ENABLE_SIGNALS
Declared as: 0x5301
Define [n_r3964.h, 71] n_r3964.h
R3964_ENABLE_SIGNALS
Declared as: 0x5301
Define [n_r3964.h, 71] n_r3964.h
Use [n_r3964.c, 1391] r3964_ioctl
R3964_ERROR
R3964_FRAME
R3964_MASTER
Declared as: 0
Define [n_r3964.h, 77] n_r3964.h
R3964_MASTER
Declared as: 0
Define [n_r3964.h, 77] n_r3964.h
Use [n_r3964.c, 1142] r3964_open
Use [n_r3964.c, 1394] r3964_ioctl
R3964_MAX_BLOCKS_IN_RX_QUEUE
R3964_MAX_MSG_COUNT
Declared as: 32
Define [n_r3964.h, 123] n_r3964.h
R3964_MAX_MSG_COUNT
Declared as: 32
Define [n_r3964.h, 123] n_r3964.h
Use [n_r3964.c, 982] add_msg
R3964_MAX_RETRIES
R3964_MTU
Declared as: 256
Define [n_r3964.h, 137] n_r3964.h
R3964_MTU
Declared as: 256
Define [n_r3964.h, 137] n_r3964.h
Use [n_r3964.c, 1329] r3964_write
Use [n_r3964.c, 1337] r3964_write
R3964_NO_TX_ROOM
R3964_OK
Declared as: 0
Define [n_r3964.h, 126] n_r3964.h
R3964_OK
Declared as: 0
Define [n_r3964.h, 126] n_r3964.h
Use [n_r3964.c, 645] on_receive_block
Use [n_r3964.c, 711] receive_char
R3964_OVERFLOW
Declared as: -2
Define [n_r3964.h, 128] n_r3964.h
R3964_OVERFLOW
Declared as: -2
Define [n_r3964.h, 128] n_r3964.h
Use [n_r3964.c, 1022] add_msg
Use [n_r3964.c, 1031] add_msg
R3964_OVERRUN
R3964_PARITY
R3964_READ_TELEGRAM
Declared as: 0x5304
Define [n_r3964.h, 74] n_r3964.h
R3964_READ_TELEGRAM
Declared as: 0x5304
Define [n_r3964.h, 74] n_r3964.h
Use [n_r3964.c, 1404] r3964_ioctl
R3964_SETPRIORITY
Declared as: 0x5302
Define [n_r3964.h, 72] n_r3964.h
R3964_SETPRIORITY
Declared as: 0x5302
Define [n_r3964.h, 72] n_r3964.h
Use [n_r3964.c, 1393] r3964_ioctl
R3964_SIG_ACK
Declared as: 0x0001
Define [n_r3964.h, 81] n_r3964.h
R3964_SIG_ACK
Declared as: 0x0001
Define [n_r3964.h, 81] n_r3964.h
R3964_SIG_ALL
Declared as: 0x000f
Define [n_r3964.h, 83] n_r3964.h
R3964_SIG_ALL
Declared as: 0x000f
Define [n_r3964.h, 83] n_r3964.h
Use [n_r3964.c, 885] enable_signals
R3964_SIG_DATA
Declared as: 0x0002
Define [n_r3964.h, 82] n_r3964.h
R3964_SIG_DATA
Declared as: 0x0002
Define [n_r3964.h, 82] n_r3964.h
Use [n_r3964.c, 643] on_receive_block
R3964_SIG_NONE
Declared as: 0x0000
Define [n_r3964.h, 84] n_r3964.h
R3964_SIG_NONE
Declared as: 0x0000
Define [n_r3964.h, 84] n_r3964.h
R3964_SLAVE
Declared as: 1
Define [n_r3964.h, 78] n_r3964.h
R3964_SLAVE
Declared as: 1
Define [n_r3964.h, 78] n_r3964.h
Use [n_r3964.c, 675] receive_char
Use [n_r3964.c, 1394] r3964_ioctl
R3964_TO_NO_BUF
R3964_TO_QVZ
R3964_TO_RX_PANIC
R3964_TO_ZVZ
R3964_TX_FAIL
Declared as: -1
Define [n_r3964.h, 127] n_r3964.h
R3964_TX_FAIL
Declared as: -1
Define [n_r3964.h, 127] n_r3964.h
Use [n_r3964.c, 517] retry_transmit
R3964_UNKNOWN
R3964_USE_BCC
Declared as: 0x5303
Define [n_r3964.h, 73] n_r3964.h
R3964_USE_BCC
Declared as: 0x5303
Define [n_r3964.h, 73] n_r3964.h
Use [n_r3964.c, 1398] r3964_ioctl
R3964_USE_SIGIO
Declared as: 0x1000
Define [n_r3964.h, 85] n_r3964.h
R3964_USE_SIGIO
Declared as: 0x1000
Define [n_r3964.h, 85] n_r3964.h
Use [n_r3964.c, 1038] add_msg
R3_OFF
Declared as: 0x18
Define [nmi.h, 88] nmi.h
R3_VERSION
Declared as: 1
Define [fs.c, 31] fs.c
R4
Declared as: 4
Define [macserial.h, 225] macserial.h
Use [macserial.c, 267] load_zsregs
Use [macserial.c, 267] load_zsregs
Use [macserial.c, 302] get_zsbaud
R4
Declared as: 4
Define [zs.h, 192] zs.h
Use [zs.c, 318] load_zsregs
Use [zs.c, 318] load_zsregs
r4
Declared as: (in_p(4) & 0xff)
Define [paride.h, 111] paride.h
Use [bpck.c, 70] bpck_read_regr
Use [bpck.c, 173] bpck_read_block
Use [bpck.c, 319] bpck_test_proto
Use [comm.c, 63] comm_read_regr
Use [comm.c, 129] comm_read_block
Use [dstr.c, 66] dstr_read_regr
Use [dstr.c, 139] dstr_read_block
Use [epat.c, 82] epat_read_regr
Use [epat.c, 132] epat_read_block
Use [epat.c, 133] epat_read_block
Use [epat.c, 139] epat_read_block
Use [epat.c, 140] epat_read_block
Use [epat.c, 146] epat_read_block
Use [epat.c, 147] epat_read_block
Use [epia.c, 74] epia_read_regr
Use [epia.c, 176] epia_read_block
Use [fit3.c, 85] fit3_read_regr
Use [fit3.c, 85] fit3_read_regr
Use [fit3.c, 126] fit3_read_block
Use [friq.c, 103] friq_read_block_int
Use [friq.c, 105] friq_read_block_int
Use [friq.c, 106] friq_read_block_int
Use [friq.c, 113] friq_read_block_int
Use [friq.c, 114] friq_read_block_int
Use [friq.c, 120] friq_read_block_int
Use [friq.c, 121] friq_read_block_int
Use [friq.c, 123] friq_read_block_int
Use [friq.c, 124] friq_read_block_int
Use [frpw.c, 100] frpw_read_block_int
Use [frpw.c, 106] frpw_read_block_int
Use [frpw.c, 108] frpw_read_block_int
Use [frpw.c, 109] frpw_read_block_int
Use [frpw.c, 116] frpw_read_block_int
Use [frpw.c, 117] frpw_read_block_int
Use [frpw.c, 123] frpw_read_block_int
Use [frpw.c, 124] frpw_read_block_int
Use [frpw.c, 126] frpw_read_block_int
Use [frpw.c, 127] frpw_read_block_int
Use [kbic.c, 67] kbic_read_regr
Use [kbic.c, 67] kbic_read_regr
Use [kbic.c, 173] kbic_read_block
Use [on26.c, 67] on26_read_regr
Use [on26.c, 68] on26_read_regr
Use [on26.c, 213] on26_read_block
R4
Declared as: 4
Define [zs.h, 189] zs.h
Use [zs.c, 303] load_zsregs
Use [zs.c, 303] load_zsregs
Use [zs.c, 2514] zs_init
Use [zs.c, 2557] zs_init
Use [zs.c, 2616] zs_init
R4
Declared as: 4
Define [z85230.h, 28] z85230.h
R4
Declared as: 4
Define [z8530.h, 10] z8530.h
Use [dmascc.c, 746] scc_open
Use [scc.c, 797] init_channel
r4
Declared as: 4
Define [ppc_asm.tmpl, 19] ppc_asm.tmpl
Macro [ppc_asm.h, 111] ppc_asm.h
Macro [ppc_asm.h, 111] ppc_asm.h
Macro [ppc_asm.h, 111] ppc_asm.h
Macro [ppc_asm.h, 111] ppc_asm.h
Macro [ppc_asm.h, 111] ppc_asm.h
Macro [ppc_asm.h, 111] ppc_asm.h
R4
Declared as: 4
Define [sgiserial.h, 196] sgiserial.h
Use [sgiserial.c, 221] load_zsregs
Use [sgiserial.c, 221] load_zsregs
R4030_ADDR_INTR
Declared as: (1<<10)
Define [jazzdma.h, 76] jazzdma.h
Use [jazzdma.c, 385] vdma_enable
R4030_CHNL_ENABLE
Declared as: (1<<0)
Define [jazzdma.h, 72] jazzdma.h
Use [jazzdma.c, 393] vdma_enable
Use [jazzdma.c, 422] vdma_disable
Use [jazz_esp.c, 206] dma_ports_p
R4030_CHNL_WRITE
Declared as: (1<<1)
Define [jazzdma.h, 73] jazzdma.h
Use [jazzdma.c, 481] vdma_set_mode
Use [jazzdma.c, 488] vdma_set_mode
R4030_MEM_INTR
Declared as: (1<<9)
Define [jazzdma.h, 75] jazzdma.h
Use [jazzdma.c, 385] vdma_enable
R4030_MODE_ATIME_120
Declared as: (2)
Define [jazzdma.h, 83] jazzdma.h
Use [jazzdma.c, 462] vdma_set_mode
R4030_MODE_ATIME_160
Declared as: (3)
Define [jazzdma.h, 84] jazzdma.h
R4030_MODE_ATIME_200
Declared as: (4)
Define [jazzdma.h, 85] jazzdma.h
R4030_MODE_ATIME_240
Declared as: (5)
Define [jazzdma.h, 86] jazzdma.h
R4030_MODE_ATIME_280
Declared as: (6)
Define [jazzdma.h, 87] jazzdma.h
R4030_MODE_ATIME_320
Declared as: (7)
Define [jazzdma.h, 88] jazzdma.h
R4030_MODE_ATIME_40
Declared as: (0)
Define [jazzdma.h, 81] jazzdma.h
R4030_MODE_ATIME_80
Declared as: (1)
Define [jazzdma.h, 82] jazzdma.h
Use [jazzdma.c, 453] vdma_set_mode
R4030_MODE_BURST
Declared as: (1<<6)
Define [jazzdma.h, 93] jazzdma.h
R4030_MODE_FAST_ACK
Declared as: (1<<7)
Define [jazzdma.h, 94] jazzdma.h
R4030_MODE_INTR_EN
Declared as: (1<<5)
Define [jazzdma.h, 92] jazzdma.h
Use [jazzdma.c, 451] vdma_set_mode
Use [jazzdma.c, 460] vdma_set_mode
R4030_MODE_WIDTH_16
Declared as: (2<<3)
Define [jazzdma.h, 90] jazzdma.h
Use [jazzdma.c, 452] vdma_set_mode
R4030_MODE_WIDTH_32
Declared as: (3<<3)
Define [jazzdma.h, 91] jazzdma.h
R4030_MODE_WIDTH_8
Declared as: (1<<3)
Define [jazzdma.h, 89] jazzdma.h
Use [jazzdma.c, 461] vdma_set_mode
R4030_TC_INTR
Declared as: (1<<8)
Define [jazzdma.h, 74] jazzdma.h
Use [jazzdma.c, 384] vdma_enable
R4_DEV
Declared as: ((DEV & 0xff) | ((DEV & 0xff00) << 10))
Define [fs.c, 28] fs.c
R4_MAJOR
Declared as: (((DEV) >> 18) & 0x3fff)
Define [fs.c, 29] fs.c
Use [fs.c, 270] solaris_mknod
R4_MINOR
Declared as: ((DEV) & 0x3ffff)
Define [fs.c, 30] fs.c
Use [fs.c, 271] solaris_mknod
R4_OFF
Declared as: 0x20
Define [nmi.h, 89] nmi.h
R4_VERSION
Declared as: 2
Define [fs.c, 32] fs.c
R4K_OPTS
Declared as: (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX)
Define [setup.c, 152] setup.c
Use [setup.c, 190] cpu_probe
Use [setup.c, 197] cpu_probe
Use [setup.c, 203] cpu_probe
Use [setup.c, 241] cpu_probe
Use [setup.c, 247] cpu_probe
Use [setup.c, 253] cpu_probe
Use [setup.c, 259] cpu_probe
Use [setup.c, 280] cpu_probe
r4l
Declared as: (delay_p,inl(pi->port+4)&0xffffffff)
Define [paride.h, 115] paride.h
Use [bpck.c, 187] bpck_read_block
Use [bpck.c, 323] bpck_test_proto
Use [comm.c, 139] comm_read_block
Use [dstr.c, 149] dstr_read_block
Use [epat.c, 145] epat_read_block
Use [epia.c, 188] epia_read_block
Use [friq.c, 119] friq_read_block_int
Use [frpw.c, 122] frpw_read_block_int
Use [kbic.c, 183] kbic_read_block
Use [on26.c, 227] on26_read_block
r4w
Declared as: (delay_p,inw(pi->port+4)&0xffff)
Define [paride.h, 114] paride.h
Use [bpck.c, 180] bpck_read_block
Use [bpck.c, 321] bpck_test_proto
Use [comm.c, 134] comm_read_block
Use [dstr.c, 144] dstr_read_block
Use [epat.c, 138] epat_read_block
Use [epia.c, 182] epia_read_block
Use [friq.c, 111] friq_read_block_int
Use [frpw.c, 114] frpw_read_block_int
Use [kbic.c, 178] kbic_read_block
Use [on26.c, 220] on26_read_block
R5
Declared as: 5
Define [macserial.h, 226] macserial.h
Use [macserial.c, 270] load_zsregs
Use [macserial.c, 270] load_zsregs
Use [macserial.c, 279] load_zsregs
Use [macserial.c, 279] load_zsregs
Use [macserial.c, 2770] serial_console_write
R5
Declared as: 5
Define [zs.h, 193] zs.h
Use [zs.c, 320] load_zsregs
Use [zs.c, 320] load_zsregs
Use [zs.c, 331] load_zsregs
Use [zs.c, 331] load_zsregs
R5
Declared as: 5
Define [zs.h, 190] zs.h
Use [zs.c, 305] load_zsregs
Use [zs.c, 305] load_zsregs
Use [zs.c, 315] load_zsregs
Use [zs.c, 315] load_zsregs
Use [zs.c, 2517] zs_init
Use [zs.c, 2536] zs_init
Use [zs.c, 2560] zs_init
Use [zs.c, 2580] zs_init
Use [zs.c, 2619] zs_init
Use [zs.c, 2635] zs_init
R5
Declared as: 5
Define [z85230.h, 29] z85230.h
Use [z85230.c, 313] z8530_rtsdtr
Use [z85230.c, 1429] z8530_tx_begin
Use [z85230.c, 1429] z8530_tx_begin
R5
Declared as: 5
Define [z8530.h, 11] z8530.h
Use [dmascc.c, 752] scc_open
Use [dmascc.c, 926] scc_send_packet
Use [dmascc.c, 1256] tm_isr
Use [dmascc.c, 1277] tm_isr
Use [scc.c, 800] init_channel
Use [scc.c, 932] scc_key_trx
Use [scc.c, 933] scc_key_trx
Use [scc.c, 935] scc_key_trx
Use [scc.c, 938] scc_key_trx
Use [scc.c, 966] scc_key_trx
Use [scc.c, 967] scc_key_trx
Use [scc.c, 969] scc_key_trx
Use [scc.c, 972] scc_key_trx
Use [scc.c, 1107] is_grouped
Use [scc.c, 1153] t_dwait
Use [scc.c, 1357] scc_set_param
r5
Declared as: 5
Define [ppc_asm.tmpl, 20] ppc_asm.tmpl
R5
Declared as: 5
Define [sgiserial.h, 197] sgiserial.h
Use [sgiserial.c, 224] load_zsregs
Use [sgiserial.c, 224] load_zsregs
Use [sgiserial.c, 233] load_zsregs
Use [sgiserial.c, 233] load_zsregs
Use [sgiserial.c, 1959] rs_init
Use [sgiserial.c, 1986] rs_init
r587_BIO
r587_IDR
r587_MSR
r587_PCR
r587_SER
R5_HASH
Declared as: 3
Define [reiserfs_fs_sb.h, 21] reiserfs_fs_sb.h
Macro [reiserfs_fs_sb.h, 22] reiserfs_fs_sb.h
R5_HASH
Declared as: 3
Define [reiserfs_fs_sb.h, 21] reiserfs_fs_sb.h
Macro [reiserfs_fs_sb.h, 22] reiserfs_fs_sb.h
R5_OFF
Declared as: 0x28
Define [nmi.h, 90] nmi.h
R6
Declared as: 6
Define [macserial.h, 227] macserial.h
R6
Declared as: 6
Define [zs.h, 194] zs.h
R6
Declared as: 6
Define [zs.h, 191] zs.h
R6
Declared as: 6
Define [z85230.h, 30] z85230.h
Use [z85230.c, 517] z8530_dma_rx
R6
Declared as: 6
Define [z8530.h, 12] z8530.h
Use [dmascc.c, 754] scc_open
Use [scc.c, 801] init_channel
Use [scc.c, 1424] scc_stop_calibrate
Use [scc.c, 1453] scc_start_calibrate
r6
Declared as: 6
Define [ppc_asm.tmpl, 21] ppc_asm.tmpl
R6
Declared as: 6
Define [sgiserial.h, 198] sgiserial.h
R647
Declared as: 1
Define [gazel.c, 24] gazel.c
Use [gazel.c, 118] ReadISAC
Use [gazel.c, 135] WriteISAC
Use [gazel.c, 151] ReadISACfifo
Use [gazel.c, 166] WriteISACfifo
Use [gazel.c, 181] ReadHSCXfifo
Use [gazel.c, 196] WriteHSCXfifo
Use [gazel.c, 213] ReadHSCX
Use [gazel.c, 230] WriteHSCX
Use [gazel.c, 333] release_io_gazel
Use [gazel.c, 362] reset_gazel
Use [gazel.c, 424] Gazel_card_msg
Use [gazel.c, 444] reserve_regions
Use [gazel.c, 505] setup_gazelisa
Use [gazel.c, 518] setup_gazelisa
Use [gazel.c, 674] setup_gazel
R64CNT
R685
Declared as: 2
Define [gazel.c, 25] gazel.c
Use [gazel.c, 120] ReadISAC
Use [gazel.c, 137] WriteISAC
Use [gazel.c, 152] ReadISACfifo
Use [gazel.c, 167] WriteISACfifo
Use [gazel.c, 182] ReadHSCXfifo
Use [gazel.c, 197] WriteHSCXfifo
Use [gazel.c, 215] ReadHSCX
Use [gazel.c, 232] WriteHSCX
Use [gazel.c, 339] release_io_gazel
Use [gazel.c, 371] reset_gazel
Use [gazel.c, 424] Gazel_card_msg
Use [gazel.c, 459] reserve_regions
Use [gazel.c, 606] setup_gazelpci
Use [gazel.c, 675] setup_gazel
R6_OFF
Declared as: 0x30
Define [nmi.h, 91] nmi.h
R7
Declared as: 7
Define [macserial.h, 228] macserial.h
R7
Declared as: 7
Define [zs.h, 195] zs.h
R7
Declared as: 7
Define [zs.h, 192] zs.h
R7
Declared as: 7
Define [z85230.h, 31] z85230.h
Use [z85230.c, 516] z8530_dma_rx
R7
Declared as: 7
Define [z8530.h, 13] z8530.h
Use [dmascc.c, 756] scc_open
Use [dmascc.c, 762] scc_open
Use [dmascc.c, 788] scc_open
Use [dmascc.c, 789] scc_open
Use [dmascc.c, 791] scc_open
Use [scc.c, 802] init_channel
Use [scc.c, 858] init_channel
Use [scc.c, 1425] scc_stop_calibrate
Use [scc.c, 1454] scc_start_calibrate
r7
Declared as: 7
Define [ppc_asm.tmpl, 22] ppc_asm.tmpl
r7
Declared as: (in_p(7) & 0xff)
Define [fit3.c, 34] fit3.c
R7
Declared as: 7
Define [sgiserial.h, 199] sgiserial.h
R742
Declared as: 4
Define [gazel.c, 27] gazel.c
Use [gazel.c, 123] ReadISAC
Use [gazel.c, 141] WriteISAC
Use [gazel.c, 156] ReadISACfifo
Use [gazel.c, 171] WriteISACfifo
Use [gazel.c, 186] ReadHSCXfifo
Use [gazel.c, 201] WriteHSCXfifo
Use [gazel.c, 218] ReadHSCX
Use [gazel.c, 236] WriteHSCX
Use [gazel.c, 349] release_io_gazel
Use [gazel.c, 398] reset_gazel
Use [gazel.c, 479] reserve_regions
Use [gazel.c, 503] setup_gazelisa
Use [gazel.c, 529] setup_gazelisa
Use [gazel.c, 685] setup_gazel
R753
Declared as: 3
Define [gazel.c, 26] gazel.c
Use [gazel.c, 122] ReadISAC
Use [gazel.c, 140] WriteISAC
Use [gazel.c, 155] ReadISACfifo
Use [gazel.c, 170] WriteISACfifo
Use [gazel.c, 185] ReadHSCXfifo
Use [gazel.c, 200] WriteHSCXfifo
Use [gazel.c, 217] ReadHSCX
Use [gazel.c, 235] WriteHSCX
Use [gazel.c, 344] release_io_gazel
Use [gazel.c, 381] reset_gazel
Use [gazel.c, 469] reserve_regions
Use [gazel.c, 618] setup_gazelpci
Use [gazel.c, 686] setup_gazel
R7_OFF
Declared as: 0x38
Define [nmi.h, 92] nmi.h
R8
Declared as: 8
Define [macserial.h, 229] macserial.h
R8
Declared as: 8
Define [zs.h, 196] zs.h
R8
Declared as: 8
Define [zs.h, 193] zs.h
R8
Declared as: 8
Define [z85230.h, 32] z85230.h
Use [z85230.c, 419] z8530_tx
Use [z85230.c, 1265] z8530_init
Use [z85230.c, 1442] z8530_tx_begin
R8
Declared as: 8
Define [z8530.h, 14] z8530.h
r8
Declared as: 8
Define [ppc_asm.tmpl, 23] ppc_asm.tmpl
R8
Declared as: 8
Define [sgiserial.h, 200] sgiserial.h
R8_OFF
Declared as: 0x40
Define [nmi.h, 93] nmi.h
R9
Declared as: 9
Define [macserial.h, 230] macserial.h
Use [macserial.c, 272] load_zsregs
Use [macserial.c, 272] load_zsregs
Use [macserial.c, 2639] macserial_init
Use [macserial.c, 2854] serial_console_setup
R9
Declared as: 9
Define [zs.h, 197] zs.h
Use [zs.c, 321] load_zsregs
Use [zs.c, 321] load_zsregs
R9
Declared as: 9
Define [zs.h, 194] zs.h
Use [zs.c, 299] load_zsregs
Use [zs.c, 301] load_zsregs
Use [zs.c, 306] load_zsregs
Use [zs.c, 306] load_zsregs
Use [zs.c, 320] load_zsregs
Use [zs.c, 320] load_zsregs
Use [zs.c, 371] kgdb_chaninit
Use [zs.c, 374] kgdb_chaninit
Use [zs.c, 2504] zs_init
Use [zs.c, 2518] zs_init
Use [zs.c, 2548] zs_init
Use [zs.c, 2561] zs_init
Use [zs.c, 2591] zs_init
Use [zs.c, 2620] zs_init
Use [zs.c, 2637] zs_init
R9
Declared as: 9
Define [z85230.h, 33] z85230.h
Use [z85230.c, 1238] z8530_init
Use [z85230.c, 1307] z8530_shutdown
R9
Declared as: 9
Define [z8530.h, 15] z8530.h
Use [dmascc.c, 492] setup_adapter
Use [dmascc.c, 744] scc_open
Use [dmascc.c, 863] scc_close
Use [scc.c, 803] init_channel
Use [scc.c, 878] init_channel
Use [scc.c, 1517] z8530_init
Use [scc.c, 1520] z8530_init
Use [scc.c, 1793] scc_net_ioctl
Use [scc.c, 2149] scc_cleanup_driver
r9
Declared as: 9
Define [ppc_asm.tmpl, 24] ppc_asm.tmpl
R9
Declared as: 9
Define [sgiserial.h, 201] sgiserial.h
Use [sgiserial.c, 226] load_zsregs
Use [sgiserial.c, 226] load_zsregs
Use [sgiserial.c, 258] kgdb_chaninit
Use [sgiserial.c, 261] kgdb_chaninit
Use [sgiserial.c, 1956] rs_init
Use [sgiserial.c, 1980] rs_init
R9_OFF
Declared as: 0x48
Define [nmi.h, 94] nmi.h
R_386_32
Declared as: 1
Define [elf.h, 198] elf.h
R_386_32
Declared as: 1
Define [elf.h, 193] elf.h
R_386_COPY
Declared as: 5
Define [elf.h, 202] elf.h
R_386_COPY
Declared as: 5
Define [elf.h, 197] elf.h
R_386_GLOB_DAT
Declared as: 6
Define [elf.h, 203] elf.h
R_386_GLOB_DAT
Declared as: 6
Define [elf.h, 198] elf.h
R_386_GOT32
Declared as: 3
Define [elf.h, 200] elf.h
R_386_GOT32
Declared as: 3
Define [elf.h, 195] elf.h
R_386_GOTOFF
Declared as: 9
Define [elf.h, 206] elf.h
R_386_GOTOFF
Declared as: 9
Define [elf.h, 201] elf.h
R_386_GOTPC
Declared as: 10
Define [elf.h, 207] elf.h
R_386_GOTPC
Declared as: 10
Define [elf.h, 202] elf.h
R_386_JMP_SLOT
Declared as: 7
Define [elf.h, 204] elf.h
R_386_JMP_SLOT
Declared as: 7
Define [elf.h, 199] elf.h
R_386_NONE
Declared as: 0
Define [elf.h, 197] elf.h
R_386_NONE
Declared as: 0
Define [elf.h, 192] elf.h
R_386_NUM
Declared as: 11
Define [elf.h, 208] elf.h
R_386_NUM
Declared as: 11
Define [elf.h, 203] elf.h
R_386_PC32
Declared as: 2
Define [elf.h, 199] elf.h
R_386_PC32
Declared as: 2
Define [elf.h, 194] elf.h
R_386_PLT32
Declared as: 4
Define [elf.h, 201] elf.h
R_386_PLT32
Declared as: 4
Define [elf.h, 196] elf.h
R_386_RELATIVE
Declared as: 8
Define [elf.h, 205] elf.h
R_386_RELATIVE
Declared as: 8
Define [elf.h, 200] elf.h
R_68K_16
Declared as: 2
Define [elf.h, 314] elf.h
R_68K_16
Declared as: 2
Define [elf.h, 309] elf.h
R_68K_32
Declared as: 1
Define [elf.h, 313] elf.h
R_68K_32
Declared as: 1
Define [elf.h, 308] elf.h
R_68K_8
Declared as: 3
Define [elf.h, 315] elf.h
R_68K_8
Declared as: 3
Define [elf.h, 310] elf.h
R_68K_COPY
Declared as: 19
Define [elf.h, 331] elf.h
R_68K_COPY
Declared as: 19
Define [elf.h, 326] elf.h
R_68K_GLOB_DAT
Declared as: 20
Define [elf.h, 332] elf.h
R_68K_GLOB_DAT
Declared as: 20
Define [elf.h, 327] elf.h
R_68K_GOT16
Declared as: 8
Define [elf.h, 320] elf.h
R_68K_GOT16
Declared as: 8
Define [elf.h, 315] elf.h
R_68K_GOT16O
Declared as: 11
Define [elf.h, 323] elf.h
R_68K_GOT16O
Declared as: 11
Define [elf.h, 318] elf.h
R_68K_GOT32
Declared as: 7
Define [elf.h, 319] elf.h
R_68K_GOT32
Declared as: 7
Define [elf.h, 314] elf.h
R_68K_GOT32O
Declared as: 10
Define [elf.h, 322] elf.h
R_68K_GOT32O
Declared as: 10
Define [elf.h, 317] elf.h
R_68K_GOT8
Declared as: 9
Define [elf.h, 321] elf.h
R_68K_GOT8
Declared as: 9
Define [elf.h, 316] elf.h
R_68K_GOT8O
Declared as: 12
Define [elf.h, 324] elf.h
R_68K_GOT8O
Declared as: 12
Define [elf.h, 319] elf.h
R_68K_JMP_SLOT
Declared as: 21
Define [elf.h, 333] elf.h
R_68K_JMP_SLOT
Declared as: 21
Define [elf.h, 328] elf.h
R_68K_NONE
Declared as: 0
Define [elf.h, 312] elf.h
R_68K_NONE
Declared as: 0
Define [elf.h, 307] elf.h
R_68K_PC16
Declared as: 5
Define [elf.h, 317] elf.h
R_68K_PC16
Declared as: 5
Define [elf.h, 312] elf.h
R_68K_PC32
Declared as: 4
Define [elf.h, 316] elf.h
R_68K_PC32
Declared as: 4
Define [elf.h, 311] elf.h
R_68K_PC8
Declared as: 6
Define [elf.h, 318] elf.h
R_68K_PC8
Declared as: 6
Define [elf.h, 313] elf.h
R_68K_PLT16
Declared as: 14
Define [elf.h, 326] elf.h
R_68K_PLT16
Declared as: 14
Define [elf.h, 321] elf.h
R_68K_PLT16O
Declared as: 17
Define [elf.h, 329] elf.h
R_68K_PLT16O
Declared as: 17
Define [elf.h, 324] elf.h
R_68K_PLT32
Declared as: 13
Define [elf.h, 325] elf.h
R_68K_PLT32
Declared as: 13
Define [elf.h, 320] elf.h
R_68K_PLT32O
Declared as: 16
Define [elf.h, 328] elf.h
R_68K_PLT32O
Declared as: 16
Define [elf.h, 323] elf.h
R_68K_PLT8
Declared as: 15
Define [elf.h, 327] elf.h
R_68K_PLT8
Declared as: 15
Define [elf.h, 322] elf.h
R_68K_PLT8O
Declared as: 18
Define [elf.h, 330] elf.h
R_68K_PLT8O
Declared as: 18
Define [elf.h, 325] elf.h
R_68K_RELATIVE
Declared as: 22
Define [elf.h, 334] elf.h
R_68K_RELATIVE
Declared as: 22
Define [elf.h, 329] elf.h
R_A_TOV
Declared as: 0
Define [cpqfcTSstructs.h, 1069] cpqfcTSstructs.h
R_ALPHA_BRADDR
Declared as: 7
Define [elf.h, 346] elf.h
R_ALPHA_BRADDR
Declared as: 7
Define [elf.h, 341] elf.h
R_ALPHA_COPY
Declared as: 24
Define [elf.h, 363] elf.h
R_ALPHA_COPY
Declared as: 24
Define [elf.h, 358] elf.h
R_ALPHA_GLOB_DAT
Declared as: 25
Define [elf.h, 364] elf.h
R_ALPHA_GLOB_DAT
Declared as: 25
Define [elf.h, 359] elf.h
R_ALPHA_GPDISP
Declared as: 6
Define [elf.h, 345] elf.h
R_ALPHA_GPDISP
Declared as: 6
Define [elf.h, 340] elf.h
R_ALPHA_GPREL32
Declared as: 3
Define [elf.h, 342] elf.h
R_ALPHA_GPREL32
Declared as: 3
Define [elf.h, 337] elf.h
R_ALPHA_GPRELHIGH
Declared as: 17
Define [elf.h, 356] elf.h
R_ALPHA_GPRELHIGH
Declared as: 17
Define [elf.h, 351] elf.h
R_ALPHA_GPRELLOW
Declared as: 18
Define [elf.h, 357] elf.h
R_ALPHA_GPRELLOW
Declared as: 18
Define [elf.h, 352] elf.h
R_ALPHA_GPVALUE
Declared as: 16
Define [elf.h, 355] elf.h
R_ALPHA_GPVALUE
Declared as: 16
Define [elf.h, 350] elf.h
R_ALPHA_HINT
Declared as: 8
Define [elf.h, 347] elf.h
R_ALPHA_HINT
Declared as: 8
Define [elf.h, 342] elf.h
R_ALPHA_IMMED_BR_HI32
Declared as: 22
Define [elf.h, 361] elf.h
R_ALPHA_IMMED_BR_HI32
Declared as: 22
Define [elf.h, 356] elf.h
R_ALPHA_IMMED_GP_16
Declared as: 19
Define [elf.h, 358] elf.h
R_ALPHA_IMMED_GP_16
Declared as: 19
Define [elf.h, 353] elf.h
R_ALPHA_IMMED_GP_HI32
Declared as: 20
Define [elf.h, 359] elf.h
R_ALPHA_IMMED_GP_HI32
Declared as: 20
Define [elf.h, 354] elf.h
R_ALPHA_IMMED_LO32
Declared as: 23
Define [elf.h, 362] elf.h
R_ALPHA_IMMED_LO32
Declared as: 23
Define [elf.h, 357] elf.h
R_ALPHA_IMMED_SCN_HI32
Declared as: 21
Define [elf.h, 360] elf.h
R_ALPHA_IMMED_SCN_HI32
Declared as: 21
Define [elf.h, 355] elf.h
R_ALPHA_JMP_SLOT
Declared as: 26
Define [elf.h, 365] elf.h
R_ALPHA_JMP_SLOT
Declared as: 26
Define [elf.h, 360] elf.h
R_ALPHA_LITERAL
Declared as: 4
Define [elf.h, 343] elf.h
R_ALPHA_LITERAL
Declared as: 4
Define [elf.h, 338] elf.h
R_ALPHA_LITUSE
Declared as: 5
Define [elf.h, 344] elf.h
R_ALPHA_LITUSE
Declared as: 5
Define [elf.h, 339] elf.h
R_ALPHA_NONE
Declared as: 0
Define [elf.h, 339] elf.h
R_ALPHA_NONE
Declared as: 0
Define [elf.h, 334] elf.h
R_ALPHA_OP_PRSHIFT
Declared as: 15
Define [elf.h, 354] elf.h
R_ALPHA_OP_PRSHIFT
Declared as: 15
Define [elf.h, 349] elf.h
R_ALPHA_OP_PSUB
Declared as: 14
Define [elf.h, 353] elf.h
R_ALPHA_OP_PSUB
Declared as: 14
Define [elf.h, 348] elf.h
R_ALPHA_OP_PUSH
Declared as: 12
Define [elf.h, 351] elf.h
R_ALPHA_OP_PUSH
Declared as: 12
Define [elf.h, 346] elf.h
R_ALPHA_OP_STORE
Declared as: 13
Define [elf.h, 352] elf.h
R_ALPHA_OP_STORE
Declared as: 13
Define [elf.h, 347] elf.h
R_ALPHA_REFLONG
Declared as: 1
Define [elf.h, 340] elf.h
R_ALPHA_REFLONG
Declared as: 1
Define [elf.h, 335] elf.h
R_ALPHA_REFQUAD
Declared as: 2
Define [elf.h, 341] elf.h
R_ALPHA_REFQUAD
Declared as: 2
Define [elf.h, 336] elf.h
R_ALPHA_RELATIVE
Declared as: 27
Define [elf.h, 366] elf.h
R_ALPHA_RELATIVE
Declared as: 27
Define [elf.h, 361] elf.h
R_ALPHA_SREL16
Declared as: 9
Define [elf.h, 348] elf.h
R_ALPHA_SREL16
Declared as: 9
Define [elf.h, 343] elf.h
R_ALPHA_SREL32
Declared as: 10
Define [elf.h, 349] elf.h
R_ALPHA_SREL32
Declared as: 10
Define [elf.h, 344] elf.h
R_ALPHA_SREL64
Declared as: 11
Define [elf.h, 350] elf.h
R_ALPHA_SREL64
Declared as: 11
Define [elf.h, 345] elf.h
R_ALT_SER_BAUDRATE
Declared as: (IO_TYPECAST_UDWORD 0xb000005c)
Define [sv_addr.agh, 2257] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_rec__BITNR
Declared as: 0
Define [sv_addr.agh, 2300] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_rec__extern
Declared as: 2
Define [sv_addr.agh, 2304] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_rec__normal
Declared as: 0
Define [sv_addr.agh, 2302] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_rec__prescale
Declared as: 1
Define [sv_addr.agh, 2303] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_rec__timer
Declared as: 3
Define [sv_addr.agh, 2305] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_rec__WIDTH
Declared as: 2
Define [sv_addr.agh, 2301] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_tr__BITNR
Declared as: 4
Define [sv_addr.agh, 2294] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_tr__extern
Declared as: 2
Define [sv_addr.agh, 2298] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_tr__normal
Declared as: 0
Define [sv_addr.agh, 2296] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_tr__prescale
Declared as: 1
Define [sv_addr.agh, 2297] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_tr__timer
Declared as: 3
Define [sv_addr.agh, 2299] sv_addr.agh
R_ALT_SER_BAUDRATE__ser0_tr__WIDTH
Declared as: 2
Define [sv_addr.agh, 2295] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_rec__BITNR
Declared as: 8
Define [sv_addr.agh, 2288] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_rec__extern
Declared as: 2
Define [sv_addr.agh, 2292] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_rec__normal
Declared as: 0
Define [sv_addr.agh, 2290] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_rec__prescale
Declared as: 1
Define [sv_addr.agh, 2291] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_rec__timer
Declared as: 3
Define [sv_addr.agh, 2293] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_rec__WIDTH
Declared as: 2
Define [sv_addr.agh, 2289] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_tr__BITNR
Declared as: 12
Define [sv_addr.agh, 2282] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_tr__extern
Declared as: 2
Define [sv_addr.agh, 2286] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_tr__normal
Declared as: 0
Define [sv_addr.agh, 2284] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_tr__prescale
Declared as: 1
Define [sv_addr.agh, 2285] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_tr__timer
Declared as: 3
Define [sv_addr.agh, 2287] sv_addr.agh
R_ALT_SER_BAUDRATE__ser1_tr__WIDTH
Declared as: 2
Define [sv_addr.agh, 2283] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_rec__BITNR
Declared as: 16
Define [sv_addr.agh, 2276] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_rec__extern
Declared as: 2
Define [sv_addr.agh, 2280] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_rec__normal
Declared as: 0
Define [sv_addr.agh, 2278] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_rec__prescale
Declared as: 1
Define [sv_addr.agh, 2279] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_rec__timer
Declared as: 3
Define [sv_addr.agh, 2281] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_rec__WIDTH
Declared as: 2
Define [sv_addr.agh, 2277] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_tr__BITNR
Declared as: 20
Define [sv_addr.agh, 2270] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_tr__extern
Declared as: 2
Define [sv_addr.agh, 2274] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_tr__normal
Declared as: 0
Define [sv_addr.agh, 2272] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_tr__prescale
Declared as: 1
Define [sv_addr.agh, 2273] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_tr__timer
Declared as: 3
Define [sv_addr.agh, 2275] sv_addr.agh
R_ALT_SER_BAUDRATE__ser2_tr__WIDTH
Declared as: 2
Define [sv_addr.agh, 2271] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_rec__BITNR
Declared as: 24
Define [sv_addr.agh, 2264] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_rec__extern
Declared as: 2
Define [sv_addr.agh, 2268] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_rec__normal
Declared as: 0
Define [sv_addr.agh, 2266] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_rec__prescale
Declared as: 1
Define [sv_addr.agh, 2267] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_rec__timer
Declared as: 3
Define [sv_addr.agh, 2269] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_rec__WIDTH
Declared as: 2
Define [sv_addr.agh, 2265] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_tr__BITNR
Declared as: 28
Define [sv_addr.agh, 2258] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_tr__extern
Declared as: 2
Define [sv_addr.agh, 2262] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_tr__normal
Declared as: 0
Define [sv_addr.agh, 2260] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_tr__prescale
Declared as: 1
Define [sv_addr.agh, 2261] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_tr__timer
Declared as: 3
Define [sv_addr.agh, 2263] sv_addr.agh
R_ALT_SER_BAUDRATE__ser3_tr__WIDTH
Declared as: 2
Define [sv_addr.agh, 2259] sv_addr.agh
R_ATA_CONFIG
Declared as: (IO_TYPECAST_UDWORD 0xb0000044)
Define [sv_addr.agh, 3063] sv_addr.agh
Use [ide.c, 222] tune_e100_ide
Use [ide.c, 230] tune_e100_ide
Use [ide.c, 238] tune_e100_ide
Use [ide.c, 246] tune_e100_ide
Use [ide.c, 254] tune_e100_ide
Use [ide.c, 299] init_e100_ide
Use [ide.c, 337] init_e100_ide
R_ATA_CONFIG__dma_hold__BITNR
Declared as: 15
Define [sv_addr.agh, 3070] sv_addr.agh
Macro [ide.c, 224] tune_e100_ide
Macro [ide.c, 232] tune_e100_ide
Macro [ide.c, 240] tune_e100_ide
Macro [ide.c, 248] tune_e100_ide
Macro [ide.c, 256] tune_e100_ide
Macro [ide.c, 339] init_e100_ide
R_ATA_CONFIG__dma_hold__WIDTH
Declared as: 5
Define [sv_addr.agh, 3071] sv_addr.agh
R_ATA_CONFIG__dma_strobe__BITNR
Declared as: 20
Define [sv_addr.agh, 3068] sv_addr.agh
Macro [ide.c, 223] tune_e100_ide
Macro [ide.c, 231] tune_e100_ide
Macro [ide.c, 239] tune_e100_ide
Macro [ide.c, 247] tune_e100_ide
Macro [ide.c, 255] tune_e100_ide
Macro [ide.c, 338] init_e100_ide
R_ATA_CONFIG__dma_strobe__WIDTH
Declared as: 5
Define [sv_addr.agh, 3069] sv_addr.agh
R_ATA_CONFIG__enable__BITNR
Declared as: 25
Define [sv_addr.agh, 3064] sv_addr.agh
Macro [ide.c, 222] tune_e100_ide
Macro [ide.c, 230] tune_e100_ide
Macro [ide.c, 238] tune_e100_ide
Macro [ide.c, 246] tune_e100_ide
Macro [ide.c, 254] tune_e100_ide
Macro [ide.c, 337] init_e100_ide
R_ATA_CONFIG__enable__off
Declared as: 0
Define [sv_addr.agh, 3067] sv_addr.agh
R_ATA_CONFIG__enable__on
Declared as: 1
Define [sv_addr.agh, 3066] sv_addr.agh
R_ATA_CONFIG__enable__WIDTH
Declared as: 1
Define [sv_addr.agh, 3065] sv_addr.agh
R_ATA_CONFIG__pio_hold__BITNR
Declared as: 0
Define [sv_addr.agh, 3076] sv_addr.agh
Macro [ide.c, 227] tune_e100_ide
Macro [ide.c, 235] tune_e100_ide
Macro [ide.c, 243] tune_e100_ide
Macro [ide.c, 251] tune_e100_ide
Macro [ide.c, 259] tune_e100_ide
Macro [ide.c, 342] init_e100_ide
R_ATA_CONFIG__pio_hold__WIDTH
Declared as: 5
Define [sv_addr.agh, 3077] sv_addr.agh
R_ATA_CONFIG__pio_setup__BITNR
Declared as: 10
Define [sv_addr.agh, 3072] sv_addr.agh
Macro [ide.c, 225] tune_e100_ide
Macro [ide.c, 233] tune_e100_ide
Macro [ide.c, 241] tune_e100_ide
Macro [ide.c, 249] tune_e100_ide
Macro [ide.c, 257] tune_e100_ide
Macro [ide.c, 340] init_e100_ide
R_ATA_CONFIG__pio_setup__WIDTH
Declared as: 5
Define [sv_addr.agh, 3073] sv_addr.agh
R_ATA_CONFIG__pio_strobe__BITNR
Declared as: 5
Define [sv_addr.agh, 3074] sv_addr.agh
Macro [ide.c, 226] tune_e100_ide
Macro [ide.c, 234] tune_e100_ide
Macro [ide.c, 242] tune_e100_ide
Macro [ide.c, 250] tune_e100_ide
Macro [ide.c, 258] tune_e100_ide
Macro [ide.c, 341] init_e100_ide
R_ATA_CONFIG__pio_strobe__WIDTH
Declared as: 5
Define [sv_addr.agh, 3075] sv_addr.agh
R_ATA_CTRL_DATA
Declared as: (IO_TYPECAST_UDWORD 0xb0000040)
Define [sv_addr.agh, 3011] sv_addr.agh
Use [ide.c, 126] outb_p
Use [ide.c, 134] byte
Use [ide.c, 297] init_e100_ide
Use [ide.c, 344] init_e100_ide
Use [ide.c, 409] e100_atapi_input_bytes
Use [ide.c, 488] e100_atapi_output_bytes
Use [ide.c, 835] e100_dmaproc
Use [ide.c, 878] e100_dmaproc
R_ATA_CTRL_DATA__addr__BITNR
Declared as: 25
Define [sv_addr.agh, 3022] sv_addr.agh
Macro [ide.c, 345] init_e100_ide
R_ATA_CTRL_DATA__addr__WIDTH
Declared as: 3
Define [sv_addr.agh, 3023] sv_addr.agh
R_ATA_CTRL_DATA__cs0__active
Declared as: 1
Define [sv_addr.agh, 3020] sv_addr.agh
R_ATA_CTRL_DATA__cs0__BITNR
Declared as: 28
Define [sv_addr.agh, 3018] sv_addr.agh
R_ATA_CTRL_DATA__cs0__inactive
Declared as: 0
Define [sv_addr.agh, 3021] sv_addr.agh
R_ATA_CTRL_DATA__cs0__WIDTH
Declared as: 1
Define [sv_addr.agh, 3019] sv_addr.agh
R_ATA_CTRL_DATA__cs1__active
Declared as: 1
Define [sv_addr.agh, 3016] sv_addr.agh
R_ATA_CTRL_DATA__cs1__BITNR
Declared as: 29
Define [sv_addr.agh, 3014] sv_addr.agh
R_ATA_CTRL_DATA__cs1__inactive
Declared as: 0
Define [sv_addr.agh, 3017] sv_addr.agh
R_ATA_CTRL_DATA__cs1__WIDTH
Declared as: 1
Define [sv_addr.agh, 3015] sv_addr.agh
R_ATA_CTRL_DATA__data__BITNR
Declared as: 0
Define [sv_addr.agh, 3044] sv_addr.agh
Macro [ide.c, 836] e100_dmaproc
Macro [ide.c, 879] e100_dmaproc
R_ATA_CTRL_DATA__data__WIDTH
Declared as: 16
Define [sv_addr.agh, 3045] sv_addr.agh
R_ATA_CTRL_DATA__dma_size__BITNR
Declared as: 20
Define [sv_addr.agh, 3040] sv_addr.agh
Macro [ide.c, 414] e100_atapi_input_bytes
Macro [ide.c, 493] e100_atapi_output_bytes
Macro [ide.c, 841] e100_dmaproc
Macro [ide.c, 884] e100_dmaproc
R_ATA_CTRL_DATA__dma_size__byte
Declared as: 1
Define [sv_addr.agh, 3042] sv_addr.agh
R_ATA_CTRL_DATA__dma_size__WIDTH
Declared as: 1
Define [sv_addr.agh, 3041] sv_addr.agh
R_ATA_CTRL_DATA__dma_size__word
Declared as: 0
Define [sv_addr.agh, 3043] sv_addr.agh
Macro [ide.c, 414] e100_atapi_input_bytes
Macro [ide.c, 493] e100_atapi_output_bytes
Macro [ide.c, 841] e100_dmaproc
Macro [ide.c, 884] e100_dmaproc
R_ATA_CTRL_DATA__handsh__BITNR
Declared as: 22
Define [sv_addr.agh, 3032] sv_addr.agh
Macro [ide.c, 412] e100_atapi_input_bytes
Macro [ide.c, 491] e100_atapi_output_bytes
Macro [ide.c, 839] e100_dmaproc
Macro [ide.c, 882] e100_dmaproc
R_ATA_CTRL_DATA__handsh__dma
Declared as: 1
Define [sv_addr.agh, 3034] sv_addr.agh
Macro [ide.c, 839] e100_dmaproc
Macro [ide.c, 882] e100_dmaproc
R_ATA_CTRL_DATA__handsh__pio
Declared as: 0
Define [sv_addr.agh, 3035] sv_addr.agh
Macro [ide.c, 412] e100_atapi_input_bytes
Macro [ide.c, 491] e100_atapi_output_bytes
R_ATA_CTRL_DATA__handsh__WIDTH
Declared as: 1
Define [sv_addr.agh, 3033] sv_addr.agh
R_ATA_CTRL_DATA__multi__BITNR
Declared as: 21
Define [sv_addr.agh, 3036] sv_addr.agh
Macro [ide.c, 413] e100_atapi_input_bytes
Macro [ide.c, 492] e100_atapi_output_bytes
Macro [ide.c, 840] e100_dmaproc
Macro [ide.c, 883] e100_dmaproc
R_ATA_CTRL_DATA__multi__off
Declared as: 0
Define [sv_addr.agh, 3039] sv_addr.agh
R_ATA_CTRL_DATA__multi__on
Declared as: 1
Define [sv_addr.agh, 3038] sv_addr.agh
Macro [ide.c, 413] e100_atapi_input_bytes
Macro [ide.c, 492] e100_atapi_output_bytes
Macro [ide.c, 840] e100_dmaproc
Macro [ide.c, 883] e100_dmaproc
R_ATA_CTRL_DATA__multi__WIDTH
Declared as: 1
Define [sv_addr.agh, 3037] sv_addr.agh
R_ATA_CTRL_DATA__rw__BITNR
Declared as: 24
Define [sv_addr.agh, 3024] sv_addr.agh
Macro [ide.c, 134] byte
Macro [ide.c, 344] init_e100_ide
Macro [ide.c, 410] e100_atapi_input_bytes
Macro [ide.c, 489] e100_atapi_output_bytes
Macro [ide.c, 837] e100_dmaproc
Macro [ide.c, 880] e100_dmaproc
R_ATA_CTRL_DATA__rw__read
Declared as: 1
Define [sv_addr.agh, 3026] sv_addr.agh
Macro [ide.c, 134] byte
Macro [ide.c, 344] init_e100_ide
Macro [ide.c, 410] e100_atapi_input_bytes
Macro [ide.c, 837] e100_dmaproc
R_ATA_CTRL_DATA__rw__WIDTH
Declared as: 1
Define [sv_addr.agh, 3025] sv_addr.agh
R_ATA_CTRL_DATA__rw__write
Declared as: 0
Define [sv_addr.agh, 3027] sv_addr.agh
Macro [ide.c, 489] e100_atapi_output_bytes
Macro [ide.c, 880] e100_dmaproc
R_ATA_CTRL_DATA__sel__BITNR
Declared as: 30
Define [sv_addr.agh, 3012] sv_addr.agh
R_ATA_CTRL_DATA__sel__WIDTH
Declared as: 2
Define [sv_addr.agh, 3013] sv_addr.agh
R_ATA_CTRL_DATA__src_dst__BITNR
Declared as: 23
Define [sv_addr.agh, 3028] sv_addr.agh
Macro [ide.c, 411] e100_atapi_input_bytes
Macro [ide.c, 490] e100_atapi_output_bytes
Macro [ide.c, 838] e100_dmaproc
Macro [ide.c, 881] e100_dmaproc
R_ATA_CTRL_DATA__src_dst__dma
Declared as: 1
Define [sv_addr.agh, 3030] sv_addr.agh
Macro [ide.c, 411] e100_atapi_input_bytes
Macro [ide.c, 490] e100_atapi_output_bytes
Macro [ide.c, 838] e100_dmaproc
Macro [ide.c, 881] e100_dmaproc
R_ATA_CTRL_DATA__src_dst__register
Declared as: 0
Define [sv_addr.agh, 3031] sv_addr.agh
R_ATA_CTRL_DATA__src_dst__WIDTH
Declared as: 1
Define [sv_addr.agh, 3029] sv_addr.agh
R_ATA_STATUS_DATA
Declared as: (IO_TYPECAST_RO_UDWORD 0xb0000040)
Define [sv_addr.agh, 3047] sv_addr.agh
Use [ide.c, 125] outb_p
Use [ide.c, 127] outb_p
Use [ide.c, 133] byte
Use [ide.c, 135] byte
Use [ide.c, 335] init_e100_ide
Use [ide.c, 347] init_e100_ide
R_ATA_STATUS_DATA__busy__BITNR
Declared as: 18
Define [sv_addr.agh, 3048] sv_addr.agh
Macro [ide.c, 125] outb_p
Macro [ide.c, 133] byte
Macro [ide.c, 347] init_e100_ide
R_ATA_STATUS_DATA__busy__no
Declared as: 0
Define [sv_addr.agh, 3051] sv_addr.agh
R_ATA_STATUS_DATA__busy__WIDTH
Declared as: 1
Define [sv_addr.agh, 3049] sv_addr.agh
Macro [ide.c, 125] outb_p
Macro [ide.c, 133] byte
Macro [ide.c, 347] init_e100_ide
R_ATA_STATUS_DATA__busy__yes
Declared as: 1
Define [sv_addr.agh, 3050] sv_addr.agh
R_ATA_STATUS_DATA__data__BITNR
Declared as: 0
Define [sv_addr.agh, 3060] sv_addr.agh
R_ATA_STATUS_DATA__data__WIDTH
Declared as: 16
Define [sv_addr.agh, 3061] sv_addr.agh
R_ATA_STATUS_DATA__dav__BITNR
Declared as: 16
Define [sv_addr.agh, 3056] sv_addr.agh
Macro [ide.c, 136] byte
R_ATA_STATUS_DATA__dav__data
Declared as: 1
Define [sv_addr.agh, 3058] sv_addr.agh
R_ATA_STATUS_DATA__dav__nodata
Declared as: 0
Define [sv_addr.agh, 3059] sv_addr.agh
R_ATA_STATUS_DATA__dav__WIDTH
Declared as: 1
Define [sv_addr.agh, 3057] sv_addr.agh
Macro [ide.c, 136] byte
R_ATA_STATUS_DATA__tr_rdy__BITNR
Declared as: 17
Define [sv_addr.agh, 3052] sv_addr.agh
Macro [ide.c, 128] outb_p
R_ATA_STATUS_DATA__tr_rdy__busy
Declared as: 0
Define [sv_addr.agh, 3055] sv_addr.agh
R_ATA_STATUS_DATA__tr_rdy__ready
Declared as: 1
Define [sv_addr.agh, 3054] sv_addr.agh
R_ATA_STATUS_DATA__tr_rdy__WIDTH
Declared as: 1
Define [sv_addr.agh, 3053] sv_addr.agh
Macro [ide.c, 128] outb_p
R_ATA_TRANSFER_CNT
Declared as: (IO_TYPECAST_UDWORD 0xb0000048)
Define [sv_addr.agh, 3079] sv_addr.agh
Use [ide.c, 298] init_e100_ide
Use [ide.c, 407] e100_atapi_input_bytes
Use [ide.c, 486] e100_atapi_output_bytes
Use [ide.c, 832] e100_dmaproc
Use [ide.c, 875] e100_dmaproc
R_ATA_TRANSFER_CNT__count__BITNR
Declared as: 0
Define [sv_addr.agh, 3080] sv_addr.agh
Macro [ide.c, 407] e100_atapi_input_bytes
Macro [ide.c, 486] e100_atapi_output_bytes
Macro [ide.c, 833] e100_dmaproc
Macro [ide.c, 876] e100_dmaproc
R_ATA_TRANSFER_CNT__count__WIDTH
Declared as: 17
Define [sv_addr.agh, 3081] sv_addr.agh
R_BPR
Declared as: 0xc2
Define [de620.h, 63] de620.h
R_BRICK
Declared as: 0x200
Define [eeprom.h, 273] eeprom.h
Macro [eeprom.h, 274] eeprom.h
Macro [eeprom.h, 301] eeprom.h
R_BUF_SIZE
Declared as: 1544
Define [ni65.c, 140] ni65.c
Use [ni65.c, 544] ni65_alloc_mem
Use [ni65.c, 606] ni65_alloc_buffer
Use [ni65.c, 773] ni65_lance_reinit
Use [ni65.c, 1060] ni65_recv_intr
R_BUFF
Declared as: 0x0400
Define [depca.h, 99] depca.h
Use [depca.c, 970] depca_rx
R_BUS_CONFIG
Declared as: (IO_TYPECAST_UDWORD 0xb0000004)
Define [sv_addr.agh, 39] sv_addr.agh
R_BUS_CONFIG__dma_burst__BITNR
Declared as: 8
Define [sv_addr.agh, 44] sv_addr.agh
R_BUS_CONFIG__dma_burst__burst16
Declared as: 1
Define [sv_addr.agh, 46] sv_addr.agh
R_BUS_CONFIG__dma_burst__burst32
Declared as: 0
Define [sv_addr.agh, 47] sv_addr.agh
R_BUS_CONFIG__dma_burst__WIDTH
Declared as: 1
Define [sv_addr.agh, 45] sv_addr.agh
R_BUS_CONFIG__flash_bw__BITNR
Declared as: 0
Define [sv_addr.agh, 76] sv_addr.agh
R_BUS_CONFIG__flash_bw__bw16
Declared as: 0
Define [sv_addr.agh, 79] sv_addr.agh
R_BUS_CONFIG__flash_bw__bw32
Declared as: 1
Define [sv_addr.agh, 78] sv_addr.agh
R_BUS_CONFIG__flash_bw__WIDTH
Declared as: 1
Define [sv_addr.agh, 77] sv_addr.agh
R_BUS_CONFIG__flash_wr__BITNR
Declared as: 4
Define [sv_addr.agh, 60] sv_addr.agh
R_BUS_CONFIG__flash_wr__ext
Declared as: 1
Define [sv_addr.agh, 62] sv_addr.agh
R_BUS_CONFIG__flash_wr__norm
Declared as: 0
Define [sv_addr.agh, 63] sv_addr.agh
R_BUS_CONFIG__flash_wr__WIDTH
Declared as: 1
Define [sv_addr.agh, 61] sv_addr.agh
R_BUS_CONFIG__pcs0_3_bw__BITNR
Declared as: 2
Define [sv_addr.agh, 68] sv_addr.agh
R_BUS_CONFIG__pcs0_3_bw__bw16
Declared as: 0
Define [sv_addr.agh, 71] sv_addr.agh
R_BUS_CONFIG__pcs0_3_bw__bw32
Declared as: 1
Define [sv_addr.agh, 70] sv_addr.agh
R_BUS_CONFIG__pcs0_3_bw__WIDTH
Declared as: 1
Define [sv_addr.agh, 69] sv_addr.agh
R_BUS_CONFIG__pcs0_3_wr__BITNR
Declared as: 6
Define [sv_addr.agh, 52] sv_addr.agh
R_BUS_CONFIG__pcs0_3_wr__ext
Declared as: 1
Define [sv_addr.agh, 54] sv_addr.agh
R_BUS_CONFIG__pcs0_3_wr__norm
Declared as: 0
Define [sv_addr.agh, 55] sv_addr.agh
R_BUS_CONFIG__pcs0_3_wr__WIDTH
Declared as: 1
Define [sv_addr.agh, 53] sv_addr.agh
R_BUS_CONFIG__pcs4_7_bw__BITNR
Declared as: 3
Define [sv_addr.agh, 64] sv_addr.agh
R_BUS_CONFIG__pcs4_7_bw__bw16
Declared as: 0
Define [sv_addr.agh, 67] sv_addr.agh
R_BUS_CONFIG__pcs4_7_bw__bw32
Declared as: 1
Define [sv_addr.agh, 66] sv_addr.agh
R_BUS_CONFIG__pcs4_7_bw__WIDTH
Declared as: 1
Define [sv_addr.agh, 65] sv_addr.agh
R_BUS_CONFIG__pcs4_7_wr__BITNR
Declared as: 7
Define [sv_addr.agh, 48] sv_addr.agh
R_BUS_CONFIG__pcs4_7_wr__ext
Declared as: 1
Define [sv_addr.agh, 50] sv_addr.agh
R_BUS_CONFIG__pcs4_7_wr__norm
Declared as: 0
Define [sv_addr.agh, 51] sv_addr.agh
R_BUS_CONFIG__pcs4_7_wr__WIDTH
Declared as: 1
Define [sv_addr.agh, 49] sv_addr.agh
R_BUS_CONFIG__sram_bw__BITNR
Declared as: 1
Define [sv_addr.agh, 72] sv_addr.agh
R_BUS_CONFIG__sram_bw__bw16
Declared as: 0
Define [sv_addr.agh, 75] sv_addr.agh
R_BUS_CONFIG__sram_bw__bw32
Declared as: 1
Define [sv_addr.agh, 74] sv_addr.agh
R_BUS_CONFIG__sram_bw__WIDTH
Declared as: 1
Define [sv_addr.agh, 73] sv_addr.agh
R_BUS_CONFIG__sram_type__BITNR
Declared as: 9
Define [sv_addr.agh, 40] sv_addr.agh
R_BUS_CONFIG__sram_type__bwe
Declared as: 0
Define [sv_addr.agh, 43] sv_addr.agh
R_BUS_CONFIG__sram_type__cwe
Declared as: 1
Define [sv_addr.agh, 42] sv_addr.agh
R_BUS_CONFIG__sram_type__WIDTH
Declared as: 1
Define [sv_addr.agh, 41] sv_addr.agh
R_BUS_CONFIG__sram_wr__BITNR
Declared as: 5
Define [sv_addr.agh, 56] sv_addr.agh
R_BUS_CONFIG__sram_wr__ext
Declared as: 1
Define [sv_addr.agh, 58] sv_addr.agh
R_BUS_CONFIG__sram_wr__norm
Declared as: 0
Define [sv_addr.agh, 59] sv_addr.agh
R_BUS_CONFIG__sram_wr__WIDTH
Declared as: 1
Define [sv_addr.agh, 57] sv_addr.agh
R_BUS_STATUS
Declared as: (IO_TYPECAST_RO_UDWORD 0xb0000004)
Define [sv_addr.agh, 81] sv_addr.agh
R_BUS_STATUS__boot__BITNR
Declared as: 1
Define [sv_addr.agh, 94] sv_addr.agh
R_BUS_STATUS__boot__network
Declared as: 2
Define [sv_addr.agh, 98] sv_addr.agh
R_BUS_STATUS__boot__parallel
Declared as: 3
Define [sv_addr.agh, 99] sv_addr.agh
R_BUS_STATUS__boot__serial
Declared as: 1
Define [sv_addr.agh, 97] sv_addr.agh
R_BUS_STATUS__boot__uncached
Declared as: 0
Define [sv_addr.agh, 96] sv_addr.agh
R_BUS_STATUS__boot__WIDTH
Declared as: 2
Define [sv_addr.agh, 95] sv_addr.agh
R_BUS_STATUS__both_faults__BITNR
Declared as: 4
Define [sv_addr.agh, 86] sv_addr.agh
R_BUS_STATUS__both_faults__no
Declared as: 0
Define [sv_addr.agh, 88] sv_addr.agh
R_BUS_STATUS__both_faults__WIDTH
Declared as: 1
Define [sv_addr.agh, 87] sv_addr.agh
R_BUS_STATUS__both_faults__yes
Declared as: 1
Define [sv_addr.agh, 89] sv_addr.agh
R_BUS_STATUS__bsen___BITNR
Declared as: 3
Define [sv_addr.agh, 90] sv_addr.agh
R_BUS_STATUS__bsen___disable
Declared as: 1
Define [sv_addr.agh, 93] sv_addr.agh
R_BUS_STATUS__bsen___enable
Declared as: 0
Define [sv_addr.agh, 92] sv_addr.agh
R_BUS_STATUS__bsen___WIDTH
Declared as: 1
Define [sv_addr.agh, 91] sv_addr.agh
R_BUS_STATUS__flashw__BITNR
Declared as: 0
Define [sv_addr.agh, 100] sv_addr.agh
R_BUS_STATUS__flashw__bw16
Declared as: 0
Define [sv_addr.agh, 103] sv_addr.agh
R_BUS_STATUS__flashw__bw32
Declared as: 1
Define [sv_addr.agh, 102] sv_addr.agh
R_BUS_STATUS__flashw__WIDTH
Declared as: 1
Define [sv_addr.agh, 101] sv_addr.agh
R_BUS_STATUS__pll_lock_tm__BITNR
Declared as: 5
Define [sv_addr.agh, 82] sv_addr.agh
R_BUS_STATUS__pll_lock_tm__counting
Declared as: 1
Define [sv_addr.agh, 85] sv_addr.agh
R_BUS_STATUS__pll_lock_tm__expired
Declared as: 0
Define [sv_addr.agh, 84] sv_addr.agh
R_BUS_STATUS__pll_lock_tm__WIDTH
Declared as: 1
Define [sv_addr.agh, 83] sv_addr.agh
R_CHG_PARM
R_CLOCK_PRESCALE
Declared as: (IO_TYPECAST_UDWORD 0xb00000f0)
Define [sv_addr.agh, 583] sv_addr.agh
R_CLOCK_PRESCALE__ser_presc__BITNR
Declared as: 16
Define [sv_addr.agh, 584] sv_addr.agh
R_CLOCK_PRESCALE__ser_presc__WIDTH
Declared as: 16
Define [sv_addr.agh, 585] sv_addr.agh
R_CLOCK_PRESCALE__tim_presc__BITNR
Declared as: 0
Define [sv_addr.agh, 586] sv_addr.agh
R_CLOCK_PRESCALE__tim_presc__WIDTH
Declared as: 16
Define [sv_addr.agh, 587] sv_addr.agh
R_CPR
Declared as: 0xc1
Define [de620.h, 62] de620.h
Use [de620.c, 715] de620_rx_intr
Use [de620.c, 840] de620_probe
R_CRC
Declared as: 0x02
Define [ewrk3.h, 138] ewrk3.h
R_CRC
Declared as: 0x0800
Define [depca.h, 98] depca.h
Use [depca.c, 969] depca_rx
Use [ewrk3.c, 978] ewrk3_rx
R_CTL_ACK_1
Declared as: 0xc0
Define [fc.h, 59] fc.h
R_CTL_ACK_N
Declared as: 0xc1
Define [fc.h, 60] fc.h
R_CTL_BASIC_SVC
Declared as: 0x80
Define [fc.h, 38] fc.h
R_CTL_COMMAND
Declared as: 0x06
Define [fc.h, 47] fc.h
R_CTL_DEVICE_DATA
Declared as: 0x00
Define [fc.h, 34] fc.h
R_CTL_ELS_REQ
Declared as: 0x22
Define [fc.h, 56] fc.h
R_CTL_ELS_RSP
Declared as: 0x23
Define [fc.h, 57] fc.h
R_CTL_EXTENDED_SVC
Declared as: 0x20
Define [fc.h, 35] fc.h
Use [soc.c, 272] soc_unsolicited
Use [socal.c, 344] socal_unsolicited
R_CTL_F_BSY_DF
Declared as: 0xc5
Define [fc.h, 64] fc.h
R_CTL_F_BSY_LC
Declared as: 0xc6
Define [fc.h, 65] fc.h
R_CTL_F_RJT
Declared as: 0xc3
Define [fc.h, 62] fc.h
R_CTL_FC4_SVC
Declared as: 0x30
Define [fc.h, 36] fc.h
R_CTL_LCR
Declared as: 0xc7
Define [fc.h, 66] fc.h
R_CTL_LINK_CTL
Declared as: 0xc0
Define [fc.h, 39] fc.h
R_CTL_LS_ABTS
Declared as: 0x81
Define [fc.h, 51] fc.h
R_CTL_LS_BA_ACC
Declared as: 0x84
Define [fc.h, 53] fc.h
R_CTL_LS_BA_RJT
Declared as: 0x85
Define [fc.h, 54] fc.h
R_CTL_LS_NOP
Declared as: 0x80
Define [fc.h, 50] fc.h
R_CTL_LS_RMC
Declared as: 0x82
Define [fc.h, 52] fc.h
R_CTL_P_BSY
Declared as: 0xc4
Define [fc.h, 63] fc.h
R_CTL_P_RJT
Declared as: 0xc2
Define [fc.h, 61] fc.h
R_CTL_SOLICITED_CONTROL
Declared as: 0x03
Define [fc.h, 44] fc.h
R_CTL_SOLICITED_DATA
Declared as: 0x01
Define [fc.h, 42] fc.h
R_CTL_STATUS
Declared as: 0x07
Define [fc.h, 48] fc.h
R_CTL_UNCATEGORIZED
Declared as: 0x00
Define [fc.h, 41] fc.h
R_CTL_UNSOL_CONTROL
Declared as: 0x02
Define [fc.h, 43] fc.h
R_CTL_UNSOL_DATA
Declared as: 0x04
Define [fc.h, 45] fc.h
R_CTL_VIDEO
Declared as: 0x40
Define [fc.h, 37] fc.h
R_CTL_XFER_RDY
Declared as: 0x05
Define [fc.h, 46] fc.h
r_ctr
Declared as: (unsigned char)inb((x)+2)
Define [ppa.h, 138] ppa.h
r_ctr
Declared as: (unsigned char)inb((x)+2)
Define [imm.h, 130] imm.h
r_data_control
Declared as: (cm206_base+0x8)
Define [cm206.h, 24] cm206.h
Use [cm206.c, 401] cm206_interrupt
Use [cm206.c, 428] cm206_interrupt
Use [cm206.c, 477] send_command
Use [cm206.c, 565] reset_cm260
Use [cm206.c, 567] reset_cm260
Use [cm206.c, 633] read_background
Use [cm206.c, 712] cm206_bh
Use [cm206.c, 1289] cm206_reset
Use [cm206.c, 1291] cm206.c
Use [cm206.c, 1408] probe_irq
Use [cm206.c, 1414] probe_irq
r_data_status
Declared as: (cm206_base)
Define [cm206.h, 20] cm206.h
Use [cm206.c, 364] cm206_interrupt
Use [cm206.c, 400] cm206_interrupt
Use [cm206.c, 477] send_command
Use [cm206.c, 712] cm206_bh
Use [cm206.c, 1503] cm206_init
R_DBE
Declared as: 0x04
Define [ewrk3.h, 137] ewrk3.h
Use [ewrk3.c, 976] ewrk3_rx
R_DCB_XMAP9_PROTOCOL
Declared as: DCB_CYCLES (2, 1, 3)
Define [newport.h, 560] newport.h
Use [newport.h, 566] xmap9FIFOWait
Use [newport.c, 184] newport_ioctl
Use [newport_con.c, 175] newport_reset
Use [newport_con.c, 178] newport_reset
Use [newport_con.c, 262] newport_get_revisions
R_DMA_CH0_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000108)
Define [sv_addr.agh, 5447] sv_addr.agh
R_DMA_CH0_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5448] sv_addr.agh
R_DMA_CH0_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5449] sv_addr.agh
R_DMA_CH0_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001d1)
Define [sv_addr.agh, 5464] sv_addr.agh
Use [ethernet.c, 486] e100_open
Use [ethernet.c, 757] e100tx_interrupt
R_DMA_CH0_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5469] sv_addr.agh
Macro [sync_serial.c, 774] tr_interrupt
Macro [sync_serial.c, 800] rx_interrupt
R_DMA_CH0_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5471] sv_addr.agh
Macro [sync_serial.c, 774] tr_interrupt
Macro [sync_serial.c, 800] rx_interrupt
R_DMA_CH0_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5472] sv_addr.agh
R_DMA_CH0_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5470] sv_addr.agh
R_DMA_CH0_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5465] sv_addr.agh
Macro [ethernet.c, 486] e100_open
Macro [ethernet.c, 757] e100tx_interrupt
Macro [sync_serial.c, 773] tr_interrupt
Macro [sync_serial.c, 799] rx_interrupt
R_DMA_CH0_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5467] sv_addr.agh
Macro [ethernet.c, 486] e100_open
Macro [ethernet.c, 757] e100tx_interrupt
Macro [sync_serial.c, 773] tr_interrupt
Macro [sync_serial.c, 799] rx_interrupt
R_DMA_CH0_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5468] sv_addr.agh
R_DMA_CH0_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5466] sv_addr.agh
R_DMA_CH0_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001d0)
Define [sv_addr.agh, 5455] sv_addr.agh
Macro [svinto.h, 42] svinto.h
Macro [svinto.h, 52] svinto.h
Macro [svinto.h, 52] svinto.h
Macro [ethernet.c, 222] ethernet.c
Macro [ethernet.c, 634] e100_tx_timeout
Use [ethernet.c, 1088] e100_hardware_send_packet
Macro [e100lpslavenet.c, 137] e100lpslavenet.c
R_DMA_CH0_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5456] sv_addr.agh
Macro [ethernet.c, 398] e100_open
Macro [ethernet.c, 399] e100_open
Macro [ethernet.c, 400] e100_open
Macro [ethernet.c, 400] e100_open
Macro [ethernet.c, 401] e100_open
Macro [ethernet.c, 401] e100_open
Macro [ethernet.c, 642] e100_tx_timeout
Macro [ethernet.c, 643] e100_tx_timeout
Macro [ethernet.c, 643] e100_tx_timeout
Macro [ethernet.c, 925] e100_close
Macro [ethernet.c, 926] e100_close
Macro [ethernet.c, 1088] e100_hardware_send_packet
Macro [ide.c, 361] init_e100_ide
Macro [ide.c, 362] init_e100_ide
Macro [ide.c, 363] init_e100_ide
Macro [ide.c, 363] init_e100_ide
Macro [ide.c, 364] init_e100_ide
Macro [ide.c, 364] init_e100_ide
Macro [ide.c, 391] e100_atapi_input_bytes
Macro [ide.c, 392] e100_atapi_input_bytes
Macro [ide.c, 392] e100_atapi_input_bytes
Macro [ide.c, 419] e100_atapi_input_bytes
Macro [ide.c, 419] e100_atapi_input_bytes
Macro [ide.c, 470] e100_atapi_output_bytes
Macro [ide.c, 471] e100_atapi_output_bytes
Macro [ide.c, 471] e100_atapi_output_bytes
Macro [ide.c, 498] e100_atapi_output_bytes
Macro [ide.c, 498] e100_atapi_output_bytes
Macro [ide.c, 807] e100_dmaproc
Macro [ide.c, 808] e100_dmaproc
Macro [ide.c, 808] e100_dmaproc
Macro [ide.c, 850] e100_dmaproc
Macro [ide.c, 851] e100_dmaproc
Macro [ide.c, 851] e100_dmaproc
Macro [sync_serial.c, 386] sync_serial_ioctl
Macro [sync_serial.c, 386] sync_serial_ioctl
Macro [sync_serial.c, 386] sync_serial_ioctl
Macro [sync_serial.c, 393] sync_serial_ioctl
Macro [sync_serial.c, 393] sync_serial_ioctl
Macro [sync_serial.c, 393] sync_serial_ioctl
Macro [sync_serial.c, 720] start_dma
Macro [sync_serial.c, 758] start_dma_in
R_DMA_CH0_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5461] sv_addr.agh
R_DMA_CH0_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5458] sv_addr.agh
Macro [ethernet.c, 400] e100_open
Macro [ethernet.c, 401] e100_open
Macro [ethernet.c, 643] e100_tx_timeout
Macro [ide.c, 363] init_e100_ide
Macro [ide.c, 364] init_e100_ide
Macro [ide.c, 392] e100_atapi_input_bytes
Macro [ide.c, 419] e100_atapi_input_bytes
Macro [ide.c, 471] e100_atapi_output_bytes
Macro [ide.c, 498] e100_atapi_output_bytes
Macro [ide.c, 808] e100_dmaproc
Macro [ide.c, 851] e100_dmaproc
Macro [sync_serial.c, 386] sync_serial_ioctl
Macro [sync_serial.c, 393] sync_serial_ioctl
R_DMA_CH0_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5462] sv_addr.agh
Macro [ethernet.c, 398] e100_open
Macro [ethernet.c, 399] e100_open
Macro [ethernet.c, 642] e100_tx_timeout
Macro [ethernet.c, 925] e100_close
Macro [ethernet.c, 926] e100_close
Macro [ide.c, 361] init_e100_ide
Macro [ide.c, 362] init_e100_ide
Macro [ide.c, 391] e100_atapi_input_bytes
Macro [ide.c, 470] e100_atapi_output_bytes
Macro [ide.c, 807] e100_dmaproc
Macro [ide.c, 850] e100_dmaproc
Macro [sync_serial.c, 386] sync_serial_ioctl
Macro [sync_serial.c, 393] sync_serial_ioctl
R_DMA_CH0_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5460] sv_addr.agh
R_DMA_CH0_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5459] sv_addr.agh
Macro [ethernet.c, 1088] e100_hardware_send_packet
Macro [sync_serial.c, 720] start_dma
Macro [sync_serial.c, 758] start_dma_in
R_DMA_CH0_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5457] sv_addr.agh
Macro [ethernet.c, 400] e100_open
Macro [ethernet.c, 401] e100_open
Macro [ethernet.c, 643] e100_tx_timeout
Macro [ide.c, 363] init_e100_ide
Macro [ide.c, 364] init_e100_ide
Macro [ide.c, 392] e100_atapi_input_bytes
Macro [ide.c, 419] e100_atapi_input_bytes
Macro [ide.c, 471] e100_atapi_output_bytes
Macro [ide.c, 498] e100_atapi_output_bytes
Macro [ide.c, 808] e100_dmaproc
Macro [ide.c, 851] e100_dmaproc
Macro [sync_serial.c, 386] sync_serial_ioctl
Macro [sync_serial.c, 393] sync_serial_ioctl
R_DMA_CH0_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000010c)
Define [sv_addr.agh, 5439] sv_addr.agh
R_DMA_CH0_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5440] sv_addr.agh
R_DMA_CH0_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5441] sv_addr.agh
R_DMA_CH0_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001a0)
Define [sv_addr.agh, 5451] sv_addr.agh
Use [ethernet.c, 759] e100tx_interrupt
Use [ethernet.c, 1087] e100_hardware_send_packet
R_DMA_CH0_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5452] sv_addr.agh
R_DMA_CH0_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5453] sv_addr.agh
R_DMA_CH0_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000100)
Define [sv_addr.agh, 5433] sv_addr.agh
R_DMA_CH0_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5434] sv_addr.agh
R_DMA_CH0_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5435] sv_addr.agh
R_DMA_CH0_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5436] sv_addr.agh
R_DMA_CH0_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5437] sv_addr.agh
R_DMA_CH0_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000104)
Define [sv_addr.agh, 5443] sv_addr.agh
R_DMA_CH0_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5444] sv_addr.agh
R_DMA_CH0_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5445] sv_addr.agh
R_DMA_CH0_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001d2)
Define [sv_addr.agh, 5474] sv_addr.agh
R_DMA_CH0_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5475] sv_addr.agh
R_DMA_CH0_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5476] sv_addr.agh
R_DMA_CH1_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000118)
Define [sv_addr.agh, 5492] sv_addr.agh
R_DMA_CH1_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5493] sv_addr.agh
R_DMA_CH1_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5494] sv_addr.agh
R_DMA_CH1_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001d5)
Define [sv_addr.agh, 5509] sv_addr.agh
Use [ethernet.c, 487] e100_open
Use [ethernet.c, 710] e100rx_interrupt
Use [ethernet.c, 723] e100rx_interrupt
R_DMA_CH1_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5514] sv_addr.agh
Macro [ethernet.c, 725] e100rx_interrupt
R_DMA_CH1_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5516] sv_addr.agh
Macro [ethernet.c, 725] e100rx_interrupt
R_DMA_CH1_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5517] sv_addr.agh
R_DMA_CH1_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5515] sv_addr.agh
R_DMA_CH1_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5510] sv_addr.agh
Macro [ethernet.c, 487] e100_open
Macro [ethernet.c, 710] e100rx_interrupt
Macro [ethernet.c, 724] e100rx_interrupt
R_DMA_CH1_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5512] sv_addr.agh
Macro [ethernet.c, 487] e100_open
Macro [ethernet.c, 710] e100rx_interrupt
Macro [ethernet.c, 724] e100rx_interrupt
R_DMA_CH1_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5513] sv_addr.agh
R_DMA_CH1_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5511] sv_addr.agh
R_DMA_CH1_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001d4)
Define [sv_addr.agh, 5500] sv_addr.agh
Use [ethernet.c, 497] e100_open
Use [ethernet.c, 721] e100rx_interrupt
R_DMA_CH1_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5501] sv_addr.agh
Macro [ethernet.c, 497] e100_open
Macro [ethernet.c, 721] e100rx_interrupt
R_DMA_CH1_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5506] sv_addr.agh
R_DMA_CH1_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5503] sv_addr.agh
R_DMA_CH1_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5507] sv_addr.agh
R_DMA_CH1_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5505] sv_addr.agh
Macro [ethernet.c, 721] e100rx_interrupt
R_DMA_CH1_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5504] sv_addr.agh
Macro [ethernet.c, 497] e100_open
R_DMA_CH1_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5502] sv_addr.agh
R_DMA_CH1_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000011c)
Define [sv_addr.agh, 5484] sv_addr.agh
R_DMA_CH1_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5485] sv_addr.agh
R_DMA_CH1_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5486] sv_addr.agh
R_DMA_CH1_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001a4)
Define [sv_addr.agh, 5496] sv_addr.agh
Use [ethernet.c, 496] e100_open
Use [ethernet.c, 714] e100rx_interrupt
R_DMA_CH1_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5497] sv_addr.agh
R_DMA_CH1_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5498] sv_addr.agh
R_DMA_CH1_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000110)
Define [sv_addr.agh, 5478] sv_addr.agh
R_DMA_CH1_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5479] sv_addr.agh
R_DMA_CH1_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5480] sv_addr.agh
R_DMA_CH1_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5481] sv_addr.agh
R_DMA_CH1_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5482] sv_addr.agh
R_DMA_CH1_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000114)
Define [sv_addr.agh, 5488] sv_addr.agh
R_DMA_CH1_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5489] sv_addr.agh
R_DMA_CH1_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5490] sv_addr.agh
R_DMA_CH1_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001d6)
Define [sv_addr.agh, 5519] sv_addr.agh
R_DMA_CH1_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5520] sv_addr.agh
R_DMA_CH1_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5521] sv_addr.agh
R_DMA_CH2_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000128)
Define [sv_addr.agh, 5537] sv_addr.agh
R_DMA_CH2_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5538] sv_addr.agh
R_DMA_CH2_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5539] sv_addr.agh
R_DMA_CH2_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001d9)
Define [sv_addr.agh, 5554] sv_addr.agh
Use [parport.c, 118] parport.c
Use [serial.c, 346] serial.c
R_DMA_CH2_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5559] sv_addr.agh
R_DMA_CH2_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5561] sv_addr.agh
R_DMA_CH2_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5562] sv_addr.agh
R_DMA_CH2_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5560] sv_addr.agh
R_DMA_CH2_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5555] sv_addr.agh
R_DMA_CH2_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5557] sv_addr.agh
R_DMA_CH2_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5558] sv_addr.agh
R_DMA_CH2_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5556] sv_addr.agh
R_DMA_CH2_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001d8)
Define [sv_addr.agh, 5545] sv_addr.agh
Use [ide.c, 482] e100_atapi_output_bytes
Use [ide.c, 871] e100_dmaproc
Use [parport.c, 120] parport.c
Use [serial.c, 346] serial.c
R_DMA_CH2_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5546] sv_addr.agh
Macro [ide.c, 482] e100_atapi_output_bytes
Macro [ide.c, 871] e100_dmaproc
R_DMA_CH2_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5551] sv_addr.agh
R_DMA_CH2_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5548] sv_addr.agh
R_DMA_CH2_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5552] sv_addr.agh
R_DMA_CH2_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5550] sv_addr.agh
R_DMA_CH2_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5549] sv_addr.agh
Macro [ide.c, 482] e100_atapi_output_bytes
Macro [ide.c, 871] e100_dmaproc
R_DMA_CH2_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5547] sv_addr.agh
R_DMA_CH2_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000012c)
Define [sv_addr.agh, 5529] sv_addr.agh
R_DMA_CH2_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5530] sv_addr.agh
R_DMA_CH2_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5531] sv_addr.agh
R_DMA_CH2_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001a8)
Define [sv_addr.agh, 5541] sv_addr.agh
Use [ide.c, 481] e100_atapi_output_bytes
Use [ide.c, 870] e100_dmaproc
Use [parport.c, 119] parport.c
Use [serial.c, 346] serial.c
R_DMA_CH2_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5542] sv_addr.agh
R_DMA_CH2_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5543] sv_addr.agh
R_DMA_CH2_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000120)
Define [sv_addr.agh, 5523] sv_addr.agh
Use [serial.c, 347] serial.c
R_DMA_CH2_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5524] sv_addr.agh
R_DMA_CH2_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5525] sv_addr.agh
R_DMA_CH2_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5526] sv_addr.agh
R_DMA_CH2_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5527] sv_addr.agh
R_DMA_CH2_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000124)
Define [sv_addr.agh, 5533] sv_addr.agh
R_DMA_CH2_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5534] sv_addr.agh
R_DMA_CH2_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5535] sv_addr.agh
R_DMA_CH2_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001da)
Define [sv_addr.agh, 5564] sv_addr.agh
Use [serial.c, 347] serial.c
R_DMA_CH2_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5565] sv_addr.agh
R_DMA_CH2_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5566] sv_addr.agh
R_DMA_CH3_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000138)
Define [sv_addr.agh, 5582] sv_addr.agh
R_DMA_CH3_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5583] sv_addr.agh
R_DMA_CH3_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5584] sv_addr.agh
R_DMA_CH3_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001dd)
Define [sv_addr.agh, 5599] sv_addr.agh
Use [parport.c, 121] parport.c
Use [serial.c, 348] serial.c
R_DMA_CH3_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5604] sv_addr.agh
R_DMA_CH3_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5606] sv_addr.agh
R_DMA_CH3_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5607] sv_addr.agh
R_DMA_CH3_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5605] sv_addr.agh
R_DMA_CH3_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5600] sv_addr.agh
R_DMA_CH3_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5602] sv_addr.agh
R_DMA_CH3_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5603] sv_addr.agh
R_DMA_CH3_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5601] sv_addr.agh
R_DMA_CH3_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001dc)
Define [sv_addr.agh, 5590] sv_addr.agh
Use [ide.c, 403] e100_atapi_input_bytes
Use [ide.c, 828] e100_dmaproc
Use [parport.c, 123] parport.c
Use [serial.c, 348] serial.c
R_DMA_CH3_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5591] sv_addr.agh
Macro [ide.c, 403] e100_atapi_input_bytes
Macro [ide.c, 828] e100_dmaproc
R_DMA_CH3_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5596] sv_addr.agh
R_DMA_CH3_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5593] sv_addr.agh
R_DMA_CH3_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5597] sv_addr.agh
R_DMA_CH3_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5595] sv_addr.agh
R_DMA_CH3_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5594] sv_addr.agh
Macro [ide.c, 403] e100_atapi_input_bytes
Macro [ide.c, 828] e100_dmaproc
R_DMA_CH3_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5592] sv_addr.agh
R_DMA_CH3_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000013c)
Define [sv_addr.agh, 5574] sv_addr.agh
R_DMA_CH3_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5575] sv_addr.agh
R_DMA_CH3_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5576] sv_addr.agh
R_DMA_CH3_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001ac)
Define [sv_addr.agh, 5586] sv_addr.agh
Use [ide.c, 402] e100_atapi_input_bytes
Use [ide.c, 827] e100_dmaproc
Use [parport.c, 122] parport.c
Use [serial.c, 348] serial.c
R_DMA_CH3_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5587] sv_addr.agh
R_DMA_CH3_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5588] sv_addr.agh
R_DMA_CH3_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000130)
Define [sv_addr.agh, 5568] sv_addr.agh
Use [serial.c, 349] serial.c
R_DMA_CH3_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5569] sv_addr.agh
R_DMA_CH3_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5570] sv_addr.agh
R_DMA_CH3_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5571] sv_addr.agh
R_DMA_CH3_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5572] sv_addr.agh
R_DMA_CH3_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000134)
Define [sv_addr.agh, 5578] sv_addr.agh
R_DMA_CH3_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5579] sv_addr.agh
R_DMA_CH3_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5580] sv_addr.agh
R_DMA_CH3_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001de)
Define [sv_addr.agh, 5609] sv_addr.agh
Use [serial.c, 349] serial.c
R_DMA_CH3_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5610] sv_addr.agh
R_DMA_CH3_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5611] sv_addr.agh
R_DMA_CH4_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000148)
Define [sv_addr.agh, 5627] sv_addr.agh
R_DMA_CH4_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5628] sv_addr.agh
R_DMA_CH4_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5629] sv_addr.agh
R_DMA_CH4_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001e1)
Define [sv_addr.agh, 5644] sv_addr.agh
Use [parport.c, 145] parport.c
Use [serial.c, 353] serial.c
Use [sync_serial.c, 159] sync_serial.c
Use [sync_serial.c, 387] sync_serial_ioctl
R_DMA_CH4_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5649] sv_addr.agh
Macro [sync_serial.c, 388] sync_serial_ioctl
R_DMA_CH4_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5651] sv_addr.agh
Macro [sync_serial.c, 388] sync_serial_ioctl
R_DMA_CH4_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5652] sv_addr.agh
R_DMA_CH4_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5650] sv_addr.agh
R_DMA_CH4_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5645] sv_addr.agh
Macro [sync_serial.c, 387] sync_serial_ioctl
R_DMA_CH4_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5647] sv_addr.agh
Macro [sync_serial.c, 387] sync_serial_ioctl
R_DMA_CH4_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5648] sv_addr.agh
R_DMA_CH4_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5646] sv_addr.agh
R_DMA_CH4_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001e0)
Define [sv_addr.agh, 5635] sv_addr.agh
Use [parport.c, 147] parport.c
Use [serial.c, 353] serial.c
Use [sync_serial.c, 158] sync_serial.c
Macro [sync_serial.c, 386] sync_serial_ioctl
Macro [sync_serial.c, 386] sync_serial_ioctl
R_DMA_CH4_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5636] sv_addr.agh
R_DMA_CH4_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5641] sv_addr.agh
R_DMA_CH4_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5638] sv_addr.agh
R_DMA_CH4_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5642] sv_addr.agh
R_DMA_CH4_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5640] sv_addr.agh
R_DMA_CH4_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5639] sv_addr.agh
R_DMA_CH4_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5637] sv_addr.agh
R_DMA_CH4_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000014c)
Define [sv_addr.agh, 5619] sv_addr.agh
R_DMA_CH4_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5620] sv_addr.agh
R_DMA_CH4_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5621] sv_addr.agh
R_DMA_CH4_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001b0)
Define [sv_addr.agh, 5631] sv_addr.agh
Use [parport.c, 146] parport.c
Use [serial.c, 353] serial.c
Use [sync_serial.c, 157] sync_serial.c
R_DMA_CH4_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5632] sv_addr.agh
R_DMA_CH4_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5633] sv_addr.agh
R_DMA_CH4_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000140)
Define [sv_addr.agh, 5613] sv_addr.agh
Use [serial.c, 354] serial.c
R_DMA_CH4_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5614] sv_addr.agh
R_DMA_CH4_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5615] sv_addr.agh
R_DMA_CH4_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5616] sv_addr.agh
R_DMA_CH4_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5617] sv_addr.agh
R_DMA_CH4_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000144)
Define [sv_addr.agh, 5623] sv_addr.agh
R_DMA_CH4_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5624] sv_addr.agh
R_DMA_CH4_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5625] sv_addr.agh
R_DMA_CH4_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001e2)
Define [sv_addr.agh, 5654] sv_addr.agh
Use [serial.c, 354] serial.c
R_DMA_CH4_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5655] sv_addr.agh
R_DMA_CH4_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5656] sv_addr.agh
R_DMA_CH5_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000158)
Define [sv_addr.agh, 5672] sv_addr.agh
R_DMA_CH5_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5673] sv_addr.agh
R_DMA_CH5_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5674] sv_addr.agh
R_DMA_CH5_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001e5)
Define [sv_addr.agh, 5689] sv_addr.agh
Use [parport.c, 148] parport.c
Use [serial.c, 355] serial.c
Use [sync_serial.c, 162] sync_serial.c
R_DMA_CH5_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5694] sv_addr.agh
R_DMA_CH5_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5696] sv_addr.agh
R_DMA_CH5_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5697] sv_addr.agh
R_DMA_CH5_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5695] sv_addr.agh
R_DMA_CH5_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5690] sv_addr.agh
R_DMA_CH5_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5692] sv_addr.agh
R_DMA_CH5_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5693] sv_addr.agh
R_DMA_CH5_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5691] sv_addr.agh
R_DMA_CH5_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001e4)
Define [sv_addr.agh, 5680] sv_addr.agh
Use [parport.c, 150] parport.c
Use [serial.c, 355] serial.c
Use [sync_serial.c, 161] sync_serial.c
R_DMA_CH5_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5681] sv_addr.agh
R_DMA_CH5_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5686] sv_addr.agh
R_DMA_CH5_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5683] sv_addr.agh
R_DMA_CH5_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5687] sv_addr.agh
R_DMA_CH5_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5685] sv_addr.agh
R_DMA_CH5_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5684] sv_addr.agh
R_DMA_CH5_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5682] sv_addr.agh
R_DMA_CH5_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000015c)
Define [sv_addr.agh, 5664] sv_addr.agh
R_DMA_CH5_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5665] sv_addr.agh
R_DMA_CH5_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5666] sv_addr.agh
R_DMA_CH5_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001b4)
Define [sv_addr.agh, 5676] sv_addr.agh
Use [parport.c, 149] parport.c
Use [serial.c, 355] serial.c
Use [sync_serial.c, 160] sync_serial.c
R_DMA_CH5_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5677] sv_addr.agh
R_DMA_CH5_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5678] sv_addr.agh
R_DMA_CH5_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000150)
Define [sv_addr.agh, 5658] sv_addr.agh
Use [serial.c, 356] serial.c
R_DMA_CH5_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5659] sv_addr.agh
R_DMA_CH5_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5660] sv_addr.agh
R_DMA_CH5_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5661] sv_addr.agh
R_DMA_CH5_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5662] sv_addr.agh
R_DMA_CH5_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000154)
Define [sv_addr.agh, 5668] sv_addr.agh
R_DMA_CH5_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5669] sv_addr.agh
R_DMA_CH5_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5670] sv_addr.agh
R_DMA_CH5_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001e6)
Define [sv_addr.agh, 5699] sv_addr.agh
Use [serial.c, 356] serial.c
R_DMA_CH5_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5700] sv_addr.agh
R_DMA_CH5_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5701] sv_addr.agh
R_DMA_CH6_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000168)
Define [sv_addr.agh, 5717] sv_addr.agh
R_DMA_CH6_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5718] sv_addr.agh
R_DMA_CH6_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5719] sv_addr.agh
R_DMA_CH6_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001e9)
Define [sv_addr.agh, 5734] sv_addr.agh
Use [serial.c, 332] serial.c
R_DMA_CH6_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5739] sv_addr.agh
Macro [serial.c, 972] transmit_chars
Macro [serial.c, 1093] receive_chars
Macro [serial.c, 1567] startup
Macro [serial.c, 1570] startup
R_DMA_CH6_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5741] sv_addr.agh
Macro [serial.c, 972] transmit_chars
Macro [serial.c, 1093] receive_chars
Macro [serial.c, 1567] startup
Macro [serial.c, 1570] startup
R_DMA_CH6_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5742] sv_addr.agh
R_DMA_CH6_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5740] sv_addr.agh
R_DMA_CH6_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5735] sv_addr.agh
Macro [serial.c, 973] transmit_chars
Macro [serial.c, 1094] receive_chars
Macro [serial.c, 1568] startup
Macro [serial.c, 1571] startup
R_DMA_CH6_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5737] sv_addr.agh
Macro [serial.c, 973] transmit_chars
Macro [serial.c, 1094] receive_chars
Macro [serial.c, 1568] startup
Macro [serial.c, 1571] startup
R_DMA_CH6_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5738] sv_addr.agh
R_DMA_CH6_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5736] sv_addr.agh
R_DMA_CH6_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001e8)
Define [sv_addr.agh, 5725] sv_addr.agh
Use [serial.c, 332] serial.c
Use [dmacopy.c, 33] dma_memcpy
R_DMA_CH6_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5726] sv_addr.agh
Macro [serial.c, 1184] receive_chars
Macro [serial.c, 1206] start_receive
Macro [serial.c, 1207] start_receive
Macro [serial.c, 1207] start_receive
Macro [serial.c, 1223] start_receive
Macro [serial.c, 1556] startup
Macro [serial.c, 1557] startup
Macro [serial.c, 1560] startup
Macro [serial.c, 1560] startup
Macro [serial.c, 1563] startup
Macro [serial.c, 1563] startup
Macro [serial.c, 1643] shutdown
Macro [serial.c, 1644] shutdown
Macro [dmacopy.c, 33] dma_memcpy
R_DMA_CH6_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5731] sv_addr.agh
R_DMA_CH6_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5728] sv_addr.agh
R_DMA_CH6_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5732] sv_addr.agh
Macro [serial.c, 1206] start_receive
Macro [serial.c, 1208] start_receive
Macro [serial.c, 1556] startup
Macro [serial.c, 1557] startup
Macro [serial.c, 1561] startup
Macro [serial.c, 1564] startup
Macro [serial.c, 1643] shutdown
Macro [serial.c, 1644] shutdown
R_DMA_CH6_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5730] sv_addr.agh
R_DMA_CH6_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5729] sv_addr.agh
Macro [serial.c, 1184] receive_chars
Macro [serial.c, 1223] start_receive
Macro [dmacopy.c, 33] dma_memcpy
R_DMA_CH6_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5727] sv_addr.agh
Macro [serial.c, 1207] start_receive
Macro [serial.c, 1560] startup
Macro [serial.c, 1563] startup
R_DMA_CH6_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000016c)
Define [sv_addr.agh, 5709] sv_addr.agh
R_DMA_CH6_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5710] sv_addr.agh
R_DMA_CH6_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5711] sv_addr.agh
R_DMA_CH6_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001b8)
Define [sv_addr.agh, 5721] sv_addr.agh
Use [serial.c, 332] serial.c
Use [dmacopy.c, 31] dma_memcpy
R_DMA_CH6_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5722] sv_addr.agh
R_DMA_CH6_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5723] sv_addr.agh
R_DMA_CH6_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000160)
Define [sv_addr.agh, 5703] sv_addr.agh
Use [serial.c, 333] serial.c
R_DMA_CH6_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5704] sv_addr.agh
R_DMA_CH6_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5705] sv_addr.agh
R_DMA_CH6_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5706] sv_addr.agh
R_DMA_CH6_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5707] sv_addr.agh
R_DMA_CH6_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000164)
Define [sv_addr.agh, 5713] sv_addr.agh
R_DMA_CH6_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5714] sv_addr.agh
R_DMA_CH6_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5715] sv_addr.agh
R_DMA_CH6_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001ea)
Define [sv_addr.agh, 5744] sv_addr.agh
Use [serial.c, 333] serial.c
R_DMA_CH6_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5745] sv_addr.agh
R_DMA_CH6_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5746] sv_addr.agh
R_DMA_CH7_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000178)
Define [sv_addr.agh, 5762] sv_addr.agh
R_DMA_CH7_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5763] sv_addr.agh
R_DMA_CH7_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5764] sv_addr.agh
R_DMA_CH7_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001ed)
Define [sv_addr.agh, 5779] sv_addr.agh
Use [serial.c, 334] serial.c
R_DMA_CH7_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5784] sv_addr.agh
R_DMA_CH7_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5786] sv_addr.agh
R_DMA_CH7_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5787] sv_addr.agh
R_DMA_CH7_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5785] sv_addr.agh
R_DMA_CH7_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5780] sv_addr.agh
R_DMA_CH7_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5782] sv_addr.agh
R_DMA_CH7_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5783] sv_addr.agh
R_DMA_CH7_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5781] sv_addr.agh
R_DMA_CH7_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001ec)
Define [sv_addr.agh, 5770] sv_addr.agh
Use [serial.c, 334] serial.c
Use [dmacopy.c, 34] dma_memcpy
Use [dmacopy.c, 36] dma_memcpy
R_DMA_CH7_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5771] sv_addr.agh
Macro [dmacopy.c, 34] dma_memcpy
R_DMA_CH7_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5776] sv_addr.agh
R_DMA_CH7_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5773] sv_addr.agh
R_DMA_CH7_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5777] sv_addr.agh
R_DMA_CH7_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5775] sv_addr.agh
R_DMA_CH7_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5774] sv_addr.agh
Macro [dmacopy.c, 34] dma_memcpy
R_DMA_CH7_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5772] sv_addr.agh
R_DMA_CH7_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000017c)
Define [sv_addr.agh, 5754] sv_addr.agh
R_DMA_CH7_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5755] sv_addr.agh
R_DMA_CH7_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5756] sv_addr.agh
R_DMA_CH7_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001bc)
Define [sv_addr.agh, 5766] sv_addr.agh
Use [serial.c, 334] serial.c
Use [dmacopy.c, 32] dma_memcpy
R_DMA_CH7_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5767] sv_addr.agh
R_DMA_CH7_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5768] sv_addr.agh
R_DMA_CH7_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000170)
Define [sv_addr.agh, 5748] sv_addr.agh
Use [serial.c, 335] serial.c
R_DMA_CH7_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5749] sv_addr.agh
R_DMA_CH7_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5750] sv_addr.agh
R_DMA_CH7_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5751] sv_addr.agh
R_DMA_CH7_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5752] sv_addr.agh
R_DMA_CH7_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000174)
Define [sv_addr.agh, 5758] sv_addr.agh
R_DMA_CH7_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5759] sv_addr.agh
R_DMA_CH7_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5760] sv_addr.agh
R_DMA_CH7_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001ee)
Define [sv_addr.agh, 5789] sv_addr.agh
Use [serial.c, 335] serial.c
R_DMA_CH7_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5790] sv_addr.agh
R_DMA_CH7_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5791] sv_addr.agh
R_DMA_CH8_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000188)
Define [sv_addr.agh, 5807] sv_addr.agh
R_DMA_CH8_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5808] sv_addr.agh
R_DMA_CH8_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5809] sv_addr.agh
R_DMA_CH8_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001f1)
Define [sv_addr.agh, 5824] sv_addr.agh
Use [serial.c, 339] serial.c
Use [sync_serial.c, 142] sync_serial.c
Use [sync_serial.c, 394] sync_serial_ioctl
R_DMA_CH8_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5829] sv_addr.agh
Macro [sync_serial.c, 395] sync_serial_ioctl
R_DMA_CH8_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5831] sv_addr.agh
Macro [sync_serial.c, 395] sync_serial_ioctl
R_DMA_CH8_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5832] sv_addr.agh
R_DMA_CH8_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5830] sv_addr.agh
R_DMA_CH8_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5825] sv_addr.agh
Macro [sync_serial.c, 394] sync_serial_ioctl
R_DMA_CH8_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5827] sv_addr.agh
Macro [sync_serial.c, 394] sync_serial_ioctl
R_DMA_CH8_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5828] sv_addr.agh
R_DMA_CH8_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5826] sv_addr.agh
R_DMA_CH8_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001f0)
Define [sv_addr.agh, 5815] sv_addr.agh
Use [serial.c, 339] serial.c
Use [sync_serial.c, 141] sync_serial.c
Macro [sync_serial.c, 393] sync_serial_ioctl
Macro [sync_serial.c, 393] sync_serial_ioctl
R_DMA_CH8_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5816] sv_addr.agh
R_DMA_CH8_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5821] sv_addr.agh
R_DMA_CH8_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5818] sv_addr.agh
R_DMA_CH8_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5822] sv_addr.agh
R_DMA_CH8_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5820] sv_addr.agh
R_DMA_CH8_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5819] sv_addr.agh
R_DMA_CH8_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5817] sv_addr.agh
R_DMA_CH8_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000018c)
Define [sv_addr.agh, 5799] sv_addr.agh
R_DMA_CH8_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5800] sv_addr.agh
R_DMA_CH8_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5801] sv_addr.agh
R_DMA_CH8_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001c0)
Define [sv_addr.agh, 5811] sv_addr.agh
Use [serial.c, 339] serial.c
Use [sync_serial.c, 140] sync_serial.c
R_DMA_CH8_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5812] sv_addr.agh
R_DMA_CH8_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5813] sv_addr.agh
R_DMA_CH8_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000180)
Define [sv_addr.agh, 5793] sv_addr.agh
Use [serial.c, 340] serial.c
R_DMA_CH8_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5794] sv_addr.agh
R_DMA_CH8_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5795] sv_addr.agh
R_DMA_CH8_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5796] sv_addr.agh
R_DMA_CH8_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5797] sv_addr.agh
R_DMA_CH8_NEP
Declared as: (IO_TYPECAST_UDWORD 0xb00001c0)
Define [sv_addr.agh, 5842] sv_addr.agh
R_DMA_CH8_NEP__nep__BITNR
Declared as: 0
Define [sv_addr.agh, 5843] sv_addr.agh
R_DMA_CH8_NEP__nep__WIDTH
Declared as: 32
Define [sv_addr.agh, 5844] sv_addr.agh
R_DMA_CH8_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000184)
Define [sv_addr.agh, 5803] sv_addr.agh
R_DMA_CH8_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5804] sv_addr.agh
R_DMA_CH8_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5805] sv_addr.agh
R_DMA_CH8_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001f2)
Define [sv_addr.agh, 5834] sv_addr.agh
Use [serial.c, 340] serial.c
R_DMA_CH8_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5835] sv_addr.agh
R_DMA_CH8_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5836] sv_addr.agh
R_DMA_CH8_SUB
Declared as: (IO_TYPECAST_UDWORD 0xb000018c)
Define [sv_addr.agh, 5838] sv_addr.agh
R_DMA_CH8_SUB0_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001e3)
Define [sv_addr.agh, 5856] sv_addr.agh
Use [usb-host.c, 1524] etrax_usb_tx_interrupt
R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5857] sv_addr.agh
Macro [usb-host.c, 1524] etrax_usb_tx_interrupt
R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5860] sv_addr.agh
Macro [usb-host.c, 1524] etrax_usb_tx_interrupt
R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5859] sv_addr.agh
R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5858] sv_addr.agh
R_DMA_CH8_SUB0_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001d3)
Define [sv_addr.agh, 5850] sv_addr.agh
Use [usb-host.c, 380] init_tx_bulk_ep
Use [usb-host.c, 1065] etrax_usb_do_bulk_hw_add
Use [usb-host.c, 1066] etrax_usb_do_bulk_hw_add
R_DMA_CH8_SUB0_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5851] sv_addr.agh
Macro [usb-host.c, 380] init_tx_bulk_ep
Macro [usb-host.c, 1065] etrax_usb_do_bulk_hw_add
Macro [usb-host.c, 1066] etrax_usb_do_bulk_hw_add
R_DMA_CH8_SUB0_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5854] sv_addr.agh
Macro [usb-host.c, 380] init_tx_bulk_ep
Macro [usb-host.c, 1066] etrax_usb_do_bulk_hw_add
R_DMA_CH8_SUB0_CMD__cmd__stop
Declared as: 0
Define [sv_addr.agh, 5853] sv_addr.agh
R_DMA_CH8_SUB0_CMD__cmd__WIDTH
Declared as: 1
Define [sv_addr.agh, 5852] sv_addr.agh
Macro [usb-host.c, 1065] etrax_usb_do_bulk_hw_add
R_DMA_CH8_SUB0_EP
Declared as: (IO_TYPECAST_UDWORD 0xb00001c8)
Define [sv_addr.agh, 5846] sv_addr.agh
Use [usb-host.c, 379] init_tx_bulk_ep
Use [usb-host.c, 1461] etrax_usb_unlink_urb
R_DMA_CH8_SUB0_EP__ep__BITNR
Declared as: 0
Define [sv_addr.agh, 5847] sv_addr.agh
R_DMA_CH8_SUB0_EP__ep__WIDTH
Declared as: 32
Define [sv_addr.agh, 5848] sv_addr.agh
R_DMA_CH8_SUB1_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001e7)
Define [sv_addr.agh, 5872] sv_addr.agh
Use [usb-host.c, 1528] etrax_usb_tx_interrupt
R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5873] sv_addr.agh
Macro [usb-host.c, 1528] etrax_usb_tx_interrupt
R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5876] sv_addr.agh
Macro [usb-host.c, 1528] etrax_usb_tx_interrupt
R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5875] sv_addr.agh
R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5874] sv_addr.agh
R_DMA_CH8_SUB1_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001d7)
Define [sv_addr.agh, 5866] sv_addr.agh
Use [usb-host.c, 354] init_tx_ctrl_ep
Use [usb-host.c, 1344] etrax_usb_do_ctrl_hw_add
Use [usb-host.c, 1345] etrax_usb_do_ctrl_hw_add
R_DMA_CH8_SUB1_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5867] sv_addr.agh
Macro [usb-host.c, 354] init_tx_ctrl_ep
Macro [usb-host.c, 1344] etrax_usb_do_ctrl_hw_add
Macro [usb-host.c, 1345] etrax_usb_do_ctrl_hw_add
R_DMA_CH8_SUB1_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5870] sv_addr.agh
Macro [usb-host.c, 354] init_tx_ctrl_ep
Macro [usb-host.c, 1345] etrax_usb_do_ctrl_hw_add
R_DMA_CH8_SUB1_CMD__cmd__stop
Declared as: 0
Define [sv_addr.agh, 5869] sv_addr.agh
R_DMA_CH8_SUB1_CMD__cmd__WIDTH
Declared as: 1
Define [sv_addr.agh, 5868] sv_addr.agh
Macro [usb-host.c, 1344] etrax_usb_do_ctrl_hw_add
R_DMA_CH8_SUB1_EP
Declared as: (IO_TYPECAST_UDWORD 0xb00001cc)
Define [sv_addr.agh, 5862] sv_addr.agh
Use [usb-host.c, 353] init_tx_ctrl_ep
Use [usb-host.c, 1455] etrax_usb_unlink_urb
R_DMA_CH8_SUB1_EP__ep__BITNR
Declared as: 0
Define [sv_addr.agh, 5863] sv_addr.agh
R_DMA_CH8_SUB1_EP__ep__WIDTH
Declared as: 32
Define [sv_addr.agh, 5864] sv_addr.agh
R_DMA_CH8_SUB2_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001eb)
Define [sv_addr.agh, 5888] sv_addr.agh
Use [usb-host.c, 1532] etrax_usb_tx_interrupt
R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5889] sv_addr.agh
Macro [usb-host.c, 1532] etrax_usb_tx_interrupt
R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5892] sv_addr.agh
Macro [usb-host.c, 1532] etrax_usb_tx_interrupt
R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5891] sv_addr.agh
R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5890] sv_addr.agh
R_DMA_CH8_SUB2_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001db)
Define [sv_addr.agh, 5882] sv_addr.agh
Use [usb-host.c, 418] init_tx_intr_ep
Use [usb-host.c, 459] etrax_usb_unlink_intr_urb
Use [usb-host.c, 486] etrax_usb_unlink_intr_urb
Use [usb-host.c, 636] etrax_usb_submit_intr_urb
R_DMA_CH8_SUB2_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5883] sv_addr.agh
Macro [usb-host.c, 418] init_tx_intr_ep
Macro [usb-host.c, 459] etrax_usb_unlink_intr_urb
Macro [usb-host.c, 486] etrax_usb_unlink_intr_urb
Macro [usb-host.c, 636] etrax_usb_submit_intr_urb
R_DMA_CH8_SUB2_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5886] sv_addr.agh
Macro [usb-host.c, 418] init_tx_intr_ep
Macro [usb-host.c, 486] etrax_usb_unlink_intr_urb
Macro [usb-host.c, 636] etrax_usb_submit_intr_urb
R_DMA_CH8_SUB2_CMD__cmd__stop
Declared as: 0
Define [sv_addr.agh, 5885] sv_addr.agh
Macro [usb-host.c, 459] etrax_usb_unlink_intr_urb
R_DMA_CH8_SUB2_CMD__cmd__WIDTH
Declared as: 1
Define [sv_addr.agh, 5884] sv_addr.agh
R_DMA_CH8_SUB2_EP
Declared as: (IO_TYPECAST_UDWORD 0xb00001f8)
Define [sv_addr.agh, 5878] sv_addr.agh
Use [usb-host.c, 417] init_tx_intr_ep
Use [usb-host.c, 485] etrax_usb_unlink_intr_urb
Use [usb-host.c, 501] etrax_usb_do_intr_recover
R_DMA_CH8_SUB2_EP__ep__BITNR
Declared as: 0
Define [sv_addr.agh, 5879] sv_addr.agh
R_DMA_CH8_SUB2_EP__ep__WIDTH
Declared as: 32
Define [sv_addr.agh, 5880] sv_addr.agh
R_DMA_CH8_SUB3_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001ef)
Define [sv_addr.agh, 5904] sv_addr.agh
Use [usb-host.c, 1536] etrax_usb_tx_interrupt
R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5905] sv_addr.agh
Macro [usb-host.c, 1536] etrax_usb_tx_interrupt
R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5908] sv_addr.agh
Macro [usb-host.c, 1536] etrax_usb_tx_interrupt
R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5907] sv_addr.agh
R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5906] sv_addr.agh
R_DMA_CH8_SUB3_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001df)
Define [sv_addr.agh, 5898] sv_addr.agh
R_DMA_CH8_SUB3_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5899] sv_addr.agh
R_DMA_CH8_SUB3_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5902] sv_addr.agh
R_DMA_CH8_SUB3_CMD__cmd__stop
Declared as: 0
Define [sv_addr.agh, 5901] sv_addr.agh
R_DMA_CH8_SUB3_CMD__cmd__WIDTH
Declared as: 1
Define [sv_addr.agh, 5900] sv_addr.agh
R_DMA_CH8_SUB3_EP
Declared as: (IO_TYPECAST_UDWORD 0xb00001fc)
Define [sv_addr.agh, 5894] sv_addr.agh
R_DMA_CH8_SUB3_EP__ep__BITNR
Declared as: 0
Define [sv_addr.agh, 5895] sv_addr.agh
R_DMA_CH8_SUB3_EP__ep__WIDTH
Declared as: 32
Define [sv_addr.agh, 5896] sv_addr.agh
R_DMA_CH8_SUB__sub__BITNR
Declared as: 0
Define [sv_addr.agh, 5839] sv_addr.agh
R_DMA_CH8_SUB__sub__WIDTH
Declared as: 32
Define [sv_addr.agh, 5840] sv_addr.agh
R_DMA_CH9_BUF
Declared as: (IO_TYPECAST_UDWORD 0xb0000198)
Define [sv_addr.agh, 5924] sv_addr.agh
R_DMA_CH9_BUF__buf__BITNR
Declared as: 0
Define [sv_addr.agh, 5925] sv_addr.agh
R_DMA_CH9_BUF__buf__WIDTH
Declared as: 32
Define [sv_addr.agh, 5926] sv_addr.agh
R_DMA_CH9_CLR_INTR
Declared as: (IO_TYPECAST_BYTE 0xb00001f5)
Define [sv_addr.agh, 5941] sv_addr.agh
Use [serial.c, 341] serial.c
Use [sync_serial.c, 145] sync_serial.c
Use [usb-host.c, 1548] etrax_usb_rx_interrupt
R_DMA_CH9_CLR_INTR__clr_descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5946] sv_addr.agh
R_DMA_CH9_CLR_INTR__clr_descr__do
Declared as: 1
Define [sv_addr.agh, 5948] sv_addr.agh
R_DMA_CH9_CLR_INTR__clr_descr__dont
Declared as: 0
Define [sv_addr.agh, 5949] sv_addr.agh
R_DMA_CH9_CLR_INTR__clr_descr__WIDTH
Declared as: 1
Define [sv_addr.agh, 5947] sv_addr.agh
R_DMA_CH9_CLR_INTR__clr_eop__BITNR
Declared as: 1
Define [sv_addr.agh, 5942] sv_addr.agh
Macro [usb-host.c, 1548] etrax_usb_rx_interrupt
R_DMA_CH9_CLR_INTR__clr_eop__do
Declared as: 1
Define [sv_addr.agh, 5944] sv_addr.agh
Macro [usb-host.c, 1548] etrax_usb_rx_interrupt
R_DMA_CH9_CLR_INTR__clr_eop__dont
Declared as: 0
Define [sv_addr.agh, 5945] sv_addr.agh
R_DMA_CH9_CLR_INTR__clr_eop__WIDTH
Declared as: 1
Define [sv_addr.agh, 5943] sv_addr.agh
R_DMA_CH9_CMD
Declared as: (IO_TYPECAST_BYTE 0xb00001f4)
Define [sv_addr.agh, 5932] sv_addr.agh
Use [serial.c, 341] serial.c
Use [sync_serial.c, 144] sync_serial.c
Use [usb-host.c, 328] init_rx_buffers
R_DMA_CH9_CMD__cmd__BITNR
Declared as: 0
Define [sv_addr.agh, 5933] sv_addr.agh
Macro [usb-host.c, 328] init_rx_buffers
R_DMA_CH9_CMD__cmd__continue
Declared as: 3
Define [sv_addr.agh, 5938] sv_addr.agh
R_DMA_CH9_CMD__cmd__hold
Declared as: 0
Define [sv_addr.agh, 5935] sv_addr.agh
R_DMA_CH9_CMD__cmd__reset
Declared as: 4
Define [sv_addr.agh, 5939] sv_addr.agh
R_DMA_CH9_CMD__cmd__restart
Declared as: 3
Define [sv_addr.agh, 5937] sv_addr.agh
R_DMA_CH9_CMD__cmd__start
Declared as: 1
Define [sv_addr.agh, 5936] sv_addr.agh
Macro [usb-host.c, 328] init_rx_buffers
R_DMA_CH9_CMD__cmd__WIDTH
Declared as: 3
Define [sv_addr.agh, 5934] sv_addr.agh
R_DMA_CH9_DESCR
Declared as: (IO_TYPECAST_UDWORD 0xb000019c)
Define [sv_addr.agh, 5916] sv_addr.agh
R_DMA_CH9_DESCR__descr__BITNR
Declared as: 0
Define [sv_addr.agh, 5917] sv_addr.agh
R_DMA_CH9_DESCR__descr__WIDTH
Declared as: 32
Define [sv_addr.agh, 5918] sv_addr.agh
R_DMA_CH9_FIRST
Declared as: (IO_TYPECAST_UDWORD 0xb00001c4)
Define [sv_addr.agh, 5928] sv_addr.agh
Use [serial.c, 341] serial.c
Use [sync_serial.c, 143] sync_serial.c
Use [usb-host.c, 327] init_rx_buffers
R_DMA_CH9_FIRST__first__BITNR
Declared as: 0
Define [sv_addr.agh, 5929] sv_addr.agh
R_DMA_CH9_FIRST__first__WIDTH
Declared as: 32
Define [sv_addr.agh, 5930] sv_addr.agh
R_DMA_CH9_HWSW
Declared as: (IO_TYPECAST_UDWORD 0xb0000190)
Define [sv_addr.agh, 5910] sv_addr.agh
Use [serial.c, 342] serial.c
R_DMA_CH9_HWSW__hw__BITNR
Declared as: 16
Define [sv_addr.agh, 5911] sv_addr.agh
R_DMA_CH9_HWSW__hw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5912] sv_addr.agh
R_DMA_CH9_HWSW__sw__BITNR
Declared as: 0
Define [sv_addr.agh, 5913] sv_addr.agh
R_DMA_CH9_HWSW__sw__WIDTH
Declared as: 16
Define [sv_addr.agh, 5914] sv_addr.agh
R_DMA_CH9_NEXT
Declared as: (IO_TYPECAST_UDWORD 0xb0000194)
Define [sv_addr.agh, 5920] sv_addr.agh
R_DMA_CH9_NEXT__next__BITNR
Declared as: 0
Define [sv_addr.agh, 5921] sv_addr.agh
R_DMA_CH9_NEXT__next__WIDTH
Declared as: 32
Define [sv_addr.agh, 5922] sv_addr.agh
R_DMA_CH9_STATUS
Declared as: (IO_TYPECAST_RO_BYTE 0xb00001f6)
Define [sv_addr.agh, 5951] sv_addr.agh
Use [serial.c, 342] serial.c
R_DMA_CH9_STATUS__avail__BITNR
Declared as: 0
Define [sv_addr.agh, 5952] sv_addr.agh
R_DMA_CH9_STATUS__avail__WIDTH
Declared as: 7
Define [sv_addr.agh, 5953] sv_addr.agh
R_DRAM_CONFIG
Declared as: (IO_TYPECAST_UDWORD 0xb000000c)
Define [sv_addr.agh, 179] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bank0
Declared as: 0
Define [sv_addr.agh, 260] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bank1
Declared as: 1
Define [sv_addr.agh, 261] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit10
Declared as: 10
Define [sv_addr.agh, 263] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit11
Declared as: 11
Define [sv_addr.agh, 264] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit12
Declared as: 12
Define [sv_addr.agh, 265] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit13
Declared as: 13
Define [sv_addr.agh, 266] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit14
Declared as: 14
Define [sv_addr.agh, 267] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit15
Declared as: 15
Define [sv_addr.agh, 268] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit16
Declared as: 16
Define [sv_addr.agh, 269] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit17
Declared as: 17
Define [sv_addr.agh, 270] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit18
Declared as: 18
Define [sv_addr.agh, 271] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit19
Declared as: 19
Define [sv_addr.agh, 272] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit20
Declared as: 20
Define [sv_addr.agh, 273] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit21
Declared as: 21
Define [sv_addr.agh, 274] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit22
Declared as: 22
Define [sv_addr.agh, 275] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit23
Declared as: 23
Define [sv_addr.agh, 276] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit24
Declared as: 24
Define [sv_addr.agh, 277] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit25
Declared as: 25
Define [sv_addr.agh, 278] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit26
Declared as: 26
Define [sv_addr.agh, 279] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit27
Declared as: 27
Define [sv_addr.agh, 280] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit28
Declared as: 28
Define [sv_addr.agh, 281] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit29
Declared as: 29
Define [sv_addr.agh, 282] sv_addr.agh
R_DRAM_CONFIG__bank01sel__bit9
Declared as: 9
Define [sv_addr.agh, 262] sv_addr.agh
R_DRAM_CONFIG__bank01sel__BITNR
Declared as: 0
Define [sv_addr.agh, 258] sv_addr.agh
R_DRAM_CONFIG__bank01sel__WIDTH
Declared as: 5
Define [sv_addr.agh, 259] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bank0
Declared as: 0
Define [sv_addr.agh, 233] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bank1
Declared as: 1
Define [sv_addr.agh, 234] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit10
Declared as: 10
Define [sv_addr.agh, 236] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit11
Declared as: 11
Define [sv_addr.agh, 237] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit12
Declared as: 12
Define [sv_addr.agh, 238] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit13
Declared as: 13
Define [sv_addr.agh, 239] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit14
Declared as: 14
Define [sv_addr.agh, 240] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit15
Declared as: 15
Define [sv_addr.agh, 241] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit16
Declared as: 16
Define [sv_addr.agh, 242] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit17
Declared as: 17
Define [sv_addr.agh, 243] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit18
Declared as: 18
Define [sv_addr.agh, 244] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit19
Declared as: 19
Define [sv_addr.agh, 245] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit20
Declared as: 20
Define [sv_addr.agh, 246] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit21
Declared as: 21
Define [sv_addr.agh, 247] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit22
Declared as: 22
Define [sv_addr.agh, 248] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit23
Declared as: 23
Define [sv_addr.agh, 249] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit24
Declared as: 24
Define [sv_addr.agh, 250] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit25
Declared as: 25
Define [sv_addr.agh, 251] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit26
Declared as: 26
Define [sv_addr.agh, 252] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit27
Declared as: 27
Define [sv_addr.agh, 253] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit28
Declared as: 28
Define [sv_addr.agh, 254] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit29
Declared as: 29
Define [sv_addr.agh, 255] sv_addr.agh
R_DRAM_CONFIG__bank23sel__bit9
Declared as: 9
Define [sv_addr.agh, 235] sv_addr.agh
R_DRAM_CONFIG__bank23sel__BITNR
Declared as: 8
Define [sv_addr.agh, 231] sv_addr.agh
R_DRAM_CONFIG__bank23sel__WIDTH
Declared as: 5
Define [sv_addr.agh, 232] sv_addr.agh
R_DRAM_CONFIG__c__bank
Declared as: 1
Define [sv_addr.agh, 199] sv_addr.agh
R_DRAM_CONFIG__c__BITNR
Declared as: 22
Define [sv_addr.agh, 196] sv_addr.agh
R_DRAM_CONFIG__c__byte
Declared as: 0
Define [sv_addr.agh, 198] sv_addr.agh
R_DRAM_CONFIG__c__WIDTH
Declared as: 1
Define [sv_addr.agh, 197] sv_addr.agh
R_DRAM_CONFIG__ca0__BITNR
Declared as: 5
Define [sv_addr.agh, 256] sv_addr.agh
R_DRAM_CONFIG__ca0__WIDTH
Declared as: 3
Define [sv_addr.agh, 257] sv_addr.agh
R_DRAM_CONFIG__ca1__BITNR
Declared as: 13
Define [sv_addr.agh, 229] sv_addr.agh
R_DRAM_CONFIG__ca1__WIDTH
Declared as: 3
Define [sv_addr.agh, 230] sv_addr.agh
R_DRAM_CONFIG__e__BITNR
Declared as: 21
Define [sv_addr.agh, 200] sv_addr.agh
R_DRAM_CONFIG__e__edo
Declared as: 1
Define [sv_addr.agh, 203] sv_addr.agh
R_DRAM_CONFIG__e__fast
Declared as: 0
Define [sv_addr.agh, 202] sv_addr.agh
R_DRAM_CONFIG__e__WIDTH
Declared as: 1
Define [sv_addr.agh, 201] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit10
Declared as: 10
Define [sv_addr.agh, 209] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit11
Declared as: 11
Define [sv_addr.agh, 210] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit12
Declared as: 12
Define [sv_addr.agh, 211] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit13
Declared as: 13
Define [sv_addr.agh, 212] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit14
Declared as: 14
Define [sv_addr.agh, 213] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit15
Declared as: 15
Define [sv_addr.agh, 214] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit16
Declared as: 16
Define [sv_addr.agh, 215] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit17
Declared as: 17
Define [sv_addr.agh, 216] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit18
Declared as: 18
Define [sv_addr.agh, 217] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit19
Declared as: 19
Define [sv_addr.agh, 218] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit20
Declared as: 20
Define [sv_addr.agh, 219] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit21
Declared as: 21
Define [sv_addr.agh, 220] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit22
Declared as: 22
Define [sv_addr.agh, 221] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit23
Declared as: 23
Define [sv_addr.agh, 222] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit24
Declared as: 24
Define [sv_addr.agh, 223] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit25
Declared as: 25
Define [sv_addr.agh, 224] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit26
Declared as: 26
Define [sv_addr.agh, 225] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit27
Declared as: 27
Define [sv_addr.agh, 226] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit28
Declared as: 28
Define [sv_addr.agh, 227] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit29
Declared as: 29
Define [sv_addr.agh, 228] sv_addr.agh
R_DRAM_CONFIG__group_sel__bit9
Declared as: 9
Define [sv_addr.agh, 208] sv_addr.agh
R_DRAM_CONFIG__group_sel__BITNR
Declared as: 16
Define [sv_addr.agh, 204] sv_addr.agh
R_DRAM_CONFIG__group_sel__grp0
Declared as: 0
Define [sv_addr.agh, 206] sv_addr.agh
R_DRAM_CONFIG__group_sel__grp1
Declared as: 1
Define [sv_addr.agh, 207] sv_addr.agh
R_DRAM_CONFIG__group_sel__WIDTH
Declared as: 5
Define [sv_addr.agh, 205] sv_addr.agh
R_DRAM_CONFIG__sh0__BITNR
Declared as: 24
Define [sv_addr.agh, 190] sv_addr.agh
R_DRAM_CONFIG__sh0__WIDTH
Declared as: 3
Define [sv_addr.agh, 191] sv_addr.agh
R_DRAM_CONFIG__sh1__BITNR
Declared as: 27
Define [sv_addr.agh, 188] sv_addr.agh
R_DRAM_CONFIG__sh1__WIDTH
Declared as: 3
Define [sv_addr.agh, 189] sv_addr.agh
R_DRAM_CONFIG__w__BITNR
Declared as: 23
Define [sv_addr.agh, 192] sv_addr.agh
R_DRAM_CONFIG__w__bw16
Declared as: 0
Define [sv_addr.agh, 194] sv_addr.agh
R_DRAM_CONFIG__w__bw32
Declared as: 1
Define [sv_addr.agh, 195] sv_addr.agh
R_DRAM_CONFIG__w__WIDTH
Declared as: 1
Define [sv_addr.agh, 193] sv_addr.agh
R_DRAM_CONFIG__wmm0__BITNR
Declared as: 30
Define [sv_addr.agh, 184] sv_addr.agh
R_DRAM_CONFIG__wmm0__norm
Declared as: 0
Define [sv_addr.agh, 187] sv_addr.agh
R_DRAM_CONFIG__wmm0__WIDTH
Declared as: 1
Define [sv_addr.agh, 185] sv_addr.agh
R_DRAM_CONFIG__wmm0__wmm
Declared as: 1
Define [sv_addr.agh, 186] sv_addr.agh
R_DRAM_CONFIG__wmm1__BITNR
Declared as: 31
Define [sv_addr.agh, 180] sv_addr.agh
R_DRAM_CONFIG__wmm1__norm
Declared as: 0
Define [sv_addr.agh, 183] sv_addr.agh
R_DRAM_CONFIG__wmm1__WIDTH
Declared as: 1
Define [sv_addr.agh, 181] sv_addr.agh
R_DRAM_CONFIG__wmm1__wmm
Declared as: 1
Define [sv_addr.agh, 182] sv_addr.agh
R_DRAM_TIMING
Declared as: (IO_TYPECAST_UDWORD 0xb0000008)
Define [sv_addr.agh, 105] sv_addr.agh
R_DRAM_TIMING__c__BITNR
Declared as: 6
Define [sv_addr.agh, 126] sv_addr.agh
R_DRAM_TIMING__c__ext
Declared as: 1
Define [sv_addr.agh, 129] sv_addr.agh
R_DRAM_TIMING__c__norm
Declared as: 0
Define [sv_addr.agh, 128] sv_addr.agh
R_DRAM_TIMING__c__WIDTH
Declared as: 1
Define [sv_addr.agh, 127] sv_addr.agh
R_DRAM_TIMING__cp__BITNR
Declared as: 2
Define [sv_addr.agh, 132] sv_addr.agh
R_DRAM_TIMING__cp__WIDTH
Declared as: 2
Define [sv_addr.agh, 133] sv_addr.agh
R_DRAM_TIMING__cw__BITNR
Declared as: 0
Define [sv_addr.agh, 134] sv_addr.agh
R_DRAM_TIMING__cw__WIDTH
Declared as: 2
Define [sv_addr.agh, 135] sv_addr.agh
R_DRAM_TIMING__cz__BITNR
Declared as: 4
Define [sv_addr.agh, 130] sv_addr.agh
R_DRAM_TIMING__cz__WIDTH
Declared as: 2
Define [sv_addr.agh, 131] sv_addr.agh
R_DRAM_TIMING__ref__BITNR
Declared as: 14
Define [sv_addr.agh, 110] sv_addr.agh
R_DRAM_TIMING__ref__disable
Declared as: 3
Define [sv_addr.agh, 115] sv_addr.agh
R_DRAM_TIMING__ref__e13us
Declared as: 1
Define [sv_addr.agh, 113] sv_addr.agh
R_DRAM_TIMING__ref__e52us
Declared as: 0
Define [sv_addr.agh, 112] sv_addr.agh
R_DRAM_TIMING__ref__e8700ns
Declared as: 2
Define [sv_addr.agh, 114] sv_addr.agh
R_DRAM_TIMING__ref__WIDTH
Declared as: 2
Define [sv_addr.agh, 111] sv_addr.agh
R_DRAM_TIMING__rh__BITNR
Declared as: 8
Define [sv_addr.agh, 120] sv_addr.agh
R_DRAM_TIMING__rh__WIDTH
Declared as: 2
Define [sv_addr.agh, 121] sv_addr.agh
R_DRAM_TIMING__rp__BITNR
Declared as: 12
Define [sv_addr.agh, 116] sv_addr.agh
R_DRAM_TIMING__rp__WIDTH
Declared as: 2
Define [sv_addr.agh, 117] sv_addr.agh
R_DRAM_TIMING__rs__BITNR
Declared as: 10
Define [sv_addr.agh, 118] sv_addr.agh
R_DRAM_TIMING__rs__WIDTH
Declared as: 2
Define [sv_addr.agh, 119] sv_addr.agh
R_DRAM_TIMING__sdram__BITNR
Declared as: 31
Define [sv_addr.agh, 106] sv_addr.agh
R_DRAM_TIMING__sdram__disable
Declared as: 0
Define [sv_addr.agh, 109] sv_addr.agh
R_DRAM_TIMING__sdram__enable
Declared as: 1
Define [sv_addr.agh, 108] sv_addr.agh
R_DRAM_TIMING__sdram__WIDTH
Declared as: 1
Define [sv_addr.agh, 107] sv_addr.agh
R_DRAM_TIMING__w__BITNR
Declared as: 7
Define [sv_addr.agh, 122] sv_addr.agh
R_DRAM_TIMING__w__ext
Declared as: 1
Define [sv_addr.agh, 125] sv_addr.agh
R_DRAM_TIMING__w__norm
Declared as: 0
Define [sv_addr.agh, 124] sv_addr.agh
R_DRAM_TIMING__w__WIDTH
Declared as: 1
Define [sv_addr.agh, 123] sv_addr.agh
r_dtr
Declared as: (unsigned char)inb((x))
Define [ppa.h, 136]