File: /usr/src/linux-2.4.7/drivers/scsi/3w-xxxx.h

1     /* 
2        3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
3        
4        Written By: Adam Radford <linux@3ware.com>
5        Modifications By: Joel Jacobson <linux@3ware.com>
6        		     Arnaldo Carvalho de Melo <acme@conectiva.com.br>
7     
8        Copyright (C) 1999-2001 3ware Inc.
9     
10        Kernel compatablity By:	Andre Hedrick <andre@suse.com>
11        Non-Copyright (C) 2000	Andre Hedrick <andre@suse.com>
12     
13        This program is free software; you can redistribute it and/or modify
14        it under the terms of the GNU General Public License as published by
15        the Free Software Foundation; version 2 of the License.
16     
17        This program is distributed in the hope that it will be useful,           
18        but WITHOUT ANY WARRANTY; without even the implied warranty of            
19        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
20        GNU General Public License for more details.                              
21     
22        NO WARRANTY                                                               
23        THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR        
24        CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT      
25        LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,      
26        MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is    
27        solely responsible for determining the appropriateness of using and       
28        distributing the Program and assumes all risks associated with its        
29        exercise of rights under this Agreement, including but not limited to     
30        the risks and costs of program errors, damage to or loss of data,         
31        programs or equipment, and unavailability or interruption of operations.  
32     
33        DISCLAIMER OF LIABILITY                                                   
34        NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY   
35        DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL        
36        DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND   
37        ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR     
38        TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE    
39        USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED  
40        HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES             
41     
42        You should have received a copy of the GNU General Public License         
43        along with this program; if not, write to the Free Software               
44        Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
45     
46        Bugs/Comments/Suggestions should be mailed to:                            
47        linux@3ware.com
48        
49        For more information, goto:
50        http://www.3ware.com
51     */
52     
53     #ifndef _3W_XXXX_H
54     #define _3W_XXXX_H
55     
56     #include <linux/version.h>
57     #include <linux/types.h>
58     #include <linux/kdev_t.h>
59     
60     /* Control register bit definitions */
61     #define TW_CONTROL_CLEAR_HOST_INTERRUPT	       0x00080000
62     #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
63     #define TW_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
64     #define TW_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
65     #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
66     #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
67     #define TW_CONTROL_CLEAR_ERROR_STATUS	       0x00000200
68     #define TW_CONTROL_ISSUE_SOFT_RESET	       0x00000100
69     #define TW_CONTROL_ENABLE_INTERRUPTS	       0x00000080
70     #define TW_CONTROL_DISABLE_INTERRUPTS	       0x00000040
71     #define TW_CONTROL_ISSUE_HOST_INTERRUPT	       0x00000020
72     
73     /* Status register bit definitions */
74     #define TW_STATUS_MAJOR_VERSION_MASK	       0xF0000000
75     #define TW_STATUS_MINOR_VERSION_MASK	       0x0F000000
76     #define TW_STATUS_PCI_PARITY_ERROR	       0x00800000
77     #define TW_STATUS_QUEUE_ERROR		       0x00400000
78     #define TW_STATUS_MICROCONTROLLER_ERROR	       0x00200000
79     #define TW_STATUS_PCI_ABORT		       0x00100000
80     #define TW_STATUS_HOST_INTERRUPT	       0x00080000
81     #define TW_STATUS_ATTENTION_INTERRUPT	       0x00040000
82     #define TW_STATUS_COMMAND_INTERRUPT	       0x00020000
83     #define TW_STATUS_RESPONSE_INTERRUPT	       0x00010000
84     #define TW_STATUS_COMMAND_QUEUE_FULL	       0x00008000
85     #define TW_STATUS_RESPONSE_QUEUE_EMPTY	       0x00004000
86     #define TW_STATUS_MICROCONTROLLER_READY	       0x00002000
87     #define TW_STATUS_COMMAND_QUEUE_EMPTY	       0x00001000
88     #define TW_STATUS_ALL_INTERRUPTS	       0x000F0000
89     #define TW_STATUS_CLEARABLE_BITS	       0x00D00000
90     #define TW_STATUS_EXPECTED_BITS		       0x00002000
91     #define TW_STATUS_UNEXPECTED_BITS	       0x00F80000
92     
93     /* RESPONSE QUEUE BIT DEFINITIONS */
94     #define TW_RESPONSE_ID_MASK		       0x00000FF0
95     
96     /* PCI related defines */
97     #define TW_IO_ADDRESS_RANGE		       0xD
98     #define TW_DEVICE_NAME			       "3ware Storage Controller"
99     #define TW_VENDOR_ID (0x13C1)	/* 3ware */
100     #define TW_DEVICE_ID (0x1000)	/* Storage Controller */
101     #define TW_DEVICE_ID2 (0x1001)  /* 7000 series controller */
102     #define TW_NUMDEVICES 2
103     
104     /* Command packet opcodes */
105     #define TW_OP_NOP	      0x0
106     #define TW_OP_INIT_CONNECTION 0x1
107     #define TW_OP_READ	      0x2
108     #define TW_OP_WRITE	      0x3
109     #define TW_OP_VERIFY	      0x4
110     #define TW_OP_GET_PARAM	      0x12
111     #define TW_OP_SET_PARAM	      0x13
112     #define TW_OP_SECTOR_INFO     0x1a
113     #define TW_OP_AEN_LISTEN      0x1c
114     #define TW_CMD_PACKET         0x1d
115     
116     /* Asynchronous Event Notification (AEN) Codes */
117     #define TW_AEN_QUEUE_EMPTY       0x0000
118     #define TW_AEN_SOFT_RESET        0x0001
119     #define TW_AEN_DEGRADED_MIRROR   0x0002
120     #define TW_AEN_CONTROLLER_ERROR  0x0003
121     #define TW_AEN_REBUILD_FAIL      0x0004
122     #define TW_AEN_REBUILD_DONE      0x0005
123     #define TW_AEN_QUEUE_FULL        0x00ff
124     #define TW_AEN_TABLE_UNDEFINED   0x15
125     
126     /* Misc defines */
127     #define TW_ALIGNMENT			      0x200 /* 16 D-WORDS */
128     #define TW_MAX_UNITS			      16
129     #define TW_COMMAND_ALIGNMENT_MASK	      0x1ff
130     #define TW_INIT_MESSAGE_CREDITS		      0x100
131     #define TW_INIT_COMMAND_PACKET_SIZE	      0x3
132     #define TW_POLL_MAX_RETRIES        	      20000
133     #define TW_MAX_SGL_LENGTH		      62
134     #define TW_Q_LENGTH			      16
135     #define TW_Q_START			      0
136     #define TW_MAX_SLOT			      32
137     #define TW_MAX_PCI_BUSES		      255
138     #define TW_MAX_RESET_TRIES		      3
139     #define TW_UNIT_INFORMATION_TABLE_BASE	      0x300
140     #define TW_MAX_CMDS_PER_LUN		      (TW_Q_LENGTH-2)/TW_MAX_UNITS
141     #define TW_BLOCK_SIZE			      0x200 /* 512-byte blocks */
142     #define TW_IOCTL                              0x80
143     #define TW_MAX_AEN_TRIES                      100
144     #define TW_UNIT_ONLINE                        1
145     #define TW_IN_INTR                            1
146     
147     /* Macros */
148     #define TW_STATUS_ERRORS(x) \
149     	(((x & TW_STATUS_PCI_ABORT) || \
150     	(x & TW_STATUS_PCI_PARITY_ERROR) || \
151     	(x & TW_STATUS_QUEUE_ERROR) || \
152     	(x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
153     	(x & TW_STATUS_MICROCONTROLLER_READY))
154     
155     #ifdef TW_DEBUG
156     #define dprintk(msg...) printk(msg)
157     #else
158     #define dprintk(msg...) do { } while(0);
159     #endif
160     
161     /* Scatter Gather List Entry */
162     typedef struct TAG_TW_SG_Entry {
163     	unsigned long address;
164     	unsigned long length;
165     } TW_SG_Entry;
166     
167     typedef unsigned char TW_Sector[512];
168     
169     /* Command Packet */
170     typedef struct TW_Command {
171     	/* First DWORD */
172     	struct {
173     		unsigned char opcode:5;
174     		unsigned char sgl_offset:3;
175     	} byte0;
176     	unsigned char size;
177     	unsigned char request_id;
178     	struct {
179     		unsigned char unit:4;
180     		unsigned char host_id:4;
181     	} byte3;
182     	/* Second DWORD */
183     	unsigned char status;
184     	unsigned char flags;
185     	union {
186     		unsigned short block_count;
187     		unsigned short parameter_count;
188     		unsigned short message_credits;
189     	} byte6;
190     	union {
191     		struct {
192     			unsigned long lba;
193     			TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
194     			unsigned long padding;	/* pad to 512 bytes */
195     		} io;
196     		struct {
197     			TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
198     			unsigned long padding[2];
199     		} param;
200     		struct {
201     			unsigned long response_queue_pointer;
202     			unsigned long padding[125];
203     		} init_connection;
204     		struct {
205     			char version[504];
206     		} ioctl_miniport_version;
207     	} byte8;
208     } TW_Command;
209     
210     typedef struct TAG_TW_Ioctl {
211     	int buffer;
212     	unsigned char opcode;
213     	unsigned short table_id;
214     	unsigned char parameter_id;
215     	unsigned char parameter_size_bytes;
216     	unsigned char data[1];
217     } TW_Ioctl;
218     
219     /* GetParam descriptor */
220     typedef struct {
221     	unsigned short	table_id;
222     	unsigned char	parameter_id;
223     	unsigned char	parameter_size_bytes;
224     	unsigned char	data[1];
225     } TW_Param, *PTW_Param;
226     
227     /* Response queue */
228     typedef union TAG_TW_Response_Queue {
229     	struct {
230     		u32 undefined_1: 4;
231     		u32 response_id: 8;
232     		u32 undefined_2: 20;
233     	} u;
234     	u32 value;
235     } TW_Response_Queue;
236     
237     typedef struct TAG_TW_Registers {
238     	u32 base_addr;
239     	u32 control_reg_addr;
240     	u32 status_reg_addr;
241     	u32 command_que_addr;
242     	u32 response_que_addr;
243     } TW_Registers;
244     
245     typedef struct TAG_TW_Info {
246     	char *buffer;
247     	int length;
248     	int offset;
249     	int position;
250     } TW_Info;
251     
252     typedef enum TAG_TW_Cmd_State {
253     	TW_S_INITIAL,		/* Initial state */
254     	TW_S_STARTED,		/* Id in use */
255     	TW_S_POSTED,		/* Posted to the controller */
256     	TW_S_PENDING,		/* Waiting to be posted in isr */
257     	TW_S_COMPLETED,		/* Completed by isr */
258     	TW_S_FINISHED,		/* I/O completely done */
259     } TW_Cmd_State;
260     
261     typedef struct TAG_TW_Device_Extension {
262     	TW_Registers		registers;
263     	u32			*alignment_virtual_address[TW_Q_LENGTH];
264     	u32			alignment_physical_address[TW_Q_LENGTH];
265     	u32			*bounce_buffer[TW_Q_LENGTH];
266     	int			is_unit_present[TW_MAX_UNITS];
267     	int			is_raid_five[TW_MAX_UNITS];
268     	int			num_units;
269     	int			num_raid_five;
270     	u32			*command_packet_virtual_address[TW_Q_LENGTH];
271     	u32			command_packet_physical_address[TW_Q_LENGTH];
272     	struct pci_dev		*tw_pci_dev;
273     	Scsi_Cmnd		*srb[TW_Q_LENGTH];
274     	unsigned char		free_queue[TW_Q_LENGTH];
275     	unsigned char		free_head;
276     	unsigned char		free_tail;
277     	unsigned char		pending_queue[TW_Q_LENGTH];
278     	unsigned char		pending_head;
279     	unsigned char		pending_tail;
280     	TW_Cmd_State		state[TW_Q_LENGTH];
281     	u32			posted_request_count;
282     	u32			max_posted_request_count;
283     	u32			request_count_marked_pending;
284     	u32			pending_request_count;
285     	u32			max_pending_request_count;
286     	u32			max_sgl_entries;
287     	u32			sgl_entries;
288     	u32			num_aborts;
289     	u32			num_resets;
290     	u32			sector_count;
291     	u32			max_sector_count;
292     	u32			aen_count;
293     	struct Scsi_Host	*host;
294     	spinlock_t		tw_lock;
295     	unsigned char		ioctl_size[TW_Q_LENGTH];
296     	unsigned short		aen_queue[TW_Q_LENGTH];
297     	unsigned char		aen_head;
298     	unsigned char		aen_tail;
299     	long			flags; /* long req'd for set_bit --RR */
300     } TW_Device_Extension;
301     
302     /* Function prototypes */
303     int tw_aen_complete(TW_Device_Extension *tw_dev, int request_id);
304     int tw_aen_drain_queue(TW_Device_Extension *tw_dev);
305     int tw_aen_read_queue(TW_Device_Extension *tw_dev, int request_id);
306     int tw_allocate_memory(TW_Device_Extension *tw_dev, int request_id, int size, int which);
307     int tw_check_bits(u32 status_reg_value);
308     int tw_check_errors(TW_Device_Extension *tw_dev);
309     void tw_clear_attention_interrupt(TW_Device_Extension *tw_dev);
310     void tw_clear_host_interrupt(TW_Device_Extension *tw_dev);
311     void tw_disable_interrupts(TW_Device_Extension *tw_dev);
312     int tw_empty_response_que(TW_Device_Extension *tw_dev);
313     void tw_enable_interrupts(TW_Device_Extension *tw_dev);
314     int tw_findcards(Scsi_Host_Template *tw_host);
315     void tw_free_device_extension(TW_Device_Extension *tw_dev);
316     int tw_initconnection(TW_Device_Extension *tw_dev, int message_credits);
317     int tw_initialize_device_extension(TW_Device_Extension *tw_dev);
318     int tw_initialize_units(TW_Device_Extension *tw_dev);
319     int tw_ioctl(TW_Device_Extension *tw_dev, int request_id);
320     int tw_ioctl_complete(TW_Device_Extension *tw_dev, int request_id);
321     void tw_mask_command_interrupt(TW_Device_Extension *tw_dev);
322     int tw_poll_status(TW_Device_Extension *tw_dev, u32 flag, int seconds);
323     int tw_post_command_packet(TW_Device_Extension *tw_dev, int request_id);
324     int tw_reset_device_extension(TW_Device_Extension *tw_dev);
325     int tw_reset_sequence(TW_Device_Extension *tw_dev);
326     int tw_scsi_biosparam(Disk *disk, kdev_t dev, int geom[]);
327     int tw_scsi_detect(Scsi_Host_Template *tw_host);
328     int tw_scsi_eh_abort(Scsi_Cmnd *SCpnt);
329     int tw_scsi_eh_reset(Scsi_Cmnd *SCpnt);
330     int tw_scsi_proc_info(char *buffer, char **start, off_t offset, int length, int inode, int inout);
331     int tw_scsi_queue(Scsi_Cmnd *cmd, void (*done) (Scsi_Cmnd *));
332     int tw_scsi_release(struct Scsi_Host *tw_host);
333     int tw_scsiop_inquiry(TW_Device_Extension *tw_dev, int request_id);
334     int tw_scsiop_inquiry_complete(TW_Device_Extension *tw_dev, int request_id);
335     int tw_scsiop_read_capacity(TW_Device_Extension *tw_dev, int request_id);
336     int tw_scsiop_read_capacity_complete(TW_Device_Extension *tw_dev, int request_id);
337     int tw_scsiop_read_write(TW_Device_Extension *tw_dev, int request_id);
338     int tw_scsiop_request_sense(TW_Device_Extension *tw_dev, int request_id);
339     int tw_scsiop_test_unit_ready(TW_Device_Extension *tw_dev, int request_id);
340     int tw_setfeature(TW_Device_Extension *tw_dev, int parm, int param_size, 
341     		  unsigned char *val);
342     int tw_setup_irq(TW_Device_Extension *tw_dev);
343     int tw_shutdown_device(TW_Device_Extension *tw_dev);
344     void tw_soft_reset(TW_Device_Extension *tw_dev);
345     int tw_state_request_finish(TW_Device_Extension *tw_dev,int request_id);
346     int tw_state_request_start(TW_Device_Extension *tw_dev, int *request_id);
347     void tw_unmask_command_interrupt(TW_Device_Extension *tw_dev);
348     
349     /* Scsi_Host_Template Initializer */
350     #define TWXXXX {					\
351     	next : NULL,					\
352     	module : NULL,					\
353     	proc_name : "3w-xxxx",				\
354     	proc_info : tw_scsi_proc_info,			\
355     	name : "3ware Storage Controller",		\
356     	detect : tw_scsi_detect,			\
357     	release : tw_scsi_release,			\
358     	info : NULL,					\
359     	ioctl : NULL,                  			\
360     	command : NULL,					\
361     	queuecommand : tw_scsi_queue,			\
362     	eh_strategy_handler : NULL,			\
363     	eh_abort_handler : tw_scsi_eh_abort,		\
364     	eh_device_reset_handler : NULL,			\
365     	eh_bus_reset_handler : NULL,			\
366     	eh_host_reset_handler : tw_scsi_eh_reset,	\
367     	abort : NULL,					\
368     	reset : NULL,					\
369     	slave_attach : NULL,				\
370     	bios_param : tw_scsi_biosparam,			\
371     	can_queue : TW_Q_LENGTH,			\
372     	this_id: -1,					\
373     	sg_tablesize : TW_MAX_SGL_LENGTH,		\
374     	cmd_per_lun: TW_MAX_CMDS_PER_LUN,		\
375     	present : 0,					\
376     	unchecked_isa_dma : 0,				\
377     	use_clustering : ENABLE_CLUSTERING,		\
378      	use_new_eh_code : 1,				\
379     	emulated : 1					\
380     }
381     #endif /* _3W_XXXX_H */
382