File: /usr/src/linux-2.4.7/drivers/scsi/53c7,8xx.h

1     /*
2      * NCR 53c{7,8}0x0 driver, header file
3      *
4      * Sponsored by
5      *      iX Multiuser Multitasking Magazine
6      *	Hannover, Germany
7      *	hm@ix.de	
8      *
9      * Copyright 1993, 1994, 1995 Drew Eckhardt
10      *      Visionary Computing 
11      *      (Unix and Linux consulting and custom programming)
12      *      drew@PoohSticks.ORG
13      *	+1 (303) 786-7975
14      *
15      * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
16      * 
17      * PRE-ALPHA
18      *
19      * For more information, please consult 
20      *
21      * NCR 53C700/53C700-66
22      * SCSI I/O Processor
23      * Data Manual
24      *
25      * NCR 53C810
26      * PCI-SCSI I/O Processor 
27      * Data Manual
28      *
29      * NCR Microelectronics
30      * 1635 Aeroplaza Drive
31      * Colorado Springs, CO 80916
32      * +1 (719) 578-3400
33      *
34      * Toll free literature number
35      * +1 (800) 334-5454
36      *
37      */
38     
39     #ifndef NCR53c7x0_H
40     #define NCR53c7x0_H
41     #include <linux/version.h>
42     
43     /* 
44      * Prevent name space pollution in hosts.c, and only provide the 
45      * define we need to get the NCR53c7x0 driver into the host template
46      * array.
47      */
48     
49     #include <scsi/scsicam.h>
50     
51     extern int NCR53c7xx_abort(Scsi_Cmnd *);
52     extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
53     extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
54     extern int NCR53c7xx_reset(Scsi_Cmnd *, unsigned int);
55     #ifdef MODULE
56     extern int NCR53c7xx_release(struct Scsi_Host *);
57     #else
58     #define NCR53c7xx_release NULL
59     #endif
60     
61     #define NCR53c7xx {					\
62               name:           "NCR53c{7,8}xx (rel 17)",	\
63     	  detect:         NCR53c7xx_detect,		\
64     	  queuecommand:   NCR53c7xx_queue_command,	\
65     	  abort:          NCR53c7xx_abort,		\
66     	  reset:          NCR53c7xx_reset,		\
67     	  bios_param:     scsicam_bios_param,		\
68     	  can_queue:      24,				\
69     	  this_id:        7,				\
70     	  sg_tablesize:   127,				\
71     	  cmd_per_lun:    3,				\
72     	  use_clustering: DISABLE_CLUSTERING} 
73     
74     #ifndef HOSTS_C
75     
76     /* Register addresses, ordered numerically */
77     
78     /* SCSI control 0 rw, default = 0xc0 */ 
79     #define SCNTL0_REG 		0x00	
80     #define SCNTL0_ARB1		0x80	/* 0 0 = simple arbitration */
81     #define SCNTL0_ARB2		0x40	/* 1 1 = full arbitration */
82     #define SCNTL0_STRT		0x20	/* Start Sequence */
83     #define SCNTL0_WATN		0x10	/* Select with ATN */
84     #define SCNTL0_EPC		0x08	/* Enable parity checking */
85     /* Bit 2 is reserved on 800 series chips */
86     #define SCNTL0_EPG_700		0x04	/* Enable parity generation */
87     #define SCNTL0_AAP		0x02	/*  ATN/ on parity error */
88     #define SCNTL0_TRG		0x01	/* Target mode */
89     
90     /* SCSI control 1 rw, default = 0x00 */
91     
92     #define SCNTL1_REG 		0x01	
93     #define SCNTL1_EXC		0x80	/* Extra Clock Cycle of Data setup */
94     #define SCNTL1_ADB		0x40	/*  contents of SODL on bus */
95     #define SCNTL1_ESR_700		0x20	/* Enable SIOP response to selection 
96     					   and reselection */
97     #define SCNTL1_DHP_800		0x20	/* Disable halt on parity error or ATN
98     					   target mode only */
99     #define SCNTL1_CON		0x10	/* Connected */
100     #define SCNTL1_RST		0x08	/* SCSI RST/ */
101     #define SCNTL1_AESP		0x04	/* Force bad parity */
102     #define SCNTL1_SND_700		0x02	/* Start SCSI send */
103     #define SCNTL1_IARB_800		0x02	/* Immediate Arbitration, start
104     					   arbitration immediately after
105     					   busfree is detected */
106     #define SCNTL1_RCV_700		0x01	/* Start SCSI receive */
107     #define SCNTL1_SST_800		0x01	/* Start SCSI transfer */
108     
109     /* SCSI control 2 rw, */
110     
111     #define SCNTL2_REG_800		0x02	
112     #define SCNTL2_800_SDU		0x80	/* SCSI disconnect unexpected */
113     
114     /* SCSI control 3 rw */
115     
116     #define SCNTL3_REG_800 		0x03	
117     #define SCNTL3_800_SCF_SHIFT	4
118     #define SCNTL3_800_SCF_MASK	0x70
119     #define SCNTL3_800_SCF2		0x40	/* Synchronous divisor */
120     #define SCNTL3_800_SCF1		0x20	/* 0x00 = SCLK/3 */
121     #define SCNTL3_800_SCF0		0x10	/* 0x10 = SCLK/1 */
122     					/* 0x20 = SCLK/1.5 
123     					   0x30 = SCLK/2 
124     					   0x40 = SCLK/3 */
125     	    
126     #define SCNTL3_800_CCF_SHIFT	0
127     #define SCNTL3_800_CCF_MASK	0x07
128     #define SCNTL3_800_CCF2		0x04	/* 0x00 50.01 to 66 */
129     #define SCNTL3_800_CCF1		0x02	/* 0x01 16.67 to 25 */
130     #define SCNTL3_800_CCF0		0x01	/* 0x02	25.01 - 37.5 
131     					   0x03	37.51 - 50 
132     					   0x04 50.01 - 66 */
133     
134     /*  
135      * SCSI destination ID rw - the appropriate bit is set for the selected
136      * target ID.  This is written by the SCSI SCRIPTS processor.
137      * default = 0x00
138      */
139     #define SDID_REG_700  		0x02	
140     #define SDID_REG_800		0x06
141     
142     #define GP_REG_800		0x07	/* General purpose IO */
143     #define GP_800_IO1		0x02
144     #define GP_800_IO2		0x01
145     
146     
147     /* SCSI interrupt enable rw, default = 0x00 */
148     #define SIEN_REG_700		0x03	
149     #define SIEN0_REG_800		0x40
150     #define SIEN_MA			0x80	/* Phase mismatch (ini) or ATN (tgt) */
151     #define SIEN_FC			0x40	/* Function complete */
152     #define SIEN_700_STO		0x20	/* Selection or reselection timeout */
153     #define SIEN_800_SEL		0x20	/* Selected */
154     #define SIEN_700_SEL		0x10	/* Selected or reselected */
155     #define SIEN_800_RESEL		0x10	/* Reselected */
156     #define SIEN_SGE		0x08	/* SCSI gross error */
157     #define SIEN_UDC		0x04	/* Unexpected disconnect */
158     #define SIEN_RST		0x02	/* SCSI RST/ received */
159     #define SIEN_PAR		0x01	/* Parity error */
160     
161     /* 
162      * SCSI chip ID rw
163      * NCR53c700 : 
164      * 	When arbitrating, the highest bit is used, when reselection or selection
165      * 	occurs, the chip responds to all IDs for which a bit is set.
166      * 	default = 0x00 
167      * NCR53c810 : 
168      *	Uses bit mapping
169      */
170     #define SCID_REG		0x04	
171     /* Bit 7 is reserved on 800 series chips */
172     #define SCID_800_RRE		0x40	/* Enable response to reselection */
173     #define SCID_800_SRE		0x20	/* Enable response to selection */
174     /* Bits four and three are reserved on 800 series chips */
175     #define SCID_800_ENC_MASK	0x07	/* Encoded SCSI ID */
176     
177     /* SCSI transfer rw, default = 0x00 */
178     #define SXFER_REG		0x05
179     #define SXFER_DHP		0x80	/* Disable halt on parity */
180     
181     #define SXFER_TP2		0x40	/* Transfer period msb */
182     #define SXFER_TP1		0x20
183     #define SXFER_TP0		0x10	/* lsb */
184     #define SXFER_TP_MASK		0x70
185     /* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */
186     #define SXFER_TP_SHIFT		5
187     #define SXFER_TP_4		0x00	/* Divisors */
188     #define SXFER_TP_5		0x10<<1
189     #define SXFER_TP_6		0x20<<1
190     #define SXFER_TP_7		0x30<<1
191     #define SXFER_TP_8		0x40<<1
192     #define SXFER_TP_9		0x50<<1
193     #define SXFER_TP_10		0x60<<1
194     #define SXFER_TP_11		0x70<<1
195     
196     #define SXFER_MO3		0x08	/* Max offset msb */
197     #define SXFER_MO2		0x04
198     #define SXFER_MO1		0x02
199     #define SXFER_MO0		0x01	/* lsb */
200     #define SXFER_MO_MASK		0x0f
201     #define SXFER_MO_SHIFT		0
202     
203     /* 
204      * SCSI output data latch rw
205      * The contents of this register are driven onto the SCSI bus when 
206      * the Assert Data Bus bit of the SCNTL1 register is set and 
207      * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
208      */
209     #define SODL_REG_700		0x06	
210     #define SODL_REG_800		0x54
211     
212     
213     /* 
214      * SCSI output control latch rw, default = 0 
215      * Note that when the chip is being manually programmed as an initiator,
216      * the MSG, CD, and IO bits must be set correctly for the phase the target
217      * is driving the bus in.  Otherwise no data transfer will occur due to 
218      * phase mismatch.
219      */
220     
221     #define SBCL_REG		0x0b
222     #define SBCL_REQ		0x80	/*  REQ */
223     #define SBCL_ACK		0x40	/*  ACK */
224     #define SBCL_BSY		0x20	/*  BSY */
225     #define SBCL_SEL		0x10	/*  SEL */
226     #define SBCL_ATN		0x08	/*  ATN */
227     #define SBCL_MSG		0x04	/*  MSG */
228     #define SBCL_CD			0x02	/*  C/D */
229     #define SBCL_IO			0x01	/*  I/O */
230     #define SBCL_PHASE_CMDOUT	SBCL_CD
231     #define SBCL_PHASE_DATAIN	SBCL_IO
232     #define SBCL_PHASE_DATAOUT	0
233     #define SBCL_PHASE_MSGIN	(SBCL_CD|SBCL_IO|SBCL_MSG)
234     #define SBCL_PHASE_MSGOUT	(SBCL_CD|SBCL_MSG)
235     #define SBCL_PHASE_STATIN	(SBCL_CD|SBCL_IO)
236     #define SBCL_PHASE_MASK		(SBCL_CD|SBCL_IO|SBCL_MSG)
237     
238     /* 
239      * SCSI first byte received latch ro 
240      * This register contains the first byte received during a block MOVE 
241      * SCSI SCRIPTS instruction, including
242      * 
243      * Initiator mode	Target mode
244      * Message in		Command
245      * Status		Message out
246      * Data in		Data out
247      *
248      * It also contains the selecting or reselecting device's ID and our 
249      * ID.
250      *
251      * Note that this is the register the various IF conditionals can 
252      * operate on.
253      */
254     #define SFBR_REG		0x08	
255     
256     /* 
257      * SCSI input data latch ro
258      * In initiator mode, data is latched into this register on the rising
259      * edge of REQ/. In target mode, data is latched on the rising edge of 
260      * ACK/
261      */
262     #define SIDL_REG_700		0x09
263     #define SIDL_REG_800		0x50
264     
265     /* 
266      * SCSI bus data lines ro 
267      * This register reflects the instantaneous status of the SCSI data 
268      * lines.  Note that SCNTL0 must be set to disable parity checking, 
269      * otherwise reading this register will latch new parity.
270      */
271     #define SBDL_REG_700		0x0a
272     #define SBDL_REG_800		0x58
273     
274     #define SSID_REG_800		0x0a
275     #define SSID_800_VAL		0x80	/* Exactly two bits asserted at sel */
276     #define SSID_800_ENCID_MASK	0x07	/* Device which performed operation */
277     
278     
279     /* 
280      * SCSI bus control lines rw, 
281      * instantaneous readout of control lines 
282      */
283     #define SOCL_REG		0x0b 	
284     #define SOCL_REQ		0x80	/*  REQ ro */
285     #define SOCL_ACK		0x40	/*  ACK ro */
286     #define SOCL_BSY		0x20	/*  BSY ro */
287     #define SOCL_SEL		0x10	/*  SEL ro */
288     #define SOCL_ATN		0x08	/*  ATN ro */
289     #define SOCL_MSG		0x04	/*  MSG ro */
290     #define SOCL_CD			0x02	/*  C/D ro */
291     #define SOCL_IO			0x01	/*  I/O ro */
292     /* 
293      * Synchronous SCSI Clock Control bits 
294      * 0 - set by DCNTL 
295      * 1 - SCLK / 1.0
296      * 2 - SCLK / 1.5
297      * 3 - SCLK / 2.0 
298      */
299     #define SBCL_SSCF1		0x02	/* wo, -66 only */
300     #define SBCL_SSCF0		0x01	/* wo, -66 only */
301     #define SBCL_SSCF_MASK		0x03
302     
303     /* 
304      * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
305      * insure that 10 clocks elapse between the two  
306      */
307     /* DMA status ro */
308     #define DSTAT_REG		0x0c	
309     #define DSTAT_DFE		0x80	/* DMA FIFO empty */
310     #define DSTAT_800_MDPE		0x40	/* Master Data Parity Error */
311     #define DSTAT_800_BF		0x20	/* Bus Fault */
312     #define DSTAT_ABRT		0x10	/* Aborted - set on error */
313     #define DSTAT_SSI		0x08	/* SCRIPTS single step interrupt */
314     #define DSTAT_SIR		0x04	/* SCRIPTS interrupt received - 
315     					   set when INT instruction is 
316     					   executed */
317     #define DSTAT_WTD		0x02	/* Watchdog timeout detected */
318     #define DSTAT_OPC		0x01	/* Illegal instruction */
319     #define DSTAT_800_IID		0x01	/* Same thing, different name */
320     
321     
322     /* NCR53c800 moves this stuff into SIST0 */
323     #define SSTAT0_REG		0x0d	/* SCSI status 0 ro */
324     #define SIST0_REG_800		0x42	
325     #define SSTAT0_MA		0x80	/* ini : phase mismatch,
326     					 * tgt : ATN/ asserted 
327     					 */
328     #define SSTAT0_CMP		0x40	/* function complete */
329     #define SSTAT0_700_STO		0x20	/* Selection or reselection timeout */
330     #define SIST0_800_SEL		0x20	/* Selected */
331     #define SSTAT0_700_SEL		0x10	/* Selected or reselected */
332     #define SIST0_800_RSL		0x10	/* Reselected */
333     #define SSTAT0_SGE		0x08	/* SCSI gross error */
334     #define SSTAT0_UDC		0x04	/* Unexpected disconnect */
335     #define SSTAT0_RST		0x02	/* SCSI RST/ received */
336     #define SSTAT0_PAR		0x01	/* Parity error */
337     
338     /* And uses SSTAT0 for what was SSTAT1 */
339     
340     #define SSTAT1_REG		0x0e	/* SCSI status 1 ro */
341     #define SSTAT1_ILF		0x80	/* SIDL full */
342     #define SSTAT1_ORF		0x40	/* SODR full */
343     #define SSTAT1_OLF		0x20	/* SODL full */
344     #define SSTAT1_AIP		0x10	/* Arbitration in progress */
345     #define SSTAT1_LOA		0x08	/* Lost arbitration */
346     #define SSTAT1_WOA		0x04	/* Won arbitration */
347     #define SSTAT1_RST		0x02	/* Instant readout of RST/ */
348     #define SSTAT1_SDP		0x01	/* Instant readout of SDP/ */
349     
350     #define SSTAT2_REG		0x0f	/* SCSI status 2 ro */
351     #define SSTAT2_FF3		0x80 	/* number of bytes in synchronous */
352     #define SSTAT2_FF2		0x40	/* data FIFO */
353     #define SSTAT2_FF1		0x20	
354     #define SSTAT2_FF0		0x10
355     #define SSTAT2_FF_MASK		0xf0
356     #define SSTAT2_FF_SHIFT		4
357     
358     /* 
359      * Latched signals, latched on the leading edge of REQ/ for initiators,
360      * ACK/ for targets.
361      */
362     #define SSTAT2_SDP		0x08	/* SDP */
363     #define SSTAT2_MSG		0x04	/* MSG */
364     #define SSTAT2_CD		0x02	/* C/D */
365     #define SSTAT2_IO		0x01	/* I/O */
366     #define SSTAT2_PHASE_CMDOUT	SSTAT2_CD
367     #define SSTAT2_PHASE_DATAIN	SSTAT2_IO
368     #define SSTAT2_PHASE_DATAOUT	0
369     #define SSTAT2_PHASE_MSGIN	(SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
370     #define SSTAT2_PHASE_MSGOUT	(SSTAT2_CD|SSTAT2_MSG)
371     #define SSTAT2_PHASE_STATIN	(SSTAT2_CD|SSTAT2_IO)
372     #define SSTAT2_PHASE_MASK	(SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
373     
374     
375     /* NCR53c700-66 only */
376     #define SCRATCHA_REG_00		0x10    /* through  0x13 Scratch A rw */
377     /* NCR53c710 and higher */
378     #define DSA_REG			0x10	/* DATA structure address */
379     
380     #define CTEST0_REG_700		0x14	/* Chip test 0 ro */
381     #define CTEST0_REG_800		0x18	/* Chip test 0 rw, general purpose */
382     /* 0x80 - 0x04 are reserved */
383     #define CTEST0_700_RTRG		0x02	/* Real target mode */
384     #define CTEST0_700_DDIR		0x01	/* Data direction, 1 = 
385     					 * SCSI bus to host, 0  =
386     					 * host to SCSI.
387     					 */
388     
389     #define CTEST1_REG_700		0x15	/* Chip test 1 ro */
390     #define CTEST1_REG_800		0x19	/* Chip test 1 ro */
391     #define CTEST1_FMT3		0x80	/* Identify which byte lanes are empty */
392     #define CTEST1_FMT2		0x40 	/* in the DMA FIFO */
393     #define CTEST1_FMT1		0x20
394     #define CTEST1_FMT0		0x10
395     
396     #define CTEST1_FFL3		0x08	/* Identify which bytes lanes are full */
397     #define CTEST1_FFL2		0x04	/* in the DMA FIFO */
398     #define CTEST1_FFL1		0x02
399     #define CTEST1_FFL0		0x01
400     
401     #define CTEST2_REG_700		0x16	/* Chip test 2 ro */
402     #define CTEST2_REG_800		0x1a	/* Chip test 2 ro */
403     
404     #define CTEST2_800_DDIR		0x80	/* 1 = SCSI->host */
405     #define CTEST2_800_SIGP		0x40	/* A copy of SIGP in ISTAT.
406     					   Reading this register clears */
407     #define CTEST2_800_CIO		0x20	/* Configured as IO */.
408     #define CTEST2_800_CM		0x10	/* Configured as memory */
409     
410     /* 0x80 - 0x40 are reserved on 700 series chips */
411     #define CTEST2_700_SOFF		0x20	/* SCSI Offset Compare,
412     					 * As an initiator, this bit is 
413     					 * one when the synchronous offset
414     					 * is zero, as a target this bit 
415     					 * is one when the synchronous 
416     					 * offset is at the maximum
417     					 * defined in SXFER
418     					 */
419     #define CTEST2_700_SFP		0x10	/* SCSI FIFO parity bit,
420     					 * reading CTEST3 unloads a byte
421     					 * from the FIFO and sets this
422     					 */
423     #define CTEST2_700_DFP		0x08	/* DMA FIFO parity bit,
424     					 * reading CTEST6 unloads a byte
425     					 * from the FIFO and sets this
426     					 */
427     #define CTEST2_TEOP		0x04	/* SCSI true end of process,
428     					 * indicates a totally finished
429     					 * transfer
430     					 */
431     #define CTEST2_DREQ		0x02	/* Data request signal */
432     /* 0x01 is reserved on 700 series chips */
433     #define CTEST2_800_DACK		0x01	
434     
435     /* 
436      * Chip test 3 ro 
437      * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
438      * check SSTAT2 FIFO full bits to determine size.  Note that a GROSS
439      * error results if a read is attempted on this register.  Also note 
440      * that 16 and 32 bit reads of this register will cause corruption.
441      */
442     #define CTEST3_REG_700		0x17	
443     /*  Chip test 3 rw */
444     #define CTEST3_REG_800		0x1b
445     #define CTEST3_800_V3		0x80	/* Chip revision */
446     #define CTEST3_800_V2		0x40
447     #define CTEST3_800_V1		0x20
448     #define CTEST3_800_V0		0x10
449     #define CTEST3_800_FLF		0x08	/* Flush DMA FIFO */
450     #define CTEST3_800_CLF		0x04	/* Clear DMA FIFO */
451     #define CTEST3_800_FM		0x02	/* Fetch mode pin */
452     /* bit 0 is reserved on 800 series chips */
453     
454     #define CTEST4_REG_700		0x18	/* Chip test 4 rw */
455     #define CTEST4_REG_800		0x21	/* Chip test 4 rw */
456     /* 0x80 is reserved on 700 series chips */
457     #define CTEST4_800_BDIS		0x80	/* Burst mode disable */
458     #define CTEST4_ZMOD		0x40	/* High impedance mode */
459     #define CTEST4_SZM		0x20	/* SCSI bus high impedance */
460     #define CTEST4_700_SLBE		0x10	/* SCSI loopback enabled */
461     #define CTEST4_800_SRTM		0x10	/* Shadow Register Test Mode */
462     #define CTEST4_700_SFWR		0x08	/* SCSI FIFO write enable, 
463     					 * redirects writes from SODL
464     					 * to the SCSI FIFO.
465     					 */
466     #define CTEST4_800_MPEE		0x08	/* Enable parity checking
467     					   during master cycles on PCI
468     					   bus */
469     
470     /* 
471      * These bits send the contents of the CTEST6 register to the appropriate
472      * byte lane of the 32 bit DMA FIFO.  Normal operation is zero, otherwise 
473      * the high bit means the low two bits select the byte lane.
474      */
475     #define CTEST4_FBL2		0x04	
476     #define CTEST4_FBL1		0x02
477     #define CTEST4_FBL0		0x01	
478     #define CTEST4_FBL_MASK		0x07
479     #define CTEST4_FBL_0		0x04	/* Select DMA FIFO byte lane 0 */
480     #define CTEST4_FBL_1		0x05	/* Select DMA FIFO byte lane 1 */
481     #define CTEST4_FBL_2		0x06	/* Select DMA FIFO byte lane 2 */
482     #define CTEST4_FBL_3		0x07	/* Select DMA FIFO byte lane 3 */
483     #define CTEST4_800_SAVE		(CTEST4_800_BDIS)
484     
485     
486     #define CTEST5_REG_700		0x19	/* Chip test 5 rw */
487     #define CTEST5_REG_800		0x22	/* Chip test 5 rw */
488     /* 
489      * Clock Address Incrementor.  When set, it increments the 
490      * DNAD register to the next bus size boundary.  It automatically 
491      * resets itself when the operation is complete.
492      */
493     #define CTEST5_ADCK		0x80
494     /*
495      * Clock Byte Counter.  When set, it decrements the DBC register to
496      * the next bus size boundary.
497      */
498     #define CTEST5_BBCK		0x40
499     /*
500      * Reset SCSI Offset.  Setting this bit to 1 clears the current offset
501      * pointer in the SCSI synchronous offset counter (SSTAT).  This bit
502      * is set to 1 if a SCSI Gross Error Condition occurs.  The offset should
503      * be cleared when a synchronous transfer fails.  When written, it is 
504      * automatically cleared after the SCSI synchronous offset counter is 
505      * reset.
506      */
507     /* Bit 5 is reserved on 800 series chips */
508     #define CTEST5_700_ROFF		0x20
509     /* 
510      * Master Control for Set or Reset pulses. When 1, causes the low 
511      * four bits of register to set when set, 0 causes the low bits to
512      * clear when set.
513      */
514     #define CTEST5_MASR 		0x10	
515     #define CTEST5_DDIR		0x08	/* DMA direction */
516     /*
517      * Bits 2-0 are reserved on 800 series chips
518      */
519     #define CTEST5_700_EOP		0x04	/* End of process */
520     #define CTEST5_700_DREQ		0x02	/* Data request */
521     #define CTEST5_700_DACK		0x01	/* Data acknowledge */
522     
523     /* 
524      * Chip test 6 rw - writing to this register writes to the byte 
525      * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
526      * register.
527      */
528     #define CTEST6_REG_700		0x1a
529     #define CTEST6_REG_800		0x23
530     
531     #define CTEST7_REG		0x1b	/* Chip test 7 rw */
532     /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
533     #define CTEST7_10_CDIS		0x80	/* Cache burst disable */
534     #define CTEST7_10_SC1		0x40	/* Snoop control bits */
535     #define CTEST7_10_SC0		0x20	
536     #define CTEST7_10_SC_MASK	0x60
537     /* 0x20 is reserved on the NCR53c700 */
538     #define CTEST7_0060_FM		0x20	/* Fetch mode */
539     #define CTEST7_STD		0x10	/* Selection timeout disable */
540     #define CTEST7_DFP		0x08	/* DMA FIFO parity bit for CTEST6 */
541     #define CTEST7_EVP		0x04	/* 1 = host bus even parity, 0 = odd */
542     #define CTEST7_10_TT1		0x02	/* Transfer type */
543     #define CTEST7_00_DC		0x02	/* Set to drive DC low during instruction 
544     					   fetch */
545     #define CTEST7_DIFF		0x01	/* Differential mode */
546     
547     #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
548     
549     
550     #define TEMP_REG		0x1c	/* through 0x1f Temporary stack rw */
551     
552     #define DFIFO_REG		0x20	/* DMA FIFO rw */
553     /* 
554      * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
555      * moved into the CTEST8 register.
556      */
557     #define DFIFO_00_FLF		0x80	/* Flush DMA FIFO to memory */
558     #define DFIFO_00_CLF		0x40	/* Clear DMA and SCSI FIFOs */
559     #define DFIFO_BO6		0x40
560     #define DFIFO_BO5		0x20
561     #define DFIFO_BO4		0x10
562     #define DFIFO_BO3		0x08
563     #define DFIFO_BO2		0x04 
564     #define DFIFO_BO1		0x02
565     #define DFIFO_BO0		0x01
566     #define DFIFO_10_BO_MASK	0x7f	/* 7 bit counter */
567     #define DFIFO_00_BO_MASK	0x3f	/* 6 bit counter */
568     
569     /* 
570      * Interrupt status rw 
571      * Note that this is the only register which can be read while SCSI
572      * SCRIPTS are being executed.
573      */
574     #define ISTAT_REG_700		0x21
575     #define ISTAT_REG_800		0x14
576     #define ISTAT_ABRT		0x80	/* Software abort, write 
577     					 *1 to abort, wait for interrupt. */
578     /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
579     #define ISTAT_10_SRST		0x40	/* software reset */
580     #define ISTAT_10_SIGP		0x20	/* signal script */
581     /* 0x10 is reserved on NCR53c700 series chips */
582     #define ISTAT_800_SEM		0x10	/* semaphore */
583     #define ISTAT_CON		0x08	/* 1 when connected */
584     #define ISTAT_800_INTF		0x04	/* Interrupt on the fly */
585     #define ISTAT_700_PRE		0x04	/* Pointer register empty.
586     					 * Set to 1 when DSPS and DSP
587     					 * registers are empty in pipeline
588     					 * mode, always set otherwise.
589     					 */
590     #define ISTAT_SIP		0x02	/* SCSI interrupt pending from
591     					 * SCSI portion of SIOP see
592     					 * SSTAT0
593     					 */
594     #define ISTAT_DIP		0x01	/* DMA interrupt pending 
595     					 * see DSTAT
596     					 */
597     
598     /* NCR53c700-66 and NCR53c710 only */
599     #define CTEST8_REG		0x22	/* Chip test 8 rw */
600     #define CTEST8_0066_EAS		0x80	/* Enable alternate SCSI clock,
601     					 * ie read from SCLK/ rather than CLK/
602     					 */
603     #define CTEST8_0066_EFM		0x40	/* Enable fetch and master outputs */
604     #define CTEST8_0066_GRP		0x20	/* Generate Receive Parity for 
605     					 * pass through.  This insures that 
606     					 * bad parity won't reach the host 
607     					 * bus.
608     					 */
609     #define CTEST8_0066_TE		0x10	/* TolerANT enable.  Enable 
610     					 * active negation, should only
611     					 * be used for slow SCSI 
612     					 * non-differential.
613     					 */
614     #define CTEST8_0066_HSC		0x08	/* Halt SCSI clock */
615     #define CTEST8_0066_SRA		0x04	/* Shorten REQ/ACK filtering,
616     					 * must be set for fast SCSI-II
617     					 * speeds.
618     					 */
619     #define CTEST8_0066_DAS		0x02	/* Disable automatic target/initiator
620     					 * switching.
621     					 */
622     #define CTEST8_0066_LDE		0x01	/* Last disconnect enable.
623     					 * The status of pending 
624     					 * disconnect is maintained by
625     					 * the core, eliminating
626     					 * the possibility of missing a 
627     					 * selection or reselection
628     					 * while waiting to fetch a 
629     					 * WAIT DISCONNECT opcode.
630     					 */
631     
632     #define CTEST8_10_V3		0x80	/* Chip revision */
633     #define CTEST8_10_V2		0x40
634     #define CTEST8_10_V1		0x20	
635     #define CTEST8_10_V0		0x10
636     #define CTEST8_10_V_MASK	0xf0	
637     #define CTEST8_10_FLF		0x08	/* Flush FIFOs */
638     #define CTEST8_10_CLF		0x04	/* Clear FIFOs */
639     #define CTEST8_10_FM		0x02	/* Fetch pin mode */
640     #define CTEST8_10_SM		0x01	/* Snoop pin mode */
641     
642     
643     /* 
644      * The CTEST9 register may be used to differentiate between a
645      * NCR53c700 and a NCR53c710.  
646      *
647      * Write 0xff to this register.
648      * Read it.
649      * If the contents are 0xff, it is a NCR53c700
650      * If the contents are 0x00, it is a NCR53c700-66 first revision
651      * If the contents are some other value, it is some other NCR53c700-66
652      */
653     #define CTEST9_REG_00		0x23	/* Chip test 9 ro */
654     #define LCRC_REG_10		0x23	
655     
656     /*
657      * 0x24 through 0x27 are the DMA byte counter register.  Instructions
658      * write their high 8 bits into the DCMD register, the low 24 bits into
659      * the DBC register.
660      *
661      * Function is dependent on the command type being executed.
662      */
663     
664      
665     #define DBC_REG			0x24
666     /* 
667      * For Block Move Instructions, DBC is a 24 bit quantity representing 
668      *     the number of bytes to transfer.
669      * For Transfer Control Instructions, DBC is bit fielded as follows : 
670      */
671     /* Bits 20 - 23 should be clear */
672     #define DBC_TCI_TRUE		(1 << 19) 	/* Jump when true */
673     #define DBC_TCI_COMPARE_DATA	(1 << 18)	/* Compare data */
674     #define DBC_TCI_COMPARE_PHASE	(1 << 17)	/* Compare phase with DCMD field */
675     #define DBC_TCI_WAIT_FOR_VALID	(1 << 16)	/* Wait for REQ */
676     /* Bits 8 - 15 are reserved on some implementations ? */
677     #define DBC_TCI_MASK_MASK	0xff00 		/* Mask for data compare */
678     #define DBC_TCI_MASK_SHIFT	8
679     #define DBC_TCI_DATA_MASK	0xff		/* Data to be compared */ 
680     #define DBC_TCI_DATA_SHIFT	0
681     
682     #define DBC_RWRI_IMMEDIATE_MASK	0xff00		/* Immediate data */
683     #define DBC_RWRI_IMMEDIATE_SHIFT 8		/* Amount to shift */
684     #define DBC_RWRI_ADDRESS_MASK	0x3f0000	/* Register address */
685     #define DBC_RWRI_ADDRESS_SHIFT 	16
686     
687     
688     /*
689      * DMA command r/w
690      */
691     #define DCMD_REG		0x27	
692     #define DCMD_TYPE_MASK		0xc0	/* Masks off type */
693     #define DCMD_TYPE_BMI		0x00	/* Indicates a Block Move instruction */
694     #define DCMD_BMI_IO		0x01	/* I/O, CD, and MSG bits selecting   */
695     #define DCMD_BMI_CD		0x02	/* the phase for the block MOVE      */
696     #define DCMD_BMI_MSG		0x04	/* instruction 			     */
697     
698     #define DCMD_BMI_OP_MASK	0x18	/* mask for opcode */
699     #define DCMD_BMI_OP_MOVE_T	0x00	/* MOVE */
700     #define DCMD_BMI_OP_MOVE_I	0x08	/* MOVE Initiator */
701     
702     #define DCMD_BMI_INDIRECT	0x20	/*  Indirect addressing */
703     
704     #define DCMD_TYPE_TCI		0x80	/* Indicates a Transfer Control 
705     					   instruction */
706     #define DCMD_TCI_IO		0x01	/* I/O, CD, and MSG bits selecting   */
707     #define DCMD_TCI_CD		0x02	/* the phase for the block MOVE      */
708     #define DCMD_TCI_MSG		0x04	/* instruction 			     */
709     #define DCMD_TCI_OP_MASK	0x38	/* mask for opcode */
710     #define DCMD_TCI_OP_JUMP	0x00	/* JUMP */
711     #define DCMD_TCI_OP_CALL	0x08	/* CALL */
712     #define DCMD_TCI_OP_RETURN	0x10	/* RETURN */
713     #define DCMD_TCI_OP_INT		0x18	/* INT */
714     
715     #define DCMD_TYPE_RWRI		0x40	/* Indicates I/O or register Read/Write
716     					   instruction */
717     #define DCMD_RWRI_OPC_MASK	0x38	/* Opcode mask */
718     #define DCMD_RWRI_OPC_WRITE	0x28	/* Write SFBR to register */
719     #define DCMD_RWRI_OPC_READ	0x30	/* Read register to SFBR */
720     #define DCMD_RWRI_OPC_MODIFY	0x38	/* Modify in place */
721     
722     #define DCMD_RWRI_OP_MASK	0x07
723     #define DCMD_RWRI_OP_MOVE	0x00
724     #define DCMD_RWRI_OP_SHL	0x01
725     #define DCMD_RWRI_OP_OR		0x02
726     #define DCMD_RWRI_OP_XOR	0x03
727     #define DCMD_RWRI_OP_AND	0x04
728     #define DCMD_RWRI_OP_SHR	0x05
729     #define DCMD_RWRI_OP_ADD	0x06
730     #define DCMD_RWRI_OP_ADDC	0x07
731     
732     #define DCMD_TYPE_MMI		0xc0	/* Indicates a Memory Move instruction 
733     					   (three words) */
734     
735     
736     #define DNAD_REG		0x28	/* through 0x2b DMA next address for 
737     					   data */
738     #define DSP_REG			0x2c	/* through 0x2f DMA SCRIPTS pointer rw */
739     #define DSPS_REG		0x30	/* through 0x33 DMA SCRIPTS pointer 
740     					   save rw */
741     #define DMODE_REG_00		0x34 	/* DMA mode rw */
742     #define DMODE_00_BL1	0x80	/* Burst length bits */
743     #define DMODE_00_BL0	0x40
744     #define DMODE_BL_MASK	0xc0
745     /* Burst lengths (800) */
746     #define DMODE_BL_2	0x00	/* 2 transfer */
747     #define DMODE_BL_4	0x40	/* 4 transfers */
748     #define DMODE_BL_8	0x80	/* 8 transfers */
749     #define DMODE_BL_16	0xc0	/* 16 transfers */
750     
751     #define DMODE_700_BW16	0x20	/* Host buswidth = 16 */
752     #define DMODE_700_286	0x10	/* 286 mode */
753     #define DMODE_700_IOM	0x08	/* Transfer to IO port */
754     #define DMODE_700_FAM	0x04	/* Fixed address mode */
755     #define DMODE_700_PIPE	0x02	/* Pipeline mode disables 
756     					 * automatic fetch / exec 
757     					 */
758     #define DMODE_MAN	0x01		/* Manual start mode, 
759     					 * requires a 1 to be written
760     					 * to the start DMA bit in the DCNTL
761     					 * register to run scripts 
762     					 */
763     
764     #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
765     
766     /* NCR53c800 series only */
767     #define SCRATCHA_REG_800	0x34	/* through 0x37 Scratch A rw */
768     /* NCR53c710 only */
769     #define SCRATCB_REG_10		0x34	/* through 0x37 scratch B rw */
770     
771     #define DMODE_REG_10    	0x38	/* DMA mode rw, NCR53c710 and newer */
772     #define DMODE_800_SIOM		0x20	/* Source IO = 1 */
773     #define DMODE_800_DIOM		0x10	/* Destination IO = 1 */
774     #define DMODE_800_ERL		0x08	/* Enable Read Line */
775     
776     /* 35-38 are reserved on 700 and 700-66 series chips */
777     #define DIEN_REG		0x39	/* DMA interrupt enable rw */
778     /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
779     #define DIEN_800_MDPE		0x40	/* Master data parity error */
780     #define DIEN_800_BF		0x20	/* BUS fault */
781     #define DIEN_ABRT		0x10	/* Enable aborted interrupt */
782     #define DIEN_SSI		0x08	/* Enable single step interrupt */
783     #define DIEN_SIR		0x04	/* Enable SCRIPTS INT command 
784     					 * interrupt
785     					 */
786     /* 0x02 is reserved on 800 series chips */
787     #define DIEN_700_WTD		0x02	/* Enable watchdog timeout interrupt */
788     #define DIEN_700_OPC		0x01	/* Enable illegal instruction 
789     					 * interrupt 
790     					 */
791     #define DIEN_800_IID		0x01	/*  Same meaning, different name */ 
792     
793     /*
794      * DMA watchdog timer rw
795      * set in 16 CLK input periods.
796      */
797     #define DWT_REG			0x3a
798     
799     /* DMA control rw */
800     #define DCNTL_REG		0x3b
801     #define DCNTL_700_CF1		0x80	/* Clock divisor bits */
802     #define DCNTL_700_CF0		0x40
803     #define DCNTL_700_CF_MASK	0xc0
804     /* Clock divisors 			   Divisor SCLK range (MHZ) */
805     #define DCNTL_700_CF_2		0x00    /* 2.0	   37.51-50.00 */
806     #define DCNTL_700_CF_1_5	0x40	/* 1.5	   25.01-37.50 */
807     #define DCNTL_700_CF_1		0x80	/* 1.0     16.67-25.00 */
808     #define DCNTL_700_CF_3		0xc0	/* 3.0	   50.01-66.67 (53c700-66) */
809     
810     #define DCNTL_700_S16		0x20	/* Load scripts 16 bits at a time */
811     #define DCNTL_SSM		0x10	/* Single step mode */
812     #define DCNTL_700_LLM		0x08	/* Low level mode, can only be set 
813     					 * after selection */
814     #define DCNTL_800_IRQM		0x08	/* Totem pole IRQ pin */
815     #define DCNTL_STD		0x04	/* Start DMA / SCRIPTS */
816     /* 0x02 is reserved */
817     #define DCNTL_00_RST		0x01	/* Software reset, resets everything
818     					 * but 286 mode bit  in DMODE. On the
819     					 * NCR53c710, this bit moved to CTEST8
820     					 */
821     #define DCNTL_10_COM		0x01	/* 700 software compatibility mode */
822     
823     #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
824     
825     
826     /* NCR53c700-66 only */
827     #define SCRATCHB_REG_00		0x3c	/* through 0x3f scratch b rw */
828     #define SCRATCHB_REG_800	0x5c	/* through 0x5f scratch b rw */
829     /* NCR53c710 only */
830     #define ADDER_REG_10		0x3c	/* Adder, NCR53c710 only */
831     
832     #define SIEN1_REG_800		0x41
833     #define SIEN1_800_STO		0x04	/* selection/reselection timeout */
834     #define SIEN1_800_GEN		0x02	/* general purpose timer */
835     #define SIEN1_800_HTH		0x01	/* handshake to handshake */
836     
837     #define SIST1_REG_800		0x43
838     #define SIST1_800_STO		0x04	/* selection/reselection timeout */
839     #define SIST1_800_GEN		0x02	/* general purpose timer */
840     #define SIST1_800_HTH		0x01	/* handshake to handshake */
841     
842     #define SLPAR_REG_800		0x44	/* Parity */
843     
844     #define MACNTL_REG_800		0x46	/* Memory access control */
845     #define MACNTL_800_TYP3		0x80
846     #define MACNTL_800_TYP2		0x40
847     #define MACNTL_800_TYP1		0x20
848     #define MACNTL_800_TYP0		0x10
849     #define MACNTL_800_DWR		0x08
850     #define MACNTL_800_DRD		0x04
851     #define MACNTL_800_PSCPT	0x02
852     #define MACNTL_800_SCPTS	0x01
853     
854     #define GPCNTL_REG_800		0x47	/* General Purpose Pin Control */
855     
856     /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
857     #define STIME0_REG_800		0x48	/* SCSI Timer Register 0 */
858     #define STIME0_800_HTH_MASK	0xf0	/* Handshake to Handshake timeout */
859     #define STIME0_800_HTH_SHIFT	4
860     #define STIME0_800_SEL_MASK	0x0f	/* Selection timeout */
861     #define STIME0_800_SEL_SHIFT	0
862     
863     #define STIME1_REG_800		0x49
864     #define STIME1_800_GEN_MASK	0x0f	/* General purpose timer */
865     
866     #define RESPID_REG_800		0x4a	/* Response ID, bit fielded.  8
867     					   bits on narrow chips, 16 on WIDE */
868     
869     #define STEST0_REG_800		0x4c	
870     #define STEST0_800_SLT		0x08	/* Selection response logic test */
871     #define STEST0_800_ART		0x04	/* Arbitration priority encoder test */
872     #define STEST0_800_SOZ		0x02	/* Synchronous offset zero */
873     #define STEST0_800_SOM		0x01	/* Synchronous offset maximum */
874     
875     #define STEST1_REG_800		0x4d
876     #define STEST1_800_SCLK		0x80	/* Disable SCSI clock */
877     
878     #define STEST2_REG_800		0x4e	
879     #define STEST2_800_SCE		0x80	/* Enable SOCL/SODL */
880     #define STEST2_800_ROF		0x40	/* Reset SCSI sync offset */
881     #define STEST2_800_SLB		0x10	/* Enable SCSI loopback mode */
882     #define STEST2_800_SZM		0x08	/* SCSI high impedance mode */
883     #define STEST2_800_EXT		0x02	/* Extend REQ/ACK filter 30 to 60ns */
884     #define STEST2_800_LOW		0x01	/* SCSI low level mode */
885     
886     #define STEST3_REG_800		0x4f	 
887     #define STEST3_800_TE		0x80	/* Enable active negation */
888     #define STEST3_800_STR		0x40	/* SCSI FIFO test read */
889     #define STEST3_800_HSC		0x20	/* Halt SCSI clock */
890     #define STEST3_800_DSI		0x10	/* Disable single initiator response */
891     #define STEST3_800_TTM		0x04	/* Time test mode */
892     #define STEST3_800_CSF		0x02	/* Clear SCSI FIFO */
893     #define STEST3_800_STW		0x01	/* SCSI FIFO test write */
894     
895     #define OPTION_PARITY 		0x1	/* Enable parity checking */
896     #define OPTION_TAGGED_QUEUE	0x2	/* Enable SCSI-II tagged queuing */
897     #define OPTION_700		0x8	/* Always run NCR53c700 scripts */
898     #define OPTION_INTFLY		0x10	/* Use INTFLY interrupts */
899     #define OPTION_DEBUG_INTR	0x20	/* Debug interrupts */
900     #define OPTION_DEBUG_INIT_ONLY	0x40	/* Run initialization code and 
901     					   simple test code, return
902     					   DID_NO_CONNECT if any SCSI
903     					   commands are attempted. */
904     #define OPTION_DEBUG_READ_ONLY	0x80	/* Return DID_ERROR if any 
905     					   SCSI write is attempted */
906     #define OPTION_DEBUG_TRACE	0x100	/* Animated trace mode, print 
907     					   each address and instruction 
908     					   executed to debug buffer. */
909     #define OPTION_DEBUG_SINGLE	0x200	/* stop after executing one 
910     					   instruction */
911     #define OPTION_SYNCHRONOUS	0x400	/* Enable sync SCSI.  */
912     #define OPTION_MEMORY_MAPPED	0x800	/* NCR registers have valid 
913     					   memory mapping */
914     #define OPTION_IO_MAPPED	0x1000  /* NCR registers have valid
915     					     I/O mapping */
916     #define OPTION_DEBUG_PROBE_ONLY	0x2000  /* Probe only, don't even init */
917     #define OPTION_DEBUG_TESTS_ONLY	0x4000  /* Probe, init, run selected tests */
918     #define OPTION_DEBUG_TEST0	0x08000 /* Run test 0 */
919     #define OPTION_DEBUG_TEST1	0x10000 /* Run test 1 */
920     #define OPTION_DEBUG_TEST2	0x20000 /* Run test 2 */
921     #define OPTION_DEBUG_DUMP	0x40000 /* Dump commands */
922     #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
923     #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
924     #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
925     #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
926     #define OPTION_DEBUG_DSA 0x800000
927     #define OPTION_DEBUG_CORRUPTION	0x1000000	/* Detect script corruption */
928     #define OPTION_DEBUG_SDTR       0x2000000	/* Debug SDTR problem */
929     #define OPTION_DEBUG_MISMATCH 	0x4000000 	/* Debug phase mismatches */
930     #define OPTION_DISCONNECT	0x8000000	/* Allow disconnect */
931     #define OPTION_DEBUG_DISCONNECT 0x10000000	
932     #define OPTION_ALWAYS_SYNCHRONOUS 0x20000000	/* Negotiate sync. transfers
933     						   on power up */
934     #define OPTION_DEBUG_QUEUES	0x80000000	
935     #define OPTION_DEBUG_ALLOCATION 0x100000000LL
936     #define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL	/* Sanity check SXFER and 
937     						   SCNTL3 registers */
938     #define OPTION_NO_ASYNC	0x400000000LL		/* Don't automagically send
939     						   SDTR for async transfers when
940     						   we haven't been told to do
941     						   a synchronous transfer. */
942     #define OPTION_NO_PRINT_RACE 0x800000000LL	/* Don't print message when
943     						   the reselect/WAIT DISCONNECT
944     						   race condition hits */
945     #if !defined(PERM_OPTIONS)
946     #define PERM_OPTIONS 0
947     #endif
948     				
949     struct NCR53c7x0_synchronous {
950         u32 select_indirect;		/* Value used for indirect selection */
951         u32 script[8];			/* Size ?? Script used when target is 
952     						reselected */
953         unsigned char synchronous_want[5];	/* Per target desired SDTR */
954     /* 
955      * Set_synchronous programs these, select_indirect and current settings after
956      * int_debug_should show a match.
957      */
958         unsigned char sxfer_sanity, scntl3_sanity;
959     };
960     
961     #define CMD_FLAG_SDTR 		1	/* Initiating synchronous 
962     					   transfer negotiation */
963     #define CMD_FLAG_WDTR		2	/* Initiating wide transfer
964     					   negotiation */
965     #define CMD_FLAG_DID_SDTR	4	/* did SDTR */
966     #define CMD_FLAG_DID_WDTR	8	/* did WDTR */
967     
968     struct NCR53c7x0_table_indirect {
969         u32 count;
970         void *address;
971     };
972     
973     enum ncr_event { 
974         EVENT_NONE = 0,
975     /* 
976      * Order is IMPORTANT, since these must correspond to the event interrupts
977      * in 53c7,8xx.scr 
978      */
979     
980         EVENT_ISSUE_QUEUE = 0x5000000,	/* Command was added to issue queue */
981         EVENT_START_QUEUE,			/* Command moved to start queue */
982         EVENT_SELECT,			/* Command completed selection */
983         EVENT_DISCONNECT,			/* Command disconnected */
984         EVENT_RESELECT,			/* Command reselected */
985         EVENT_COMPLETE,		        /* Command completed */
986         EVENT_IDLE,
987         EVENT_SELECT_FAILED,
988         EVENT_BEFORE_SELECT,
989         EVENT_RESELECT_FAILED
990     };
991     
992     struct NCR53c7x0_event {
993         enum ncr_event event;	/* What type of event */
994         unsigned char target;
995         unsigned char lun;
996         struct timeval time;	
997         u32 *dsa;			/* What's in the DSA register now (virt) */
998     /* 
999      * A few things from that SCSI pid so we know what happened after 
1000      * the Scsi_Cmnd structure in question may have disappeared.
1001      */
1002         unsigned long pid;		/* The SCSI PID which caused this 
1003     				   event */
1004         unsigned char cmnd[12];
1005     };
1006     
1007     /*
1008      * Things in the NCR53c7x0_cmd structure are split into two parts :
1009      *
1010      * 1.  A fixed portion, for things which are not accessed directly by static NCR
1011      *	code (ie, are referenced only by the Linux side of the driver,
1012      *	or only by dynamically generated code).  
1013      *
1014      * 2.  The DSA portion, for things which are accessed directly by static NCR
1015      *	code.
1016      *
1017      * This is a little ugly, but it 
1018      * 1.  Avoids conflicts between the NCR code's picture of the structure, and 
1019      * 	Linux code's idea of what it looks like.
1020      *
1021      * 2.  Minimizes the pain in the Linux side of the code needed 
1022      * 	to calculate real dsa locations for things, etc.
1023      * 
1024      */
1025     
1026     struct NCR53c7x0_cmd {
1027         void *real;				/* Real, unaligned address for
1028     					   free function */
1029         void (* free)(void *, int);		/* Command to deallocate; NULL
1030     					   for structures allocated with
1031     					   scsi_register, etc. */
1032         Scsi_Cmnd *cmd;			/* Associated Scsi_Cmnd 
1033     					   structure, Scsi_Cmnd points
1034     					   at NCR53c7x0_cmd using 
1035     					   host_scribble structure */
1036     
1037         int size;				/* scsi_malloc'd size of this 
1038     					   structure */
1039     
1040         int flags;				/* CMD_* flags */
1041     
1042     /*
1043      * SDTR and WIDE messages are an either/or affair
1044      * in this message, since we will go into message out and send
1045      * _the whole mess_ without dropping out of message out to 
1046      * let the target go into message in after sending the first 
1047      * message.
1048      */
1049     
1050         unsigned char select[11];		/* Select message, includes
1051     					   IDENTIFY
1052     					   (optional) QUEUE TAG
1053      				 	   (optional) SDTR or WDTR
1054     					 */
1055     
1056     
1057         volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free,
1058     					    running, eventually finished */
1059         					 
1060     
1061         u32 *data_transfer_start;		/* Start of data transfer routines */
1062         u32 *data_transfer_end;		/* Address after end of data transfer o
1063         	    	    	    	    	   routines */
1064     /* 
1065      * The following three fields were moved from the DSA proper to here
1066      * since only dynamically generated NCR code refers to them, meaning
1067      * we don't need dsa_* absolutes, and it is simpler to let the 
1068      * host code refer to them directly.
1069      */
1070     
1071     /* 
1072      * HARD CODED : residual and saved_residual need to agree with the sizes
1073      * used in NCR53c7,8xx.scr.  
1074      * 
1075      * FIXME: we want to consider the case where we have odd-length 
1076      *	scatter/gather buffers and a WIDE transfer, in which case 
1077      *	we'll need to use the CHAIN MOVE instruction.  Ick.
1078      */
1079         u32 residual[6];			/* Residual data transfer which
1080     					   allows pointer code to work
1081     					   right.
1082     
1083         	    	    	    	    	    [0-1] : Conditional call to 
1084         	    	    	    	    	    	appropriate other transfer 
1085         	    	    	    	    	    	routine.
1086         	    	    	    	    	    [2-3] : Residual block transfer
1087         	    	    	    	    	    	instruction.
1088         	    	    	    	    	    [4-5] : Jump to instruction
1089         	    	    	    	    	    	after splice.
1090     					 */
1091         u32 saved_residual[6]; 		/* Copy of old residual, so we 
1092     					   can get another partial 
1093     					   transfer and still recover 
1094         	    	    	    	    	 */
1095         	    	
1096         u32 saved_data_pointer;		/* Saved data pointer */
1097     
1098         u32 dsa_next_addr;		        /* _Address_ of dsa_next field  
1099     					   in this dsa for RISCy 
1100     					   style constant. */
1101     
1102         u32 dsa_addr;			/* Address of dsa; RISCy style
1103     					   constant */
1104     
1105         u32 dsa[0];				/* Variable length (depending
1106     					   on host type, number of scatter /
1107     					   gather buffers, etc).  */
1108     };
1109     
1110     struct NCR53c7x0_break {
1111         u32 *address, old_instruction[2];
1112         struct NCR53c7x0_break *next;
1113         unsigned char old_size;		/* Size of old instruction */
1114     };
1115     
1116     /* Indicates that the NCR is not executing code */
1117     #define STATE_HALTED	0		
1118     /* 
1119      * Indicates that the NCR is executing the wait for select / reselect 
1120      * script.  Only used when running NCR53c700 compatible scripts, only 
1121      * state during which an ABORT is _not_ considered an error condition.
1122      */
1123     #define STATE_WAITING	1		
1124     /* Indicates that the NCR is executing other code. */
1125     #define STATE_RUNNING	2		
1126     /* 
1127      * Indicates that the NCR was being aborted.
1128      */
1129     #define STATE_ABORTING	3
1130     /* Indicates that the NCR was successfully aborted. */
1131     #define STATE_ABORTED 4
1132     /* Indicates that the NCR has been disabled due to a fatal error */
1133     #define STATE_DISABLED 5
1134     
1135     /* 
1136      * Where knowledge of SCSI SCRIPT(tm) specified values are needed 
1137      * in an interrupt handler, an interrupt handler exists for each 
1138      * different SCSI script so we don't have name space problems.
1139      * 
1140      * Return values of these handlers are as follows : 
1141      */
1142     #define SPECIFIC_INT_NOTHING 	0	/* don't even restart */
1143     #define SPECIFIC_INT_RESTART	1	/* restart at the next instruction */
1144     #define SPECIFIC_INT_ABORT	2	/* recoverable error, abort cmd */
1145     #define SPECIFIC_INT_PANIC	3	/* unrecoverable error, panic */
1146     #define SPECIFIC_INT_DONE	4	/* normal command completion */
1147     #define SPECIFIC_INT_BREAK	5	/* break point encountered */
1148     
1149     struct NCR53c7x0_hostdata {
1150         int size;				/* Size of entire Scsi_Host
1151     					   structure */
1152         int board;				/* set to board type, useful if 
1153     					   we have host specific things,
1154     					   ie, a general purpose I/O 
1155     					   bit is being used to enable
1156     					   termination, etc. */
1157     
1158         int chip;				/* set to chip type; 700-66 is
1159     					   700-66, rest are last three
1160     					   digits of part number */
1161         /*
1162          * PCI bus, device, function, only for NCR53c8x0 chips.
1163          * pci_valid indicates that the PCI configuration information
1164          * is valid, and we can twiddle MAX_LAT, etc. as recommended
1165          * for maximum performance in the NCR documentation.
1166          */
1167         unsigned char pci_bus, pci_device_fn;
1168         unsigned pci_valid:1;
1169     
1170         u32 *dsp;				/* dsp to restart with after
1171     					   all stacked interrupts are
1172     					   handled. */
1173     
1174         unsigned dsp_changed:1;		/* Has dsp changed within this
1175     					   set of stacked interrupts ? */
1176     
1177         unsigned char dstat;		/* Most recent value of dstat */
1178         unsigned dstat_valid:1;
1179     
1180         unsigned expecting_iid:1;		/* Expect IID interrupt */
1181         unsigned expecting_sto:1;		/* Expect STO interrupt */
1182         
1183         /* 
1184          * The code stays cleaner if we use variables with function
1185          * pointers and offsets that are unique for the different
1186          * scripts rather than having a slew of switch(hostdata->chip) 
1187          * statements.
1188          * 
1189          * It also means that the #defines from the SCSI SCRIPTS(tm)
1190          * don't have to be visible outside of the script-specific
1191          * instructions, preventing name space pollution.
1192          */
1193     
1194         void (* init_fixup)(struct Scsi_Host *host);
1195         void (* init_save_regs)(struct Scsi_Host *host);
1196         void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1197         void (* soft_reset)(struct Scsi_Host *host);
1198         int (* run_tests)(struct Scsi_Host *host);
1199     
1200         /*
1201          * Called when DSTAT_SIR is set, indicating an interrupt generated
1202          * by the INT instruction, where values are unique for each SCSI
1203          * script.  Should return one of the SPEC_* values.
1204          */
1205     
1206         int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1207     
1208         int dsa_len; /* Size of DSA structure */
1209     
1210         /*
1211          * Location of DSA fields for the SCSI SCRIPT corresponding to this 
1212          * chip.  
1213          */
1214     
1215         s32 dsa_start;			
1216         s32 dsa_end;			
1217         s32 dsa_next;
1218         s32 dsa_prev;
1219         s32 dsa_cmnd;
1220         s32 dsa_select;
1221         s32 dsa_msgout;
1222         s32 dsa_cmdout;
1223         s32 dsa_dataout;
1224         s32 dsa_datain;
1225         s32 dsa_msgin;
1226         s32 dsa_msgout_other;
1227         s32 dsa_write_sync;
1228         s32 dsa_write_resume;
1229         s32 dsa_check_reselect;
1230         s32 dsa_status;
1231         s32 dsa_saved_pointer;
1232         s32 dsa_jump_dest;
1233     
1234         /* 
1235          * Important entry points that generic fixup code needs
1236          * to know about, fixed up.
1237          */
1238     
1239         s32 E_accept_message;
1240         s32 E_command_complete;		
1241         s32 E_data_transfer;
1242         s32 E_dsa_code_template;
1243         s32 E_dsa_code_template_end;
1244         s32 E_end_data_transfer;
1245         s32 E_msg_in;
1246         s32 E_initiator_abort;
1247         s32 E_other_transfer;
1248         s32 E_other_in;
1249         s32 E_other_out;
1250         s32 E_target_abort;
1251         s32 E_debug_break;	
1252         s32 E_reject_message;
1253         s32 E_respond_message;
1254         s32 E_select;
1255         s32 E_select_msgout;
1256         s32 E_test_0;
1257         s32 E_test_1;
1258         s32 E_test_2;
1259         s32 E_test_3;
1260         s32 E_dsa_zero;
1261         s32 E_cmdout_cmdout;
1262         s32 E_wait_reselect;
1263         s32 E_dsa_code_begin;
1264     
1265         long long options;			/* Bitfielded set of options enabled */
1266         volatile u32 test_completed;	/* Test completed */
1267         int test_running;			/* Test currently running */
1268         s32 test_source;
1269         volatile s32 test_dest;
1270     
1271         volatile int state;			/* state of driver, only used for 
1272     					   OPTION_700 */
1273     
1274         unsigned char  dmode;		/* 
1275     					 * set to the address of the DMODE 
1276     					 * register for this chip.
1277     					 */
1278         unsigned char istat;		/* 
1279         	    	    	    	    	 * set to the address of the ISTAT 
1280         	    	    	    	    	 * register for this chip.
1281         	    	    	    	    	 */
1282       
1283         int scsi_clock;			/* 
1284     					 * SCSI clock in HZ. 0 may be used 
1285     					 * for unknown, although this will
1286     					 * disable synchronous negotiation.
1287     					 */
1288     
1289         volatile int intrs;			/* Number of interrupts */
1290         volatile int resets;		/* Number of SCSI resets */
1291         unsigned char saved_dmode;	
1292         unsigned char saved_ctest4;
1293         unsigned char saved_ctest7;
1294         unsigned char saved_dcntl;
1295         unsigned char saved_scntl3;
1296     
1297         unsigned char this_id_mask;
1298     
1299         /* Debugger information */
1300         struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1301     	*breakpoint_current;		/* Current breakpoint being stepped 
1302     					   through, NULL if we are running 
1303     					   normally. */
1304     #ifdef NCR_DEBUG
1305         int debug_size;			/* Size of debug buffer */
1306         volatile int debug_count;		/* Current data count */
1307         volatile char *debug_buf;		/* Output ring buffer */
1308         volatile char *debug_write;		/* Current write pointer */
1309         volatile char *debug_read;		/* Current read pointer */
1310     #endif /* def NCR_DEBUG */
1311     
1312         /* XXX - primitive debugging junk, remove when working ? */
1313         int debug_print_limit;		/* Number of commands to print
1314     					   out exhaustive debugging
1315     					   information for if 
1316     					   OPTION_DEBUG_DUMP is set */ 
1317     
1318         unsigned char debug_lun_limit[16];	/* If OPTION_DEBUG_TARGET_LIMIT
1319     					   set, puke if commands are sent
1320     					   to other target/lun combinations */
1321     
1322         int debug_count_limit;		/* Number of commands to execute
1323     					   before puking to limit debugging 
1324     					   output */
1325     				    
1326     
1327         volatile unsigned idle:1;			/* set to 1 if idle */
1328     
1329         /* 
1330          * Table of synchronous+wide transfer parameters set on a per-target
1331          * basis.
1332          */
1333         
1334         volatile struct NCR53c7x0_synchronous sync[16];
1335     
1336         volatile Scsi_Cmnd *issue_queue;
1337     						/* waiting to be issued by
1338     						   Linux driver */
1339         volatile struct NCR53c7x0_cmd *running_list;	
1340     						/* commands running, maintained
1341     						   by Linux driver */
1342     
1343         volatile struct NCR53c7x0_cmd *curr;	/* currently connected 
1344     						   nexus, ONLY valid for
1345     						   NCR53c700/NCR53c700-66
1346     						 */
1347     
1348         volatile struct NCR53c7x0_cmd *spare;	/* pointer to spare,
1349         	    	    	    	    	    	   allocated at probe time,
1350         	    	    	    	    	    	   which we can use for 
1351     						   initialization */
1352         volatile struct NCR53c7x0_cmd *free;
1353         int max_cmd_size;				/* Maximum size of NCR53c7x0_cmd
1354     					    	   based on number of 
1355     						   scatter/gather segments, etc.
1356     						   */
1357         volatile int num_cmds;			/* Number of commands 
1358     						   allocated */
1359         volatile int extra_allocate;
1360         volatile unsigned char cmd_allocated[16];	/* Have we allocated commands
1361     						   for this target yet?  If not,
1362     						   do so ASAP */
1363         volatile unsigned char busy[16][8];     	/* number of commands 
1364     						   executing on each target
1365         	    	    	    	    	    	 */
1366         /* 
1367          * Eventually, I'll switch to a coroutine for calling 
1368          * cmd->done(cmd), etc. so that we can overlap interrupt
1369          * processing with this code for maximum performance.
1370          */
1371         
1372         volatile struct NCR53c7x0_cmd *finished_queue;	
1373     						
1374     
1375         /* Shared variables between SCRIPT and host driver */
1376         volatile u32 *schedule;			/* Array of JUMPs to dsa_begin
1377     						   routines of various DSAs.  
1378     						   When not in use, replace
1379     						   with jump to next slot */
1380     
1381     
1382         volatile unsigned char msg_buf[16];		/* buffer for messages
1383     						   other than the command
1384     						   complete message */
1385     
1386         /* Per-target default synchronous and WIDE messages */
1387         volatile unsigned char synchronous_want[16][5];
1388         volatile unsigned char wide_want[16][4];
1389     
1390         /* Bit fielded set of targets we want to speak synchronously with */ 
1391         volatile u16 initiate_sdtr;	
1392         /* Bit fielded set of targets we want to speak wide with */
1393         volatile u16 initiate_wdtr;
1394         /* Bit fielded list of targets we've talked to. */
1395         volatile u16 talked_to;
1396     
1397         /* Array of bit-fielded lun lists that we need to request_sense */
1398         volatile unsigned char request_sense[16];
1399     
1400         u32 addr_reconnect_dsa_head;		/* RISCy style constant,
1401     						   address of following */
1402         volatile u32 reconnect_dsa_head;	
1403         /* Data identifying nexus we are trying to match during reselection */
1404         volatile unsigned char reselected_identify; /* IDENTIFY message */
1405         volatile unsigned char reselected_tag;	/* second byte of queue tag 
1406     						   message or 0 */
1407         /* These were static variables before we moved them */
1408     
1409         s32 NCR53c7xx_zero;
1410         s32 NCR53c7xx_sink;
1411         u32 NOP_insn;
1412         char NCR53c7xx_msg_reject;
1413         char NCR53c7xx_msg_abort;
1414         char NCR53c7xx_msg_nop;
1415     
1416         volatile int event_size, event_index;
1417         volatile struct NCR53c7x0_event *events;
1418     
1419         /* If we need to generate code to kill off the currently connected 
1420            command, this is where we do it. Should have a BMI instruction
1421            to source or sink the current data, followed by a JUMP
1422            to abort_connected */
1423     
1424         u32 *abort_script;
1425     
1426         int script_count;				/* Size of script in words */
1427         u32 script[0];				/* Relocated SCSI script */
1428     
1429     };
1430     
1431     #define IRQ_NONE	255
1432     #define DMA_NONE	255
1433     #define IRQ_AUTO	254
1434     #define DMA_AUTO	254
1435     
1436     #define BOARD_GENERIC	0
1437     
1438     #define NCR53c7x0_insn_size(insn)					\
1439         (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1440         
1441     
1442     #define NCR53c7x0_local_declare()					\
1443         volatile unsigned char *NCR53c7x0_address_memory;			\
1444         unsigned int NCR53c7x0_address_io;					\
1445         int NCR53c7x0_memory_mapped
1446     
1447     #define NCR53c7x0_local_setup(host)					\
1448         NCR53c7x0_address_memory = (void *) (host)->base;			\
1449         NCR53c7x0_address_io = (unsigned int) (host)->io_port;		\
1450         NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) 		\
1451     	host->hostdata)-> options & OPTION_MEMORY_MAPPED 
1452     
1453     #define NCR53c7x0_read8(address) 					\
1454         (NCR53c7x0_memory_mapped ? 						\
1455     	(unsigned int)readb(NCR53c7x0_address_memory + (address)) :	\
1456     	inb(NCR53c7x0_address_io + (address)))
1457     
1458     #define NCR53c7x0_read16(address) 					\
1459         (NCR53c7x0_memory_mapped ? 						\
1460     	(unsigned int)readw(NCR53c7x0_address_memory + (address)) :	\
1461     	inw(NCR53c7x0_address_io + (address)))
1462     
1463     #define NCR53c7x0_read32(address) 					\
1464         (NCR53c7x0_memory_mapped ? 						\
1465     	(unsigned int) readl(NCR53c7x0_address_memory + (address)) : 	\
1466     	inl(NCR53c7x0_address_io + (address)))
1467     
1468     #define NCR53c7x0_write8(address,value) 				\
1469         (NCR53c7x0_memory_mapped ? 						\
1470          ({writeb((value), NCR53c7x0_address_memory + (address)); mb();}) :	\
1471     	outb((value), NCR53c7x0_address_io + (address)))
1472     
1473     #define NCR53c7x0_write16(address,value) 				\
1474         (NCR53c7x0_memory_mapped ? 						\
1475          ({writew((value), NCR53c7x0_address_memory + (address)); mb();}) :	\
1476     	outw((value), NCR53c7x0_address_io + (address)))
1477     
1478     #define NCR53c7x0_write32(address,value) 				\
1479         (NCR53c7x0_memory_mapped ? 						\
1480          ({writel((value), NCR53c7x0_address_memory + (address)); mb();}) :	\
1481     	outl((value), NCR53c7x0_address_io + (address)))
1482     
1483     /* Patch arbitrary 32 bit words in the script */
1484     #define patch_abs_32(script, offset, symbol, value)			\
1485         	for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof 		\
1486         	    (u32)); ++i) {					\
1487     	    (script)[A_##symbol##_used[i] - (offset)] += (value);	\
1488     	    if (hostdata->options & OPTION_DEBUG_FIXUP) 		\
1489     	      printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1490     		host->host_no, #symbol, i, A_##symbol##_used[i] - 	\
1491     		(int)(offset), #script, (script)[A_##symbol##_used[i] -	\
1492     		(offset)]);						\
1493         	}
1494     
1495     /* Patch read/write instruction immediate field */
1496     #define patch_abs_rwri_data(script, offset, symbol, value)		\
1497         	for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof 		\
1498         	    (u32)); ++i)					\
1499         	    (script)[A_##symbol##_used[i] - (offset)] =			\
1500     	    	((script)[A_##symbol##_used[i] - (offset)] & 		\
1501     	    	~DBC_RWRI_IMMEDIATE_MASK) | 				\
1502         	    	(((value) << DBC_RWRI_IMMEDIATE_SHIFT) &		\
1503     		 DBC_RWRI_IMMEDIATE_MASK)
1504     
1505     /* Patch transfer control instruction data field */
1506     #define patch_abs_tci_data(script, offset, symbol, value)	        \
1507         	for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof 		\
1508         	    (u32)); ++i)					\
1509         	    (script)[A_##symbol##_used[i] - (offset)] =			\
1510     	    	((script)[A_##symbol##_used[i] - (offset)] & 		\
1511     	    	~DBC_TCI_DATA_MASK) | 					\
1512         	    	(((value) << DBC_TCI_DATA_SHIFT) &			\
1513     		 DBC_TCI_DATA_MASK)
1514     
1515     /* Patch field in dsa structure (assignment should be +=?) */
1516     #define patch_dsa_32(dsa, symbol, word, value)				\
1517     	{								\
1518     	(dsa)[(hostdata->symbol - hostdata->dsa_start) / sizeof(u32)	\
1519     	    + (word)] = (value);					\
1520     	if (hostdata->options & OPTION_DEBUG_DSA)			\
1521     	    printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n",	\
1522     		#dsa, #symbol, hostdata->symbol, 			\
1523     		(word), (u32) le32_to_cpu(value));			\
1524     	}
1525     
1526     /* Paranoid people could use panic() here. */
1527     #define FATAL(host) shutdown((host));
1528     
1529     #endif /* NCR53c7x0_C */
1530     #endif /* NCR53c7x0_H */
1531